Return the entire comparison expression, not just the cc_reg.
This will allow the routine to adjust the comparison code as
needed for TImode comparisons.
Note that some users were passing e.g. EQ to aarch64_gen_compare_reg
and then using gen_rtx_NE. Pass the proper code in the first place.
* config/aarch64/aarch64.c (aarch64_gen_compare_reg): Return
the final comparison for code & cc_reg.
(aarch64_gen_compare_reg_maybe_ze): Likewise.
(aarch64_expand_compare_and_swap): Update to match -- do not
build the final comparison here, but PUT_MODE as necessary.
(aarch64_split_compare_and_swap): Use prebuilt comparison.
* config/aarch64/aarch64-simd.md (aarch64_cm<COMPARISONS>di): Likewise.
(aarch64_cm<UCOMPARISONS>di): Likewise.
(aarch64_cmtstdi): Likewise.
* config/aarch64/aarch64-speculation.cc
(aarch64_speculation_establish_tracker): Likewise.
* config/aarch64/aarch64.md (cbranch<GPI>4, cbranch<GPF>4): Likewise.
(mod<GPI>3, abs<GPI>2): Likewise.
(cstore<GPI>4, cstore<GPF>4): Likewise.
(cmov<GPI>6, cmov<GPF>6): Likewise.
(mov<ALLI>cc, mov<GPF><GPI>cc, mov<GPF>cc): Likewise.
(<NEG_NOT><GPI>cc): Likewise.
(ffs<GPI>2): Likewise.
(cstorecc4): Remove redundant "".
---
gcc/config/aarch64/aarch64.c | 26 +++---
gcc/config/aarch64/aarch64-simd.md | 18 ++---
gcc/config/aarch64/aarch64-speculation.cc | 5 +-
gcc/config/aarch64/aarch64.md | 96 ++++++++++-------------
4 files changed, 63 insertions(+), 82 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 8e54506bc3e..93658338041 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -2328,7 +2328,7 @@ emit_set_insn (rtx x, rtx y)
}
/* X and Y are two things to compare using CODE. Emit the compare insn and
- return the rtx for register 0 in the proper mode. */
+ return the rtx for the CCmode comparison. */
rtx
aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y)
{
@@ -2359,7 +2359,7 @@ aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y)
cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM);
emit_set_insn (cc_reg, gen_rtx_COMPARE (cc_mode, x, y));
}
- return cc_reg;
+ return gen_rtx_fmt_ee (code, VOIDmode, cc_reg, const0_rtx);
}
/* Similarly, but maybe zero-extend Y if Y_MODE < SImode. */
@@ -2382,7 +2382,7 @@ aarch64_gen_compare_reg_maybe_ze (RTX_CODE code, rtx x,
rtx y,
cc_mode = CC_SWPmode;
cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM);
emit_set_insn (cc_reg, t);
- return cc_reg;
+ return gen_rtx_fmt_ee (code, VOIDmode, cc_reg, const0_rtx);
}
}
@@ -18487,7 +18487,8 @@ aarch64_expand_compare_and_swap (rtx operands[])
emit_insn (gen_aarch64_compare_and_swap_lse (mode, rval, mem,
newval, mod_s));
- cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
+ x = aarch64_gen_compare_reg_maybe_ze (EQ, rval, oldval, mode);
+ PUT_MODE (x, SImode);
}
else if (TARGET_OUTLINE_ATOMICS)
{
@@ -18498,7 +18499,8 @@ aarch64_expand_compare_and_swap (rtx operands[])
rval = emit_library_call_value (func, NULL_RTX, LCT_NORMAL, r_mode,
oldval, mode, newval, mode,
XEXP (mem, 0), Pmode);
- cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
+ x = aarch64_gen_compare_reg_maybe_ze (EQ, rval, oldval, mode);
+ PUT_MODE (x, SImode);
}
else
{
@@ -18510,13 +18512,13 @@ aarch64_expand_compare_and_swap (rtx operands[])
emit_insn (GEN_FCN (code) (rval, mem, oldval, newval,
is_weak, mod_s, mod_f));
cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
+ x = gen_rtx_EQ (SImode, cc_reg, const0_rtx);
}
if (r_mode != mode)
rval = gen_lowpart (mode, rval);
emit_move_insn (operands[1], rval);
- x = gen_rtx_EQ (SImode, cc_reg, const0_rtx);
emit_insn (gen_rtx_SET (bval, x));
}
@@ -18591,10 +18593,8 @@ aarch64_split_compare_and_swap (rtx operands[])
if (strong_zero_p)
x = gen_rtx_NE (VOIDmode, rval, const0_rtx);
else
- {
- rtx cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
- x = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
- }
+ x = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
+
x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
@@ -18607,8 +18607,7 @@ aarch64_split_compare_and_swap (rtx operands[])
{
/* Emit an explicit compare instruction, so that we can correctly
track the condition codes. */
- rtx cc_reg = aarch64_gen_compare_reg (NE, scratch, const0_rtx);
- x = gen_rtx_NE (GET_MODE (cc_reg), cc_reg, const0_rtx);
+ x = aarch64_gen_compare_reg (NE, scratch, const0_rtx);
}
else
x = gen_rtx_NE (VOIDmode, scratch, const0_rtx);
@@ -18703,8 +18702,7 @@ aarch64_split_atomic_op (enum rtx_code code, rtx
old_out, rtx new_out, rtx mem,
{
/* Emit an explicit compare instruction, so that we can correctly
track the condition codes. */
- rtx cc_reg = aarch64_gen_compare_reg (NE, cond, const0_rtx);
- x = gen_rtx_NE (GET_MODE (cc_reg), cc_reg, const0_rtx);
+ x = aarch64_gen_compare_reg (NE, cond, const0_rtx);
}
else
x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 24a11fb5040..69e099a2c23 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4800,10 +4800,8 @@
if (GP_REGNUM_P (REGNO (operands[0]))
&& GP_REGNUM_P (REGNO (operands[1])))
{
- machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]);
- rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);
- rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);
- emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
+ rtx cmp = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);
+ emit_insn (gen_cstoredi_neg (operands[0], cmp, XEXP (cmp, 0)));
DONE;
}
/* Otherwise, we expand to a similar pattern which does not
@@ -4863,10 +4861,8 @@
if (GP_REGNUM_P (REGNO (operands[0]))
&& GP_REGNUM_P (REGNO (operands[1])))
{
- machine_mode mode = CCmode;
- rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);
- rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);
- emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
+ rtx cmp = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);
+ emit_insn (gen_cstoredi_neg (operands[0], cmp, XEXP (cmp, 0)));
DONE;
}
/* Otherwise, we expand to a similar pattern which does not
@@ -4936,10 +4932,8 @@
&& GP_REGNUM_P (REGNO (operands[1])))
{
rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]);
- machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx);
- rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx);
- rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx);
- emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
+ rtx cmp = aarch64_gen_compare_reg (NE, and_tree, const0_rtx);
+ emit_insn (gen_cstoredi_neg (operands[0], cmp, XEXP (cmp, 0)));
DONE;
}
/* Otherwise, we expand to a similar pattern which does not
diff --git a/gcc/config/aarch64/aarch64-speculation.cc
b/gcc/config/aarch64/aarch64-speculation.cc
index f490b64ae61..87d5964871b 100644
--- a/gcc/config/aarch64/aarch64-speculation.cc
+++ b/gcc/config/aarch64/aarch64-speculation.cc
@@ -162,9 +162,8 @@ aarch64_speculation_establish_tracker ()
rtx sp = gen_rtx_REG (DImode, SP_REGNUM);
rtx tracker = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM);
start_sequence ();
- rtx cc = aarch64_gen_compare_reg (EQ, sp, const0_rtx);
- emit_insn (gen_cstoredi_neg (tracker,
- gen_rtx_NE (CCmode, cc, const0_rtx), cc));
+ rtx x = aarch64_gen_compare_reg (NE, sp, const0_rtx);
+ emit_insn (gen_cstoredi_neg (tracker, x, XEXP (x, 0)));
rtx_insn *seq = get_insns ();
end_sequence ();
return seq;
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index c11c4366bf9..dbaeb7c251c 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -466,12 +466,12 @@
(label_ref (match_operand 3 "" ""))
(pc)))]
""
- "
- operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
+{
+ operands[0] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
operands[2]);
+ operands[1] = XEXP (operands[0], 0);
operands[2] = const0_rtx;
- "
-)
+})
(define_expand "cbranch<mode>4"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
@@ -480,12 +480,12 @@
(label_ref (match_operand 3 "" ""))
(pc)))]
""
- "
- operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
+{
+ operands[0] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
operands[2]);
+ operands[1] = XEXP (operands[0], 0);
operands[2] = const0_rtx;
- "
-)
+})
(define_expand "cbranchcc4"
[(set (pc) (if_then_else
@@ -600,9 +600,8 @@
if (val == 2)
{
rtx masked = gen_reg_rtx (<MODE>mode);
- rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
+ rtx x = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
emit_insn (gen_and<mode>3 (masked, operands[1], mask));
- rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
emit_insn (gen_csneg3<mode>_insn (operands[0], x, masked, masked));
DONE;
}
@@ -3502,8 +3501,7 @@
(match_operand:GPI 1 "register_operand")]
""
{
- rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
- rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
+ rtx x = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
emit_insn (gen_csneg3<mode>_insn (operands[0], x, operands[1],
operands[1]));
DONE;
}
@@ -3917,12 +3915,13 @@
[(match_operand:GPI 2 "register_operand")
(match_operand:GPI 3 "aarch64_plus_operand")]))]
""
- "
- operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
- operands[3]);
+{
+ operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
+ operands[3]);
+ PUT_MODE (operands[1], SImode);
+ operands[2] = XEXP (operands[1], 0);
operands[3] = const0_rtx;
- "
-)
+})
(define_expand "cstorecc4"
[(set (match_operand:SI 0 "register_operand")
@@ -3930,11 +3929,10 @@
[(match_operand 2 "cc_register")
(match_operand 3 "const0_operand")]))]
""
-"{
+{
emit_insn (gen_rtx_SET (operands[0], operands[1]));
DONE;
-}")
-
+})
(define_expand "cstore<mode>4"
[(set (match_operand:SI 0 "register_operand")
@@ -3942,12 +3940,13 @@
[(match_operand:GPF 2 "register_operand")
(match_operand:GPF 3 "aarch64_fp_compare_operand")]))]
""
- "
- operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
- operands[3]);
+{
+ operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
+ operands[3]);
+ PUT_MODE (operands[1], SImode);
+ operands[2] = XEXP (operands[1], 0);
operands[3] = const0_rtx;
- "
-)
+})
(define_insn "aarch64_cstore<mode>"
[(set (match_operand:ALLI 0 "register_operand" "=r")
@@ -4033,12 +4032,12 @@
(match_operand:GPI 4 "register_operand")
(match_operand:GPI 5 "register_operand")))]
""
- "
- operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
- operands[3]);
+{
+ operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
+ operands[3]);
+ operands[2] = XEXP (operands[1], 0);
operands[3] = const0_rtx;
- "
-)
+})
(define_expand "cmov<mode>6"
[(set (match_operand:GPF 0 "register_operand")
@@ -4049,12 +4048,12 @@
(match_operand:GPF 4 "register_operand")
(match_operand:GPF 5 "register_operand")))]
""
- "
- operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
- operands[3]);
+{
+ operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
+ operands[3]);
+ operands[2] = XEXP (operands[1], 0);
operands[3] = const0_rtx;
- "
-)
+})
(define_insn "*cmov<mode>_insn"
[(set (match_operand:ALLI 0 "register_operand" "=r,r,r,r,r,r,r")
@@ -4131,15 +4130,13 @@
(match_operand:ALLI 3 "register_operand")))]
""
{
- rtx ccreg;
enum rtx_code code = GET_CODE (operands[1]);
if (code == UNEQ || code == LTGT)
FAIL;
- ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
- XEXP (operands[1], 1));
- operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+ operands[1] = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
+ XEXP (operands[1], 1));
}
)
@@ -4150,15 +4147,13 @@
(match_operand:GPF 3 "register_operand")))]
""
{
- rtx ccreg;
enum rtx_code code = GET_CODE (operands[1]);
if (code == UNEQ || code == LTGT)
FAIL;
- ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
- XEXP (operands[1], 1));
- operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+ operands[1] = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
+ XEXP (operands[1], 1));
}
)
@@ -4169,15 +4164,13 @@
(match_operand:GPF 3 "register_operand")))]
""
{
- rtx ccreg;
enum rtx_code code = GET_CODE (operands[1]);
if (code == UNEQ || code == LTGT)
FAIL;
- ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
- XEXP (operands[1], 1));
- operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+ operands[1] = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
+ XEXP (operands[1], 1));
}
)
@@ -4188,15 +4181,13 @@
(match_operand:GPI 3 "register_operand")))]
""
{
- rtx ccreg;
enum rtx_code code = GET_CODE (operands[1]);
if (code == UNEQ || code == LTGT)
FAIL;
- ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
- XEXP (operands[1], 1));
- operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+ operands[1] = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
+ XEXP (operands[1], 1));
}
)
@@ -4705,8 +4696,7 @@
(match_operand:GPI 1 "register_operand")]
""
{
- rtx ccreg = aarch64_gen_compare_reg (EQ, operands[1], const0_rtx);
- rtx x = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
+ rtx x = aarch64_gen_compare_reg (NE, operands[1], const0_rtx);
emit_insn (gen_rbit<mode>2 (operands[0], operands[1]));
emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
--
2.20.1
