On Fri, Jun 28, 2019 at 10:56 AM Jan Beulich wrote:
>
> There's no need for three alternatives: "v" without TARGET_AVX512F is
> the same as "x".
>
> gcc/
> 2019-06-28 Jan Beulich
>
> * config/i386/sse.md (vgf2p8affineinvqb_,
> vgf2p8affineqb_): Eliminate redundant
> alternative.
Please also mention vgf2p8mulb_ in the ChangeLog.
OK with the above change.
> ---
> v2: New, split off from previous bigger patch.
> ---
> In fact I doubt two alternatives are necessary, seeing how other insns
> get away with just one. But I'm not bothered enough to try to actually
> get this right.
You need two alternatives, non-avx one has matched operand.
Uros.
>
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -22072,56 +22072,53 @@
> "vpopcnt\t{%1, %0|%0, %1}")
>
> (define_insn "vgf2p8affineinvqb_"
> - [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
> + [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v")
> (unspec:VI1_AVX512F
> - [(match_operand:VI1_AVX512F 1 "register_operand" "0,x,v")
> - (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,xm,vm")
> - (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
> + [(match_operand:VI1_AVX512F 1 "register_operand" "0,v")
> + (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm")
> + (match_operand:QI 3 "const_0_to_255_operand" "n,n")]
> UNSPEC_GF2P8AFFINEINV))]
> "TARGET_GFNI"
> "@
> gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3}
> - vgf2p8affineinvqb\t{%3, %2, %1, %0|
> %0, %1, %2, %3}
> vgf2p8affineinvqb\t{%3, %2, %1, %0|
> %0, %1, %2, %3}"
> - [(set_attr "isa" "noavx,avx,avx512f")
> - (set_attr "prefix_data16" "1,*,*")
> + [(set_attr "isa" "noavx,avx")
> + (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> - (set_attr "prefix" "orig,maybe_evex,evex")
> + (set_attr "prefix" "orig,maybe_evex")
> (set_attr "mode" "")])
>
> (define_insn "vgf2p8affineqb_"
> - [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
> + [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v")
> (unspec:VI1_AVX512F
> - [(match_operand:VI1_AVX512F 1 "register_operand" "0,x,v")
> - (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,xm,vm")
> - (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
> + [(match_operand:VI1_AVX512F 1 "register_operand" "0,v")
> + (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm")
> + (match_operand:QI 3 "const_0_to_255_operand" "n,n")]
> UNSPEC_GF2P8AFFINE))]
> "TARGET_GFNI"
> "@
> gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
> - vgf2p8affineqb\t{%3, %2, %1, %0| %0,
> %1, %2, %3}
> vgf2p8affineqb\t{%3, %2, %1, %0| %0,
> %1, %2, %3}"
> - [(set_attr "isa" "noavx,avx,avx512f")
> - (set_attr "prefix_data16" "1,*,*")
> + [(set_attr "isa" "noavx,avx")
> + (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> - (set_attr "prefix" "orig,maybe_evex,evex")
> + (set_attr "prefix" "orig,maybe_evex")
> (set_attr "mode" "")])
>
> (define_insn "vgf2p8mulb_"
> - [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
> + [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v")
> (unspec:VI1_AVX512F
> - [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
> - (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")]
> + [(match_operand:VI1_AVX512F 1 "register_operand" "%0,v")
> + (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm")]
> UNSPEC_GF2P8MUL))]
> "TARGET_GFNI"
> "@
> gf2p8mulb\t{%2, %0| %0, %2}
> - vgf2p8mulb\t{%2, %1, %0| %0, %1, %2}
> vgf2p8mulb\t{%2, %1, %0| %0, %1, %2}"
> - [(set_attr "isa" "noavx,avx,avx512f")
> - (set_attr "prefix_data16" "1,*,*")
> + [(set_attr "isa" "noavx,avx")
> + (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> - (set_attr "prefix" "orig,maybe_evex,evex")
> + (set_attr "prefix" "orig,maybe_evex")
> (set_attr "mode" "")])
>
> (define_insn "vpshrd_"
