This patch enables the compressible features with ZC* extensions. Since all ZC* extension depends on the Zca extension, it's sufficient to only add the target Zca to extend the target RVC.
Co-Authored by: Mary Bennett <mary.benn...@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamna...@embecosm.com> Co-Authored by: Simon Cook <simon.c...@embecosm.com> gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Enable compressed builtins when ZC* extensions enabled. * config/riscv/riscv-shorten-memrefs.cc: Enable shorten_memrefs pass when ZC* extensions enabled. * config/riscv/riscv.cc (riscv_compressed_reg_p): Enable compressible registers when ZC* extensions enabled. (riscv_rtx_costs): Allow adjusting rtx costs when ZC* extensions enabled. (riscv_address_cost): Allow adjusting address cost when ZC* extensions enabled. (riscv_first_stack_step): Allow compression of the register saves without adding extra instructions. * config/riscv/riscv.h (FUNCTION_BOUNDARY): Adjusts function boundary to 16 bits when ZC* extensions enabled. --- gcc/config/riscv/riscv-c.cc | 2 +- gcc/config/riscv/riscv-shorten-memrefs.cc | 3 ++- gcc/config/riscv/riscv.cc | 11 +++++++---- gcc/config/riscv/riscv.h | 2 +- 4 files changed, 11 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 6ad562dcb8b..2937c160071 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -47,7 +47,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) { builtin_define ("__riscv"); - if (TARGET_RVC) + if (TARGET_RVC || TARGET_ZCA) builtin_define ("__riscv_compressed"); if (TARGET_RVE) diff --git a/gcc/config/riscv/riscv-shorten-memrefs.cc b/gcc/config/riscv/riscv-shorten-memrefs.cc index 8f10d24ec39..6f2b973278e 100644 --- a/gcc/config/riscv/riscv-shorten-memrefs.cc +++ b/gcc/config/riscv/riscv-shorten-memrefs.cc @@ -65,7 +65,8 @@ public: /* opt_pass methods: */ virtual bool gate (function *) { - return TARGET_RVC && riscv_mshorten_memrefs && optimize > 0; + return (TARGET_RVC || TARGET_ZCA) + && riscv_mshorten_memrefs && optimize > 0; } virtual unsigned int execute (function *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 21e7d3b3caa..3a07122bf6a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1176,7 +1176,8 @@ static bool riscv_compressed_reg_p (int regno) { /* x8-x15/f8-f15 are compressible registers. */ - return (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15) + return ((TARGET_RVC || TARGET_ZCA) + && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15) || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15))); } @@ -2416,7 +2417,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN /* When optimizing for size, make uncompressible 32-bit addresses more expensive so that compressible 32-bit addresses are preferred. */ - if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode + if ((TARGET_RVC || TARGET_ZCA) + && !speed && riscv_mshorten_memrefs && mode == SImode && !riscv_compressed_lw_address_p (XEXP (x, 0))) cost++; @@ -2828,7 +2830,8 @@ riscv_address_cost (rtx addr, machine_mode mode, { /* When optimizing for size, make uncompressible 32-bit addresses more * expensive so that compressible 32-bit addresses are preferred. */ - if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode + if ((TARGET_RVC || TARGET_ZCA) + && !speed && riscv_mshorten_memrefs && mode == SImode && !riscv_compressed_lw_address_p (addr)) return riscv_address_insns (addr, mode, false) + 1; return riscv_address_insns (addr, mode, false); @@ -5331,7 +5334,7 @@ riscv_first_stack_step (struct riscv_frame_info *frame, poly_int64 remaining_siz && remaining_const_size % IMM_REACH >= min_first_step) return remaining_const_size % IMM_REACH; - if (TARGET_RVC) + if (TARGET_RVC || TARGET_ZCA) { /* If we need two subtracts, and one is small enough to allow compressed loads and stores, then put that one first. */ diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 4541255a8ae..a507db61900 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -186,7 +186,7 @@ ASM_MISA_SPEC #define PARM_BOUNDARY BITS_PER_WORD /* Allocation boundary (in *bits*) for the code of a function. */ -#define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32) +#define FUNCTION_BOUNDARY ((TARGET_RVC || TARGET_ZCA) ? 16 : 32) /* The smallest supported stack boundary the calling convention supports. */ #define STACK_BOUNDARY \ -- 2.25.1