Re: [PATCH v2 2/9] RISC-V: Handle differences between xtheadvector and vector
> diff --git a/gcc/config/riscv/riscv_th_vector.h
> b/gcc/config/riscv/riscv_th_vector.h
> new file mode 100644
> index 000..194652032bc
> --- /dev/null
> +++ b/gcc/config/riscv/riscv_th_vector.h
...
> +/* NOTE: This implementation of riscv_vector.h is intentionally short. It
> does
> + not define the RVV types and intrinsic functions directly in C and C++
> + code, but instead uses the following pragma to tell GCC to insert the
> + necessary type and function definitions itself. The net effect is the
> + same, and the file is a complete implementation of riscv_vector.h. */
> +#pragma riscv intrinsic "vector"
Plz use #pragma riscv intrinsic "thead_vector"
> @@ -1135,7 +1135,7 @@ (define_expand "@mov_lra"
> [(set (match_operand:V_FRACT 0 "reg_or_mem_operand")
> (match_operand:V_FRACT 1 "reg_or_mem_operand"))
> (clobber (match_scratch:P 2))])]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
It's an accident, right?
> {})
>
> (define_expand "@mov_lra"
> @@ -1143,14 +1143,14 @@ (define_expand "@mov_lra"
> [(set (match_operand:VB 0 "reg_or_mem_operand")
> (match_operand:VB 1 "reg_or_mem_operand"))
> (clobber (match_scratch:P 2))])]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Ditto.
> {})
>
> (define_insn_and_split "*mov_lra"
>[(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr")
> (match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr"))
> (clobber (match_scratch:P 2 "=&r,&r,X"))]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Ditto.
>"#"
>"&& reload_completed"
>[(const_int 0)]
> @@ -1172,7 +1172,7 @@ (define_insn_and_split "*mov_lra"
>[(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
> (match_operand:VB 1 "reg_or_mem_operand" " m,vr,vr"))
> (clobber (match_scratch:P 2 "=&r,&r,X"))]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Ditto.
>"#"
>"&& reload_completed"
>[(const_int 0)]
> @@ -1286,14 +1286,14 @@ (define_expand "@mov_lra"
> [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
> (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand"))
> (clobber (match_scratch:P 2))])]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Ditto.
> {})
>
> (define_insn_and_split "*mov_lra"
>[(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
> (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
> (clobber (match_scratch:P 2 "=&r,&r,X"))]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)
Ditto.
> && (register_operand (operands[0], mode)
> || register_operand (operands[1], mode))"
>"#"
> @@ -1359,7 +1359,7 @@ (define_expand "movmisalign"
> (define_expand "movmisalign"
>[(set (match_operand:V 0 "nonimmediate_operand")
> (match_operand:V 1 "general_operand"))]
> - "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
> + "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
Ditto.
>{
> emit_move_insn (operands[0], operands[1]);
> DONE;
> @@ -1396,7 +1396,7 @@ (define_insn_and_split "*vec_duplicate"
>[(set (match_operand:V_VLS 0 "register_operand")
> (vec_duplicate:V_VLS
>(match_operand: 1 "direct_broadcast_operand")))]
> - "TARGET_VECTOR && can_create_pseudo_p ()"
> + "TARGET_VECTOR && can_create_pseudo_p ()"
Ditto.
>"#"
>"&& 1"
>[(const_int 0)]
[PATCH v2 2/9] RISC-V: Handle differences between xtheadvector and vector
This patch is to handle the differences in instruction generation
between vector and xtheadvector, mainly adding th. prefix
to all xtheadvector instructions.
Contributors:
Jun Sha (Joshua)
Jin Ma
Christoph Müllner
gcc/ChangeLog:
* config.gcc: Add header for XTheadVector intrinsics.
* config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
Add XTheadVector.
* config/riscv/riscv.cc (riscv_print_operand):
Add new operand format directives.
(riscv_print_operand_punct_valid_p): Likewise.
* config/riscv/vector-iterators.md: Split any_int_unop
for not and neg.
* config/riscv/vector.md (@pred_):
Add th. for xtheadvector instructions.
* config/riscv/riscv_th_vector.h: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
---
gcc/config.gcc| 2 +-
gcc/config/riscv/riscv-c.cc | 4 +-
gcc/config/riscv/riscv.cc | 11 +-
gcc/config/riscv/riscv_th_vector.h| 49 ++
gcc/config/riscv/vector-iterators.md | 4 +
gcc/config/riscv/vector.md| 777 +-
.../gcc.target/riscv/rvv/base/pragma-1.c | 2 +-
7 files changed, 466 insertions(+), 383 deletions(-)
create mode 100644 gcc/config/riscv/riscv_th_vector.h
diff --git a/gcc/config.gcc b/gcc/config.gcc
index ba6d63e33ac..e0fc2b1a27c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -548,7 +548,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o"
d_target_objs="riscv-d.o"
- extra_headers="riscv_vector.h"
+ extra_headers="riscv_vector.h riscv_th_vector.h"
target_gtfiles="$target_gtfiles
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 184fff905b2..0a17d5f6656 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -194,8 +194,8 @@ riscv_pragma_intrinsic (cpp_reader *)
{
if (!TARGET_VECTOR)
{
- error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension "
-"enabled",
+ error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or "
+"'XTHEADVECTOR' extension enabled",
name);
return;
}
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ecee7eb4727..754107cdaac 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5323,7 +5323,7 @@ riscv_get_v_regno_alignment (machine_mode mode)
static void
riscv_print_operand (FILE *file, rtx op, int letter)
{
- /* `~` does not take an operand so op will be null
+ /* `~` and '^' does not take an operand so op will be null
Check for before accessing op.
*/
if (letter == '~')
@@ -5332,6 +5332,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
fputc('w', file);
return;
}
+
+ if (letter == '^')
+{
+ if (TARGET_XTHEADVECTOR)
+ fputs ("th.", file);
+ return;
+}
machine_mode mode = GET_MODE (op);
enum rtx_code code = GET_CODE (op);
@@ -5584,7 +5591,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
static bool
riscv_print_operand_punct_valid_p (unsigned char code)
{
- return (code == '~');
+ return (code == '~' || code == '^');
}
/* Implement TARGET_PRINT_OPERAND_ADDRESS. */
diff --git a/gcc/config/riscv/riscv_th_vector.h
b/gcc/config/riscv/riscv_th_vector.h
new file mode 100644
index 000..194652032bc
--- /dev/null
+++ b/gcc/config/riscv/riscv_th_vector.h
@@ -0,0 +1,49 @@
+/* RISC-V 'XTheadVector' Extension intrinsics include file.
+ Copyright (C) 2022-2023 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+
