Re: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
> > &, ^, | has supported on clang, so I think we should support that as well > > Looks gcc lack of such operation right now, so mark the TYPE_INDIVISIBLE_P > (type) = 0 as aarch64 did. > I have a try but I am afraid we need separated patch to take care of it for > risk control consideration. Yeah, agree, that's defer this part to GCC 15 :)
RE: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
> The result of comparison should be vbool* rather than v[u]int*. > The result of comparison should be vbool* rather than vfloat*, > otherwise all 1 is not really meanful for floating point value. > But I know clang generates the same strange/wrong code here... I see, will update the test cases and double check about it in v4. > &, ^, | has supported on clang, so I think we should support that as well Looks gcc lack of such operation right now, so mark the TYPE_INDIVISIBLE_P (type) = 0 as aarch64 did. I have a try but I am afraid we need separated patch to take care of it for risk control consideration. Pan -Original Message- From: Kito Cheng Sent: Thursday, March 21, 2024 9:25 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang ; rdapp@gmail.com; vine...@rivosinc.com; pal...@rivosinc.com Subject: Re: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV > For the vint*m*_t below operations are allowed. > * The sizeof. > * The global variable(s). > * The element of union and struct. > * The cast to other equalities. > * CMP: >, <, ==, !=, <=, >= The result of comparison should be vbool* rather than v[u]int*. > * ALU: +, -, *, /, %, &, |, ^, >>, <<, ~, - > > For the vfloat*m*_t below operations are allowed. > * The sizeof. > * The global variable(s). > * The element of union and struct. > * The cast to other equalities. > * CMP: >, <, ==, !=, <=, >= The result of comparison should be vbool* rather than vfloat*, otherwise all 1 is not really meanful for floating point value. But I know clang generates the same strange/wrong code here... > * ALU: +, -, *, /, - > > For the vbool*_t types only below operations are allowed except > the CMP and ALU. The CMP and ALU operations on vbool*_t is not > well defined currently. > * The sizeof. > * The global variable(s). > * The element of union and struct. > * The cast to other equalities. &, ^, | has supported on clang, so I think we should support that as well
Re: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
Hi Stefan: I admit that's kinda bad practice here, the spec should appear before implementation or at least come together, however we have long discussion on the RISC-V gcc community on this, and we give a waiver for this feature due to the clang compatibility, and this features also used on some project, so we would like to moving this forward even it's incomplete. For the spec part, we are working in progress and will put the draft soon. On Fri, Mar 15, 2024 at 9:46 AM Li, Pan2 wrote: > > > Shouldn't a major user-facing change like this be discussed in a PR against > > https://github.com/riscv-non-isa/riscv-c-api-doc/ or > > https://github.com/riscv-non-isa/rvv-intrinsic-doc before or concurrent with > > compiler implementation? > > I think Kito is working on the spec doc already. > > Hi Kito > Could you please help to correct me the behavior of the riscv_rvv_vector_bits > attribute? > Sort of details and I suspect there is something missing, or different > behavior compared with clang side. > > Pan > > -Original Message- > From: Stefan O'Rear > Sent: Tuesday, March 12, 2024 9:25 PM > To: Li, Pan2 ; gcc-patches@gcc.gnu.org > Cc: juzhe.zh...@rivai.ai; Kito Cheng ; Wang, Yanzhang > ; rdapp....@gmail.com; Vineet Gupta > ; Palmer Dabbelt > Subject: Re: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits > for RVV > > On Tue, Mar 12, 2024, at 2:15 AM, pan2...@intel.com wrote: > > From: Pan Li > > > > Update in v3: > > * Add pre-defined __riscv_v_fixed_vlen when zvl. > > > > Update in v2: > > * Cleanup some unused code. > > * Fix some typo of commit log. > > > > Original log: > > > > This patch would like to introduce one new gcc attribute for RVV. > > This attribute is used to define fixed-length variants of one > > existing sizeless RVV types. > > > > This attribute is valid if and only if the mrvv-vector-bits=zvl, the only > > one args should be the integer constant and its' value is terminated > > by the LMUL and the vector register bits in zvl*b. For example: > > > > typedef vint32m2_t fixed_vint32m2_t > > __attribute__((riscv_rvv_vector_bits(128))); > > > > The above type define is valid when -march=rv64gc_zve64d_zvl64b > > (aka 2(m2) * 64 = 128 for vin32m2_t), and will report error when > > -march=rv64gcv_zvl128b similar to below. > > > > "error: invalid RVV vector size '128', expected size is '256' based on > > LMUL of type and '-mrvv-vector-bits=zvl'" > > > > Meanwhile, a pre-define macro __riscv_v_fixed_vlen is introduced to > > represent the fixed vlen in a RVV vector register. > > Shouldn't a major user-facing change like this be discussed in a PR against > https://github.com/riscv-non-isa/riscv-c-api-doc/ or > https://github.com/riscv-non-isa/rvv-intrinsic-doc before or concurrent with > compiler implementation? > > -s > > > For the vint*m*_t below operations are allowed. > > * The sizeof. > > * The global variable(s). > > * The element of union and struct. > > * The cast to other equalities. > > * CMP: >, <, ==, !=, <=, >= > > * ALU: +, -, *, /, %, &, |, ^, >>, <<, ~, - > > > > For the vfloat*m*_t below operations are allowed. > > * The sizeof. > > * The global variable(s). > > * The element of union and struct. > > * The cast to other equalities. > > * CMP: >, <, ==, !=, <=, >= > > * ALU: +, -, *, /, - > > > > For the vbool*_t types only below operations are allowed except > > the CMP and ALU. The CMP and ALU operations on vbool*_t is not > > well defined currently. > > * The sizeof. > > * The global variable(s). > > * The element of union and struct. > > * The cast to other equalities. > > > > For the vint*x*m*_t tuple types are not suppored in this patch > > which is compatible with clang. > > > > This patch passed the below testsuites. > > * The riscv fully regression tests. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define > > macro __riscv_v_fixed_vlen when zvl. > > * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute): > > New static func to take care of the RVV types decorated by > > the attributes. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-1.c: New test. > > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-10.c: New test. > > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-11.c: New
Re: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
> For the vint*m*_t below operations are allowed. > * The sizeof. > * The global variable(s). > * The element of union and struct. > * The cast to other equalities. > * CMP: >, <, ==, !=, <=, >= The result of comparison should be vbool* rather than v[u]int*. > * ALU: +, -, *, /, %, &, |, ^, >>, <<, ~, - > > For the vfloat*m*_t below operations are allowed. > * The sizeof. > * The global variable(s). > * The element of union and struct. > * The cast to other equalities. > * CMP: >, <, ==, !=, <=, >= The result of comparison should be vbool* rather than vfloat*, otherwise all 1 is not really meanful for floating point value. But I know clang generates the same strange/wrong code here... > * ALU: +, -, *, /, - > > For the vbool*_t types only below operations are allowed except > the CMP and ALU. The CMP and ALU operations on vbool*_t is not > well defined currently. > * The sizeof. > * The global variable(s). > * The element of union and struct. > * The cast to other equalities. &, ^, | has supported on clang, so I think we should support that as well
RE: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
> Shouldn't a major user-facing change like this be discussed in a PR against > https://github.com/riscv-non-isa/riscv-c-api-doc/ or > https://github.com/riscv-non-isa/rvv-intrinsic-doc before or concurrent with > compiler implementation? I think Kito is working on the spec doc already. Hi Kito Could you please help to correct me the behavior of the riscv_rvv_vector_bits attribute? Sort of details and I suspect there is something missing, or different behavior compared with clang side. Pan -Original Message- From: Stefan O'Rear Sent: Tuesday, March 12, 2024 9:25 PM To: Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; Kito Cheng ; Wang, Yanzhang ; rdapp@gmail.com; Vineet Gupta ; Palmer Dabbelt Subject: Re: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV On Tue, Mar 12, 2024, at 2:15 AM, pan2...@intel.com wrote: > From: Pan Li > > Update in v3: > * Add pre-defined __riscv_v_fixed_vlen when zvl. > > Update in v2: > * Cleanup some unused code. > * Fix some typo of commit log. > > Original log: > > This patch would like to introduce one new gcc attribute for RVV. > This attribute is used to define fixed-length variants of one > existing sizeless RVV types. > > This attribute is valid if and only if the mrvv-vector-bits=zvl, the only > one args should be the integer constant and its' value is terminated > by the LMUL and the vector register bits in zvl*b. For example: > > typedef vint32m2_t fixed_vint32m2_t > __attribute__((riscv_rvv_vector_bits(128))); > > The above type define is valid when -march=rv64gc_zve64d_zvl64b > (aka 2(m2) * 64 = 128 for vin32m2_t), and will report error when > -march=rv64gcv_zvl128b similar to below. > > "error: invalid RVV vector size '128', expected size is '256' based on > LMUL of type and '-mrvv-vector-bits=zvl'" > > Meanwhile, a pre-define macro __riscv_v_fixed_vlen is introduced to > represent the fixed vlen in a RVV vector register. Shouldn't a major user-facing change like this be discussed in a PR against https://github.com/riscv-non-isa/riscv-c-api-doc/ or https://github.com/riscv-non-isa/rvv-intrinsic-doc before or concurrent with compiler implementation? -s > For the vint*m*_t below operations are allowed. > * The sizeof. > * The global variable(s). > * The element of union and struct. > * The cast to other equalities. > * CMP: >, <, ==, !=, <=, >= > * ALU: +, -, *, /, %, &, |, ^, >>, <<, ~, - > > For the vfloat*m*_t below operations are allowed. > * The sizeof. > * The global variable(s). > * The element of union and struct. > * The cast to other equalities. > * CMP: >, <, ==, !=, <=, >= > * ALU: +, -, *, /, - > > For the vbool*_t types only below operations are allowed except > the CMP and ALU. The CMP and ALU operations on vbool*_t is not > well defined currently. > * The sizeof. > * The global variable(s). > * The element of union and struct. > * The cast to other equalities. > > For the vint*x*m*_t tuple types are not suppored in this patch > which is compatible with clang. > > This patch passed the below testsuites. > * The riscv fully regression tests. > > gcc/ChangeLog: > > * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define > macro __riscv_v_fixed_vlen when zvl. > * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute): > New static func to take care of the RVV types decorated by > the attributes. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-1.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-10.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-11.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-12.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-13.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-14.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-15.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-16.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-17.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-2.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-3.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-4.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-5.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-6.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-7.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-8.c: New test. > * gcc.target/riscv/rvv/b
Re: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
On Tue, Mar 12, 2024, at 2:15 AM, pan2...@intel.com wrote: > From: Pan Li > > Update in v3: > * Add pre-defined __riscv_v_fixed_vlen when zvl. > > Update in v2: > * Cleanup some unused code. > * Fix some typo of commit log. > > Original log: > > This patch would like to introduce one new gcc attribute for RVV. > This attribute is used to define fixed-length variants of one > existing sizeless RVV types. > > This attribute is valid if and only if the mrvv-vector-bits=zvl, the only > one args should be the integer constant and its' value is terminated > by the LMUL and the vector register bits in zvl*b. For example: > > typedef vint32m2_t fixed_vint32m2_t > __attribute__((riscv_rvv_vector_bits(128))); > > The above type define is valid when -march=rv64gc_zve64d_zvl64b > (aka 2(m2) * 64 = 128 for vin32m2_t), and will report error when > -march=rv64gcv_zvl128b similar to below. > > "error: invalid RVV vector size '128', expected size is '256' based on > LMUL of type and '-mrvv-vector-bits=zvl'" > > Meanwhile, a pre-define macro __riscv_v_fixed_vlen is introduced to > represent the fixed vlen in a RVV vector register. Shouldn't a major user-facing change like this be discussed in a PR against https://github.com/riscv-non-isa/riscv-c-api-doc/ or https://github.com/riscv-non-isa/rvv-intrinsic-doc before or concurrent with compiler implementation? -s > For the vint*m*_t below operations are allowed. > * The sizeof. > * The global variable(s). > * The element of union and struct. > * The cast to other equalities. > * CMP: >, <, ==, !=, <=, >= > * ALU: +, -, *, /, %, &, |, ^, >>, <<, ~, - > > For the vfloat*m*_t below operations are allowed. > * The sizeof. > * The global variable(s). > * The element of union and struct. > * The cast to other equalities. > * CMP: >, <, ==, !=, <=, >= > * ALU: +, -, *, /, - > > For the vbool*_t types only below operations are allowed except > the CMP and ALU. The CMP and ALU operations on vbool*_t is not > well defined currently. > * The sizeof. > * The global variable(s). > * The element of union and struct. > * The cast to other equalities. > > For the vint*x*m*_t tuple types are not suppored in this patch > which is compatible with clang. > > This patch passed the below testsuites. > * The riscv fully regression tests. > > gcc/ChangeLog: > > * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define > macro __riscv_v_fixed_vlen when zvl. > * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute): > New static func to take care of the RVV types decorated by > the attributes. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-1.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-10.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-11.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-12.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-13.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-14.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-15.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-16.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-17.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-2.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-3.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-4.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-5.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-6.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-7.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-8.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-9.c: New test. > * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits.h: New test. > > Signed-off-by: Pan Li > --- > gcc/config/riscv/riscv-c.cc | 3 + > gcc/config/riscv/riscv.cc | 87 +- > .../riscv/rvv/base/riscv_rvv_vector_bits-1.c | 6 + > .../riscv/rvv/base/riscv_rvv_vector_bits-10.c | 53 + > .../riscv/rvv/base/riscv_rvv_vector_bits-11.c | 76 > .../riscv/rvv/base/riscv_rvv_vector_bits-12.c | 14 +++ > .../riscv/rvv/base/riscv_rvv_vector_bits-13.c | 10 ++ > .../riscv/rvv/base/riscv_rvv_vector_bits-14.c | 10 ++ > .../riscv/rvv/base/riscv_rvv_vector_bits-15.c | 10 ++ > .../riscv/rvv/base/riscv_rvv_vector_bits-16.c | 11 ++ > .../riscv/rvv/base/riscv_rvv_vector_bits-17.c | 10 ++ > .../riscv/rvv/base/riscv_rvv_vector_bits-2.c | 6 + > .../riscv/rvv/base/riscv_rvv_vector_bits-3.c | 6 + > .../riscv/rvv/base/riscv_rvv_vector_bits-4.c | 6 + > .../riscv/rvv/base/riscv_rvv_vector_bits-5.c | 6 + > .../riscv/rvv/base/riscv_rvv_vector_bits-6.c | 6 + > .../riscv/rvv/base/riscv_rvv_vector_bits-7.c | 76
[PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
From: Pan Li Update in v3: * Add pre-defined __riscv_v_fixed_vlen when zvl. Update in v2: * Cleanup some unused code. * Fix some typo of commit log. Original log: This patch would like to introduce one new gcc attribute for RVV. This attribute is used to define fixed-length variants of one existing sizeless RVV types. This attribute is valid if and only if the mrvv-vector-bits=zvl, the only one args should be the integer constant and its' value is terminated by the LMUL and the vector register bits in zvl*b. For example: typedef vint32m2_t fixed_vint32m2_t __attribute__((riscv_rvv_vector_bits(128))); The above type define is valid when -march=rv64gc_zve64d_zvl64b (aka 2(m2) * 64 = 128 for vin32m2_t), and will report error when -march=rv64gcv_zvl128b similar to below. "error: invalid RVV vector size '128', expected size is '256' based on LMUL of type and '-mrvv-vector-bits=zvl'" Meanwhile, a pre-define macro __riscv_v_fixed_vlen is introduced to represent the fixed vlen in a RVV vector register. For the vint*m*_t below operations are allowed. * The sizeof. * The global variable(s). * The element of union and struct. * The cast to other equalities. * CMP: >, <, ==, !=, <=, >= * ALU: +, -, *, /, %, &, |, ^, >>, <<, ~, - For the vfloat*m*_t below operations are allowed. * The sizeof. * The global variable(s). * The element of union and struct. * The cast to other equalities. * CMP: >, <, ==, !=, <=, >= * ALU: +, -, *, /, - For the vbool*_t types only below operations are allowed except the CMP and ALU. The CMP and ALU operations on vbool*_t is not well defined currently. * The sizeof. * The global variable(s). * The element of union and struct. * The cast to other equalities. For the vint*x*m*_t tuple types are not suppored in this patch which is compatible with clang. This patch passed the below testsuites. * The riscv fully regression tests. gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define macro __riscv_v_fixed_vlen when zvl. * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute): New static func to take care of the RVV types decorated by the attributes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-1.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-10.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-11.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-12.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-13.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-14.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-15.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-16.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-17.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-2.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-3.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-4.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-5.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-6.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-7.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-8.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-9.c: New test. * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits.h: New test. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-c.cc | 3 + gcc/config/riscv/riscv.cc | 87 +- .../riscv/rvv/base/riscv_rvv_vector_bits-1.c | 6 + .../riscv/rvv/base/riscv_rvv_vector_bits-10.c | 53 + .../riscv/rvv/base/riscv_rvv_vector_bits-11.c | 76 .../riscv/rvv/base/riscv_rvv_vector_bits-12.c | 14 +++ .../riscv/rvv/base/riscv_rvv_vector_bits-13.c | 10 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-14.c | 10 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-15.c | 10 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-16.c | 11 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-17.c | 10 ++ .../riscv/rvv/base/riscv_rvv_vector_bits-2.c | 6 + .../riscv/rvv/base/riscv_rvv_vector_bits-3.c | 6 + .../riscv/rvv/base/riscv_rvv_vector_bits-4.c | 6 + .../riscv/rvv/base/riscv_rvv_vector_bits-5.c | 6 + .../riscv/rvv/base/riscv_rvv_vector_bits-6.c | 6 + .../riscv/rvv/base/riscv_rvv_vector_bits-7.c | 76 .../riscv/rvv/base/riscv_rvv_vector_bits-8.c | 75 .../riscv/rvv/base/riscv_rvv_vector_bits-9.c | 76 .../riscv/rvv/base/riscv_rvv_vector_bits.h| 108 ++ 20 files changed, 653 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-10.c create mode
