Re: [PATCH v4] RISC-V: Libitm add RISC-V support.

2022-10-29 Thread Xiongchuan Tan via Gcc-patches 
On Saturday, 29 October 2022 12:33:50 CST Jeff Law wrote:
> > +#ifdef __riscv_e
> > +#  error "rv32e unsupported"
> > +#endif
> 
> error "rv32e and rv64e unsupported" would probably be a better error 
> here.  But it's probably not a big deal.

Fixed in v5.

> Do you have commit access?  If so, go ahead and commit the change.  Else 
> let me know and I can do it for you.

I don't have commit access, so thank you for doing it for me!

Re: [PATCH v4] RISC-V: Libitm add RISC-V support.

2022-10-28 Thread Jeff Law via Gcc-patches 



On 10/28/22 06:34, Xiongchuan Tan via Gcc-patches wrote:

Reviewed-by: Palmer Dabbelt 
Acked-by: Palmer Dabbelt 

libitm/ChangeLog:

 * configure.tgt: Add riscv support.
 * config/riscv/asm.h: New file.
 * config/riscv/sjlj.S: New file.
 * config/riscv/target.h: New file.
---
v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc)

v3: Ensure the stack is aligned to 16 bytes; make use of Zihintpause in
cpu_relax()

v4: Add a guard for unsupported RV32E

  libitm/config/riscv/asm.h|  58 ++
  libitm/config/riscv/sjlj.S   | 144 +++
  libitm/config/riscv/target.h |  62 +++
  libitm/configure.tgt |   2 +
  4 files changed, 266 insertions(+)
  create mode 100644 libitm/config/riscv/asm.h
  create mode 100644 libitm/config/riscv/sjlj.S
  create mode 100644 libitm/config/riscv/target.h

diff --git a/libitm/config/riscv/asm.h b/libitm/config/riscv/asm.h
new file mode 100644
index 000..8d02117
--- /dev/null
+++ b/libitm/config/riscv/asm.h
@@ -0,0 +1,58 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+   Contributed by Xiongchuan Tan .
+
+   This file is part of the GNU Transactional Memory Library (libitm).
+
+   Libitm is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#ifndef _RV_ASM_H
+#define _RV_ASM_H
+
+#ifdef __riscv_e
+#  error "rv32e unsupported"
+#endif


error "rv32e and rv64e unsupported" would probably be a better error 
here.  But it's probably not a big deal.




+#else
+#  define SZ_FPR 0
+#endif


Sneaky way to not allocate space for the FP regs.  ;)

Do you have commit access?  If so, go ahead and commit the change.  Else 
let me know and I can do it for you.



Thanks,



Jeff

[PATCH v4] RISC-V: Libitm add RISC-V support.

2022-10-28 Thread Xiongchuan Tan via Gcc-patches 
Reviewed-by: Palmer Dabbelt 
Acked-by: Palmer Dabbelt 

libitm/ChangeLog:

* configure.tgt: Add riscv support.
* config/riscv/asm.h: New file.
* config/riscv/sjlj.S: New file.
* config/riscv/target.h: New file.
---
v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc)

v3: Ensure the stack is aligned to 16 bytes; make use of Zihintpause in
cpu_relax()

v4: Add a guard for unsupported RV32E

 libitm/config/riscv/asm.h|  58 ++
 libitm/config/riscv/sjlj.S   | 144 +++
 libitm/config/riscv/target.h |  62 +++
 libitm/configure.tgt |   2 +
 4 files changed, 266 insertions(+)
 create mode 100644 libitm/config/riscv/asm.h
 create mode 100644 libitm/config/riscv/sjlj.S
 create mode 100644 libitm/config/riscv/target.h

diff --git a/libitm/config/riscv/asm.h b/libitm/config/riscv/asm.h
new file mode 100644
index 000..8d02117
--- /dev/null
+++ b/libitm/config/riscv/asm.h
@@ -0,0 +1,58 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+   Contributed by Xiongchuan Tan .
+
+   This file is part of the GNU Transactional Memory Library (libitm).
+
+   Libitm is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#ifndef _RV_ASM_H
+#define _RV_ASM_H
+
+#ifdef __riscv_e
+#  error "rv32e unsupported"
+#endif
+
+#if __riscv_xlen == 64
+#  define GPR_L ld
+#  define GPR_S sd
+#  define SZ_GPR 8
+#  define LEN_GPR 14
+#elif __riscv_xlen == 32
+#  define GPR_L lw
+#  define GPR_S sw
+#  define SZ_GPR 4
+#  define LEN_GPR 16 /* Extra padding to align the stack to 16 bytes */
+#else
+#  error Unsupported XLEN (must be 64-bit or 32-bit).
+#endif
+
+#if defined(__riscv_flen) && __riscv_flen == 64
+#  define FPR_L fld
+#  define FPR_S fsd
+#  define SZ_FPR 8
+#elif defined(__riscv_flen) && __riscv_flen == 32
+#  define FPR_L flw
+#  define FPR_S fsw
+#  define SZ_FPR 4
+#else
+#  define SZ_FPR 0
+#endif
+
+#endif  /* _RV_ASM_H */
diff --git a/libitm/config/riscv/sjlj.S b/libitm/config/riscv/sjlj.S
new file mode 100644
index 000..93f12ec
--- /dev/null
+++ b/libitm/config/riscv/sjlj.S
@@ -0,0 +1,144 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+   Contributed by Xiongchuan Tan .
+
+   This file is part of the GNU Transactional Memory Library (libitm).
+
+   Libitm is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#include "asmcfi.h"
+#include "asm.h"
+
+   .text
+   .align  2
+   .global _ITM_beginTransaction
+   .type   _ITM_beginTransaction, @function
+
+_ITM_beginTransaction:
+   cfi_startproc
+   mv a1, sp
+   addi sp, sp, -(LEN_GPR*SZ_GPR+12*SZ_FPR)
+   cfi_adjust_cfa_offset(LEN_GPR*SZ_GPR+12*SZ_FPR)
+
+   /* Return Address */
+   GPR_S ra, 0*SZ_GPR(sp)
+   cfi_rel_offset(ra, 0*SZ_GPR)
+
+   /* Caller's sp */
+   GPR_S a1, 1*SZ_GPR(sp)
+
+   /* Caller's s0/fp */
+   GPR_S fp, 2*SZ_GPR(sp)
+   cfi_rel_offset(fp, 2*SZ_GPR)
+
+   /* Callee-saved registers */
+   GPR_S s1, 3*SZ_GPR(sp)
+   GPR_S s2, 4*SZ_GPR(sp)
+   GPR_S s3, 5*SZ_GPR(sp)
+   GPR_S s4, 6*SZ_GPR(sp)
+   GPR_S s5,