Re: [PATCH v5] RISC-V: Support XTheadVector extension

2024-01-19 Thread Jeff Law




On 1/18/24 07:43, Christoph Müllner wrote:

On Fri, Jan 12, 2024 at 4:18 AM Jun Sha (Joshua)
 wrote:


This patch series presents gcc implementation of the XTheadVector
extension [1].

[1] https://github.com/T-head-Semi/thead-extension-spec/

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 10 changes in vector.md.

For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.

We have run the GCC test suite and can confirm that there
are no regressions.

Furthermore, we have run the tests in
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples,
and all the tests passed.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 

[PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0
[PATCH v5] RISC-V: Adds the prefix "th." for the instructions of XTheadVector
[PATCH v6] RISC-V: Handle differences between XTheadvector and Vector
[PATCH v6] RISC-V: Add support for xtheadvector-specific intrinsics
[PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions
[PATCH v5] RISC-V: Rewrite some instructions using ASM targethook


All patches of this series got either "LGTM" or "OK":
* https://gcc.gnu.org/pipermail/gcc-patches/2024-January/643339.html
* https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642798.html
* https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642799.html
* https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642800.html
* https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642801.html
* https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642802.html

As mentioned earlier, I have rebased the patches, retested them locally and
(after ensuring there are no regressions) pushed them.

To all involved people: thank you very much!
A special 'thank you' goes to Juzhe, who did a great job in reviewing
the patches
and providing suggestions to get the code into shape!
Likewise.  Glad to see we were able to push this through to a reasonable 
conclusion and a huge thanks to Juzhe for all his work on the review side.


Jeff


Re: [PATCH v5] RISC-V: Support XTheadVector extension

2024-01-18 Thread Christoph Müllner
On Fri, Jan 12, 2024 at 4:18 AM Jun Sha (Joshua)
 wrote:
>
> This patch series presents gcc implementation of the XTheadVector
> extension [1].
>
> [1] https://github.com/T-head-Semi/thead-extension-spec/
>
> For some vector patterns that cannot be avoided, we use
> "!TARGET_XTHEADVECTOR" to disable them in order not to
> generate instructions that xtheadvector does not support,
> causing 10 changes in vector.md.
>
> For the th. prefix issue, we use current_output_insn and
> the ASM_OUTPUT_OPCODE hook instead of directly modifying
> patterns in vector.md.
>
> We have run the GCC test suite and can confirm that there
> are no regressions.
>
> Furthermore, we have run the tests in
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples,
> and all the tests passed.
>
> Co-authored-by: Jin Ma 
> Co-authored-by: Xianmiao Qu 
> Co-authored-by: Christoph Müllner 
>
> [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0
> [PATCH v5] RISC-V: Adds the prefix "th." for the instructions of XTheadVector
> [PATCH v6] RISC-V: Handle differences between XTheadvector and Vector
> [PATCH v6] RISC-V: Add support for xtheadvector-specific intrinsics
> [PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector 
> instructions
> [PATCH v5] RISC-V: Rewrite some instructions using ASM targethook

All patches of this series got either "LGTM" or "OK":
* https://gcc.gnu.org/pipermail/gcc-patches/2024-January/643339.html
* https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642798.html
* https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642799.html
* https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642800.html
* https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642801.html
* https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642802.html

As mentioned earlier, I have rebased the patches, retested them locally and
(after ensuring there are no regressions) pushed them.

To all involved people: thank you very much!
A special 'thank you' goes to Juzhe, who did a great job in reviewing
the patches
and providing suggestions to get the code into shape!


[PATCH v5] RISC-V: Support XTheadVector extension

2024-01-11 Thread Jun Sha (Joshua)
This patch series presents gcc implementation of the XTheadVector
extension [1].

[1] https://github.com/T-head-Semi/thead-extension-spec/

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 10 changes in vector.md.

For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.

We have run the GCC test suite and can confirm that there
are no regressions.

Furthermore, we have run the tests in 
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples, 
and all the tests passed.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 

[PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0
[PATCH v5] RISC-V: Adds the prefix "th." for the instructions of XTheadVector
[PATCH v6] RISC-V: Handle differences between XTheadvector and Vector
[PATCH v6] RISC-V: Add support for xtheadvector-specific intrinsics
[PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions
[PATCH v5] RISC-V: Rewrite some instructions using ASM targethook