This is more code clean-up for insn attributes.
It removes "mcu_have_movw", "mcu_mega" and defines "enabled" and "isa"
attributes instead.
The "isa" attribute which triggers "enabled" is a replacement for AVR_HAVE_MOVW
assembler dialect. We don't actually support assembler dialects but different
ISAs so that an attribute that reflects ISA capabilities seems more appropriate
and straight forward here. Moreover, it's easier to write down different
instruction lengths (which wouldn't occur if it was just an assembler dialect).
The only notable change is to epilogue_restores:
(set (reg:HI REG_Y)
(plus:HI (reg:HI REG_Y)
(match_operand:HI 0 "immediate_operand" "i,i")))
- (set (reg:HI REG_SP)
-(reg:HI REG_Y))
+ (set (reg:HI REG_SP)
+(plus:HI (reg:HI REG_Y)
+ (match_dup 0)))
The original code does not quite represent what the insn does:
A PARALLEL's actions all happen simultaneously, not in sequence.
Thus, an instruction sequence like
Y = Y + const
SP = Y
has wo be written in RTL as
Y = Y + const
SP = Y + const
and *not* as
Y = Y + const
SP = Y
The patch passes without regressions.
The patch passes with 2 more regressions if the test suite is run with
-mcall-prologues, but the two additional run-fails
./gcc.dg/sibcall-3.c
./gcc.dg/sibcall-4.c
are because tail call optimization is turned off at -mcall-prologues,
see avr.c:avr_function_ok_for_sibcall().
Ok for trunk?
Johann
* config/avr/avr.h (ASSEMBLER_DIALECT): Remove.
* config/avr/avr.md (mcu_have_movw, mcu_mega): Remove attributes.
(adjust_len): Add alternative "call".
(isa, enabled): New insn attributes.
(length): Use match_test with AVR_HAVE_JMP_CALL instead of
mcu_mega attribute.
(*sbrx_branch): Ditto.
(*sbrx_and_branch): Ditto.
(*sbix_branch): Ditto.
(*sbix_branch_bit7): Ditto.
(*sbix_branch_tmp): Ditto.
(*sbix_branch_tmp_bit7): Ditto.
(jump): Ditto.
(negsi2): Use attribute "isa" instead of assembler dialect.
(extendhisi2): Ditto.
(call_insn, call_value_insn): Set adjust_len attribute.
(indirect_jump): Indent to coding rules.
(call_prologue_saves): Use isa attribute instead of mcu_mega.
(epilogue_restores): Ditto. Fix setting of SP as described in the
RTX pattern.
(*indirect_jump): Fusion of *jcindirect_jump, *njcindirect_jump
and *indirect_jump_avr6.
(*tablejump): Fusion of *tablejump_rjmp and *tablejump_lib.
(*jcindirect_jump, *njcindirect_jump, *indirect_jump_avr6): Remove.
(*tablejump_rjmp, *tablejump_lib): Remove.
* config/avr/avr.c (adjust_insn_length): Handle ADJUST_LEN_CALL.
Index: config/avr/avr.md
===
--- config/avr/avr.md (revision 180076)
+++ config/avr/avr.md (working copy)
@@ -84,17 +84,6 @@ (define_attr "cc" "none,set_czn,set_zn,s
(define_attr "type" "branch,branch1,arith,xcall"
(const_string "arith"))
-(define_attr "mcu_have_movw" "yes,no"
- (const (if_then_else (symbol_ref "AVR_HAVE_MOVW")
- (const_string "yes")
- (const_string "no"
-
-(define_attr "mcu_mega" "yes,no"
- (const (if_then_else (symbol_ref "AVR_HAVE_JMP_CALL")
- (const_string "yes")
- (const_string "no"
-
-
;; The size of instructions in bytes.
;; XXX may depend from "cc"
@@ -124,7 +113,7 @@ (define_attr "length" ""
(const_int 3)
(const_int 4)))
(eq_attr "type" "xcall")
- (if_then_else (eq_attr "mcu_mega" "no")
+ (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
(const_int 1)
(const_int 2))]
(const_int 2)))
@@ -133,11 +122,10 @@ (define_attr "length" ""
;; Following insn attribute tells if and how the adjustment has to be
;; done:
;; no No adjustment needed; attribute "length" is fine.
-;; yesAnalyse pattern in adjust_insn_length by hand.
;; Otherwise do special processing depending on the attribute.
(define_attr "adjust_len"
- "out_bitop, out_plus, addto_sp, tsthi, tstsi, compare,
+ "out_bitop, out_plus, addto_sp, tsthi, tstsi, compare, call,
mov8, mov16, mov32, reload_in16, reload_in32,
ashlqi, ashrqi, lshrqi,
ashlhi, ashrhi, lshrhi,
@@ -145,6 +133,50 @@ (define_attr "adjust_len"
no"
(const_string "no"))
+;; Flavours of instruction set architecture (ISA), used in enabled attribute
+
+;; mov: ISA has no MOVW
+;; movw: ISA has MOVW
+;; rjmp: ISA has no CALL/JMP
+;; jmp: ISA has CALL/JMP
+;; ijmp: ISA has no EICALL/EIJMP
+;; eijmp: ISA has EICALL/EIJMP
+
+(define_attr "isa"
+ "mov,movw, rjmp,jmp, ijmp,eijmp,
+ standard"
+ (const_string "standard"))
+
+(define_attr "enabled" ""
+ (cond [(eq_attr "isa" "standard")
+ (const_int 1)
+
+ (and (eq_attr "isa"
