Re: [Patch ARM/AArch64 01/11] Fix typo in vreinterpret.c test comment.

2016-05-16 Thread Kyrill Tkachov 


On 11/05/16 14:23, Christophe Lyon wrote:

2016-05-02  Christophe Lyon  

* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Fix typo in 
comment.


Ok (I agree it's obvious)

Thanks,
Kyrill


Change-Id: I7244c0dc0a5ab2dbcec65b40c050f72f92707139

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
index 9e45e25..d4e5768 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
@@ -405,7 +405,7 @@ VECT_VAR_DECL(expected_q_f32_9,hfloat,32,4) [] = { 
0xf3f2f1f0, 0xf7f6f5f4,
  VECT_VAR_DECL(expected_q_f32_10,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
0xfff5fff4, 0xfff7fff6 };
  
-/* Expected results for vreinterpretq_xx_f32.  */

+/* Expected results for vreinterpret_xx_f32.  */
  VECT_VAR_DECL(expected_xx_f32_1,int,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
0x0, 0x0, 0x70, 0xc1 };
  VECT_VAR_DECL(expected_xx_f32_2,int,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };

Re: [Patch ARM/AArch64 01/11] Fix typo in vreinterpret.c test comment.

2016-05-13 Thread James Greenhalgh 
On Wed, May 11, 2016 at 03:23:51PM +0200, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  
> 
>   * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Fix typo in 
> comment.

This one would have been OK to commit as obvious.

OK for trunk.

Thanks,
James

[Patch ARM/AArch64 01/11] Fix typo in vreinterpret.c test comment.

2016-05-11 Thread Christophe Lyon 
2016-05-02  Christophe Lyon  

* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Fix typo in 
comment.

Change-Id: I7244c0dc0a5ab2dbcec65b40c050f72f92707139

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
index 9e45e25..d4e5768 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
@@ -405,7 +405,7 @@ VECT_VAR_DECL(expected_q_f32_9,hfloat,32,4) [] = { 
0xf3f2f1f0, 0xf7f6f5f4,
 VECT_VAR_DECL(expected_q_f32_10,hfloat,32,4) [] = { 0xfff1fff0, 0xfff3fff2,
0xfff5fff4, 0xfff7fff6 };
 
-/* Expected results for vreinterpretq_xx_f32.  */
+/* Expected results for vreinterpret_xx_f32.  */
 VECT_VAR_DECL(expected_xx_f32_1,int,8,8) [] = { 0x0, 0x0, 0x80, 0xc1,
0x0, 0x0, 0x70, 0xc1 };
 VECT_VAR_DECL(expected_xx_f32_2,int,16,4) [] = { 0x0, 0xc180, 0x0, 0xc170 };
-- 
1.9.1