Re: [Patch ARM/AArch64 11/11] Add missing tests for vreinterpret, operating of fp16 type.

[Kyrill Tkachov]

On 11/05/16 14:24, Christophe Lyon wrote:

2016-05-04  Christophe Lyon  

 * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add fp16 tests.
 * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise.
 * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: Likewise.


Ok.
Thanks for working on these!
Kyrill



Change-Id: Ic8061f1a5f3e042844a33a70c0f42a5f92c43c98

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
index 2570f73..0de2ab3 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
@@ -21,6 +21,8 @@ VECT_VAR_DECL(expected_s8_8,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 
0xf3,
0xf4, 0xf5, 0xf6, 0xf7 };
  VECT_VAR_DECL(expected_s8_9,int,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_s8_10,int,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
+0x00, 0xcb, 0x80, 0xca };
  
  /* Expected results for vreinterpret_s16_xx.  */

  VECT_VAR_DECL(expected_s16_1,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 
};
@@ -32,6 +34,7 @@ VECT_VAR_DECL(expected_s16_6,int,16,4) [] = { 0xfff0, 0x, 
0xfff1, 0x };
  VECT_VAR_DECL(expected_s16_7,int,16,4) [] = { 0xfff0, 0x, 0x, 0x 
};
  VECT_VAR_DECL(expected_s16_8,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 
};
  VECT_VAR_DECL(expected_s16_9,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 
};
+VECT_VAR_DECL(expected_s16_10,int,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 
};
  
  /* Expected results for vreinterpret_s32_xx.  */

  VECT_VAR_DECL(expected_s32_1,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
@@ -43,6 +46,7 @@ VECT_VAR_DECL(expected_s32_6,int,32,2) [] = { 0xfff0, 
0xfff1 };
  VECT_VAR_DECL(expected_s32_7,int,32,2) [] = { 0xfff0, 0x };
  VECT_VAR_DECL(expected_s32_8,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
  VECT_VAR_DECL(expected_s32_9,int,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_s32_10,int,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
  
  /* Expected results for vreinterpret_s64_xx.  */

  VECT_VAR_DECL(expected_s64_1,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
@@ -54,6 +58,7 @@ VECT_VAR_DECL(expected_s64_6,int,64,1) [] = { 
0xfff1fff0 };
  VECT_VAR_DECL(expected_s64_7,int,64,1) [] = { 0xfff0 };
  VECT_VAR_DECL(expected_s64_8,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
  VECT_VAR_DECL(expected_s64_9,int,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(expected_s64_10,int,64,1) [] = { 0xca80cb00cb80cc00 };
  
  /* Expected results for vreinterpret_u8_xx.  */

  VECT_VAR_DECL(expected_u8_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
@@ -74,6 +79,8 @@ VECT_VAR_DECL(expected_u8_8,uint,8,8) [] = { 0xf0, 0xf1, 
0xf2, 0xf3,
 0xf4, 0xf5, 0xf6, 0xf7 };
  VECT_VAR_DECL(expected_u8_9,uint,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
 0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_u8_10,uint,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
+ 0x00, 0xcb, 0x80, 0xca };
  
  /* Expected results for vreinterpret_u16_xx.  */

  VECT_VAR_DECL(expected_u16_1,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 
};
@@ -85,6 +92,7 @@ VECT_VAR_DECL(expected_u16_6,uint,16,4) [] = { 0xfff0, 
0x, 0xfff1, 0x };
  VECT_VAR_DECL(expected_u16_7,uint,16,4) [] = { 0xfff0, 0x, 0x, 0x 
};
  VECT_VAR_DECL(expected_u16_8,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 
};
  VECT_VAR_DECL(expected_u16_9,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 
};
+VECT_VAR_DECL(expected_u16_10,uint,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 
};
  
  /* Expected results for vreinterpret_u32_xx.  */

  VECT_VAR_DECL(expected_u32_1,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
@@ -96,6 +104,7 @@ VECT_VAR_DECL(expected_u32_6,uint,32,2) [] = { 0xfff1fff0, 
0xfff3fff2 };
  VECT_VAR_DECL(expected_u32_7,uint,32,2) [] = { 0xfff0, 0x };
  VECT_VAR_DECL(expected_u32_8,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
  VECT_VAR_DECL(expected_u32_9,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_u32_10,uint,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
  
  /* Expected results for vreinterpret_u64_xx.  */

  VECT_VAR_DECL(expected_u64_1,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
@@ -107,6 +116,7 @@ VECT_VAR_DECL(expected_u64_6,uint,64,1) [] = { 
0xfff3fff2fff1fff0 };
  VECT_VAR_DECL(expected_u64_7,uint,64,1) [] = { 0xfff1fff0 };
  VECT_VAR_DECL(expected_u64_8,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
  VECT_VAR_DECL(expected_u64_9,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(expected_u64_10,uint,64,1) [] = { 0xca80cb00cb80cc00 };
  
  /* Expected results for 

Re: [Patch ARM/AArch64 11/11] Add missing tests for vreinterpret, operating of fp16 type.

[James Greenhalgh]

On Wed, May 11, 2016 at 03:24:01PM +0200, Christophe Lyon wrote:
> 2016-05-04  Christophe Lyon  
> 
> * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add fp16 
> tests.
> * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise.
> * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: Likewise.

OK.

Thanks,
James

[Patch ARM/AArch64 11/11] Add missing tests for vreinterpret, operating of fp16 type.

[Christophe Lyon]

2016-05-04  Christophe Lyon  

* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add fp16 tests.
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: Likewise.

Change-Id: Ic8061f1a5f3e042844a33a70c0f42a5f92c43c98

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
index 2570f73..0de2ab3 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
@@ -21,6 +21,8 @@ VECT_VAR_DECL(expected_s8_8,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 
0xf3,
0xf4, 0xf5, 0xf6, 0xf7 };
 VECT_VAR_DECL(expected_s8_9,int,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_s8_10,int,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
+0x00, 0xcb, 0x80, 0xca };
 
 /* Expected results for vreinterpret_s16_xx.  */
 VECT_VAR_DECL(expected_s16_1,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
@@ -32,6 +34,7 @@ VECT_VAR_DECL(expected_s16_6,int,16,4) [] = { 0xfff0, 0x, 
0xfff1, 0x };
 VECT_VAR_DECL(expected_s16_7,int,16,4) [] = { 0xfff0, 0x, 0x, 0x };
 VECT_VAR_DECL(expected_s16_8,int,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 };
 VECT_VAR_DECL(expected_s16_9,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_s16_10,int,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 
};
 
 /* Expected results for vreinterpret_s32_xx.  */
 VECT_VAR_DECL(expected_s32_1,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
@@ -43,6 +46,7 @@ VECT_VAR_DECL(expected_s32_6,int,32,2) [] = { 0xfff0, 
0xfff1 };
 VECT_VAR_DECL(expected_s32_7,int,32,2) [] = { 0xfff0, 0x };
 VECT_VAR_DECL(expected_s32_8,int,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
 VECT_VAR_DECL(expected_s32_9,int,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_s32_10,int,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
 
 /* Expected results for vreinterpret_s64_xx.  */
 VECT_VAR_DECL(expected_s64_1,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
@@ -54,6 +58,7 @@ VECT_VAR_DECL(expected_s64_6,int,64,1) [] = { 
0xfff1fff0 };
 VECT_VAR_DECL(expected_s64_7,int,64,1) [] = { 0xfff0 };
 VECT_VAR_DECL(expected_s64_8,int,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
 VECT_VAR_DECL(expected_s64_9,int,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(expected_s64_10,int,64,1) [] = { 0xca80cb00cb80cc00 };
 
 /* Expected results for vreinterpret_u8_xx.  */
 VECT_VAR_DECL(expected_u8_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
@@ -74,6 +79,8 @@ VECT_VAR_DECL(expected_u8_8,uint,8,8) [] = { 0xf0, 0xf1, 
0xf2, 0xf3,
 0xf4, 0xf5, 0xf6, 0xf7 };
 VECT_VAR_DECL(expected_u8_9,uint,8,8) [] = { 0xf0, 0xff, 0xf1, 0xff,
 0xf2, 0xff, 0xf3, 0xff };
+VECT_VAR_DECL(expected_u8_10,uint,8,8) [] = { 0x00, 0xcc, 0x80, 0xcb,
+ 0x00, 0xcb, 0x80, 0xca };
 
 /* Expected results for vreinterpret_u16_xx.  */
 VECT_VAR_DECL(expected_u16_1,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 
};
@@ -85,6 +92,7 @@ VECT_VAR_DECL(expected_u16_6,uint,16,4) [] = { 0xfff0, 
0x, 0xfff1, 0x };
 VECT_VAR_DECL(expected_u16_7,uint,16,4) [] = { 0xfff0, 0x, 0x, 0x 
};
 VECT_VAR_DECL(expected_u16_8,uint,16,4) [] = { 0xf1f0, 0xf3f2, 0xf5f4, 0xf7f6 
};
 VECT_VAR_DECL(expected_u16_9,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 
};
+VECT_VAR_DECL(expected_u16_10,uint,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 
};
 
 /* Expected results for vreinterpret_u32_xx.  */
 VECT_VAR_DECL(expected_u32_1,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
@@ -96,6 +104,7 @@ VECT_VAR_DECL(expected_u32_6,uint,32,2) [] = { 0xfff1fff0, 
0xfff3fff2 };
 VECT_VAR_DECL(expected_u32_7,uint,32,2) [] = { 0xfff0, 0x };
 VECT_VAR_DECL(expected_u32_8,uint,32,2) [] = { 0xf3f2f1f0, 0xf7f6f5f4 };
 VECT_VAR_DECL(expected_u32_9,uint,32,2) [] = { 0xfff1fff0, 0xfff3fff2 };
+VECT_VAR_DECL(expected_u32_10,uint,32,2) [] = { 0xcb80cc00, 0xca80cb00 };
 
 /* Expected results for vreinterpret_u64_xx.  */
 VECT_VAR_DECL(expected_u64_1,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
@@ -107,6 +116,7 @@ VECT_VAR_DECL(expected_u64_6,uint,64,1) [] = { 
0xfff3fff2fff1fff0 };
 VECT_VAR_DECL(expected_u64_7,uint,64,1) [] = { 0xfff1fff0 };
 VECT_VAR_DECL(expected_u64_8,uint,64,1) [] = { 0xf7f6f5f4f3f2f1f0 };
 VECT_VAR_DECL(expected_u64_9,uint,64,1) [] = { 0xfff3fff2fff1fff0 };
+VECT_VAR_DECL(expected_u64_10,uint,64,1) [] = { 0xca80cb00cb80cc00 };
 
 /* Expected results for vreinterpret_p8_xx.  */
 VECT_VAR_DECL(expected_p8_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
@@ -127,6 +137,8 @@ VECT_VAR_DECL(expected_p8_8,poly,8,8) [] = { 0xf0,