[SH] Allow reg+disp address modes for atomics

2015-02-09 Thread Oleg Endo
Hi,

The attached patch fixes the lost mem aliasing info for atomic ops on SH
and allows the utilization of reg+disp address modes for atomic ops.
Actually it was supposed to be a pretty straight forward patch that just
replaces the open coded 'mem:QIHISI (match_operand:SI
"arith_reg_operand")' operands with something like 'match_operand:QIHISI
"atomic_mem_operand".  For most of the patterns that's what it does and
the changes are quite mechanical.  However, the QIHImode LLCS patterns
modify the address register of the mem operand and thus required some
special care (additional insns / splits).

I've briefly tested it with
make -k check-gcc RUNTESTFLAGS="sh.exp --target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m2e/-ml,-m2e/-mb,-m3/-ml,-m3/-mb,-m3e/-ml,-m3e/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"

to verify that the patterns work in isolation.  However, one thing I'm
not sure about is the fact that the predicate 'atomic_mem_operand_*' and
the Sra,Sdd,Ara,Add mem constraints are not in sync, i.e. the
constraints allow certain things which the predicates do not allow and
vice versa.

Kaz, could you please try the patch on sh4-linux?

Cheers,
Oleg


gcc/ChangeLog:

PR target/64661
* config/sh/sh-protos.h (TARGET_ATOMIC_ANY, TARGET_ATOMIC_STRICT,
TARGET_ATOMIC_SOFT_GUSA, TARGET_ATOMIC_HARD_LLCS,
TARGET_ATOMIC_SOFT_TCB, TARGET_ATOMIC_SOFT_IMASK): Add parentheses.
* config/sh/constraints.md (Ara, Add): New constraints.
* config/sh/sync.md (atomic_mem_operand_0, atomic_mem_operand_1): New
predicates.
(atomic_compare_and_swap, atomic_exchange): Use
atomic_mem_operand_0.  Don't use force_reg on the memory address.
(atomic_compare_and_swapsi_hard): Use atomic_mem_operand_0 predicate and
Sra constraint.  Convert to insn_and_split.  Add workaround for
PR 64974.
(atomic_compare_and_swap_hard): Copy to
atomic_compare_and_swap_hard_1.  Convert to insn_and_split.
Use atomic_mem_operand_0 predicate.
(atomic_compare_and_swap_soft_gusa,
atomic_exchange_soft_gusa): Use atomic_mem_operand_0 predicate and
AraAdd constraints.
(atomic_compare_and_swap_soft_tcb,
atomic_compare_and_swap_soft_imask,
atomic_exchange_soft_tcb, atomic_exchange_soft_imask): Use
atomic_mem_operand_0 predicate and SraSdd constraints.
(atomic_exchangesi_hard) Use atomic_mem_operand_0 predicate and Sra
constraint.
(atomic_exchange_hard): Copy to atomic_exchange_hard_1.
Convert to insn_and_split.  Use atomic_mem_operand_0 predicate.
(atomic_fetch_, atomic_fetch_nand,
atomic__fetch):
Use atomic_mem_operand_1.  Don't use force_reg on the memory address.
(atomic_fetch_si_hard, atomic_fetch_notsi_hard,
atomic_fetch_nandsi_hard, atomic__fetchsi_hard,
atomic_not_fetchsi_hard, atomic_nand_fetchsi_hard): Use
atomic_mem_operand_1 predicate and Sra constraint.
(atomic_fetch__hard): Copy to
atomic_fetch__hard_1.  Convert to insn_and_split.
Use atomic_mem_operand_1 predicate.
(atomic__hard): Copy to
atomic__hard_1.  Convert to insn_and_split.
Use atomic_mem_operand_1 predicate.
(atomic_fetch_nand_hard): Copy to atomic_fetch_nand_hard_1.
Convert to insn_and_split.  Use atomic_mem_operand_1 predicate.
(atomic_nand_hard): Copy to atomic_nand_hard_1.  Convert to
insn_and_split.  Use atomic_mem_operand_1 predicate.
(atomic__fetch_hard): Copy to
atomic__fetch_hard_1.  Convert to insn_and_split.
Use atomic_mem_operand_1 predicate.
(atomic_nand_fetch_hard): Copy to atomic_nand_fetch_hard_1.
Convert to insn_and_split.  Use atomic_mem_operand_1 predicate.
(atomic_fetch_not_hard, atomic_not_fetch_hard): Replace mems
in generated insn with original mem operand before emitting the insn.
(atomic_fetch__soft_gusa,
atomic_fetch_not_soft_gusa, atomic_fetch_nand_soft_gusa,
atomic__fetch_soft_gusa,
atomic_not_fetch_soft_gusa, atomic_nand_fetch_soft_gusa):
Use atomic_mem_operand_1 predicate and AraAdd constraints.
(atomic_fetch__soft_tcb,
atomic__soft_tcb, atomic_fetch_not_soft_tcb,
atomic_not_soft_tcb, atomic_fetch__soft_imask,
atomic_fetch_not_soft_imask, atomic_fetch_nand_soft_tcb,
atomic_nand_soft_tcb, atomic_fetch_nand_soft_imask,
atomic__fetch_soft_tcb,
atomic_not_fetch_soft_tcb,
atomic__fetch_soft_imask,
atomic_not_fetch_soft_imask, atomic_nand_fetch,
atomic_nand_fetch_soft_tcb, atomic_nand_fetch_soft_imask):
Use atomic_mem_operand_1 predicate and SraSdd constraints.

gcc/testsuite/ChangeLog:
PR target/64661
* gcc.taget/sh/pr64661-0.h: New.
* gcc.taget/sh/pr64661-1.c: New.
* gcc.taget/sh/pr64661-2.c: New.
* gcc.taget/sh/pr6466

Re: [SH] Allow reg+disp address modes for atomics

2015-02-10 Thread Kaz Kojima
Oleg Endo  wrote:
> The attached patch fixes the lost mem aliasing info for atomic ops on SH
> and allows the utilization of reg+disp address modes for atomic ops.
> Actually it was supposed to be a pretty straight forward patch that just
> replaces the open coded 'mem:QIHISI (match_operand:SI
> "arith_reg_operand")' operands with something like 'match_operand:QIHISI
> "atomic_mem_operand".  For most of the patterns that's what it does and
> the changes are quite mechanical.  However, the QIHImode LLCS patterns
> modify the address register of the mem operand and thus required some
> special care (additional insns / splits).
> 
> I've briefly tested it with
> make -k check-gcc RUNTESTFLAGS="sh.exp --target_board=sh-sim
> \{-m2/-ml,-m2/-mb,-m2a/-mb,-m2e/-ml,-m2e/-mb,-m3/-ml,-m3/-mb,-m3e/-ml,-m3e/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"
> 
> to verify that the patterns work in isolation.  However, one thing I'm
> not sure about is the fact that the predicate 'atomic_mem_operand_*' and
> the Sra,Sdd,Ara,Add mem constraints are not in sync, i.e. the
> constraints allow certain things which the predicates do not allow and
> vice versa.
> 
> Kaz, could you please try the patch on sh4-linux?

No new failures on sh4-unknown-linux-gnu.

Regards,
kaz


Re: [SH] Allow reg+disp address modes for atomics

2015-02-10 Thread Oleg Endo
On Tue, 2015-02-10 at 18:35 +0900, Kaz Kojima wrote:
> Oleg Endo  wrote:
> > The attached patch fixes the lost mem aliasing info for atomic ops on SH
> > and allows the utilization of reg+disp address modes for atomic ops.
> > Actually it was supposed to be a pretty straight forward patch that just
> > replaces the open coded 'mem:QIHISI (match_operand:SI
> > "arith_reg_operand")' operands with something like 'match_operand:QIHISI
> > "atomic_mem_operand".  For most of the patterns that's what it does and
> > the changes are quite mechanical.  However, the QIHImode LLCS patterns
> > modify the address register of the mem operand and thus required some
> > special care (additional insns / splits).
> > 
> > I've briefly tested it with
> > make -k check-gcc RUNTESTFLAGS="sh.exp --target_board=sh-sim
> > \{-m2/-ml,-m2/-mb,-m2a/-mb,-m2e/-ml,-m2e/-mb,-m3/-ml,-m3/-mb,-m3e/-ml,-m3e/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"
> > 
> > to verify that the patterns work in isolation.  However, one thing I'm
> > not sure about is the fact that the predicate 'atomic_mem_operand_*' and
> > the Sra,Sdd,Ara,Add mem constraints are not in sync, i.e. the
> > constraints allow certain things which the predicates do not allow and
> > vice versa.
> > 
> > Kaz, could you please try the patch on sh4-linux?
> 
> No new failures on sh4-unknown-linux-gnu.

Thanks.  Committed as r220594.

Cheers,
Oleg