If you compile the following C++ code at -O for Linux or Solaris:
int exchange (int *loc, int val)
{
return __atomic_exchange_4 (loc, val, __ATOMIC_SEQ_CST);
}
you get in the assembly file:
_Z8exchangePii:
.LLFB0:
mov %o0, %g1
membar 2
mov %o1, %o0
swap[%g1], %o0
jmp %o7+8
nop
membar 2 is membar #StoreLoad. Now Linux and Solaris default to TSO, which
means that the swap is effectively preceded by membar #StoreStore; moreover
swap is atomic and both a load and a store, so this preceding membar is also a
membar #StoreLoad; in the end, the generated membar is superfluous.
This is confirmed by the last sentence below from the V9 manual:
8.4.4.3 Total Store Order (TSO)
[...]
The rules for TSO are:
— Loads are blocking and ordered with respect to earlier loads.
— Stores are ordered with respect to stores.
— Atomic load-stores are ordered with respect to loads and stores.
The attached patchlet implements the missing bits to eliminate the membar, very
similarly to what Richard did for loads and the PSO model. Since it can only
affect the 3 hardware atomic primitives, I'd like to apply it on all active
branches. Any objections?
2013-07-30 Eric Botcazou ebotca...@adacore.com
* config/sparc/sparc.c (sparc_emit_membar_for_model) SMM_TSO: Add
the implied StoreLoad barrier for atomic operations if before.
--
Eric Botcazou
Index: config/sparc/sparc.c
===
--- config/sparc/sparc.c (revision 201177)
+++ config/sparc/sparc.c (working copy)
@@ -11318,6 +11319,11 @@ sparc_emit_membar_for_model (enum memmod
/* Total Store Ordering: all memory transactions with store semantics
are followed by an implied StoreStore. */
implied |= StoreStore;
+
+ /* If we're not looking for a raw barrer (before+after), then atomic
+ operations get the benefit of being both load and store. */
+ if (load_store == 3 before_after == 1)
+ implied |= StoreLoad;
/* FALLTHRU */
case SMM_PSO:
