Re: [alpha] Revert input_operand change for vms

[Richard Henderson]

On 03/24/2011 05:06 PM, Richard Henderson wrote:
> While purging Windows code, I failed to remember that VMS has a 32-bit
> mode as well, and thus this line still matters.

Bah.  This patch, not the other one.


r~
commit 3351cef043c126925829c9b414a087251dc67e45
Author: rth 
Date:   Fri Mar 25 00:04:19 2011 +

alpha: Revert change to input_operand for 32-bit vms.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@171428 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 85c45b6..aef5088 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2011-02-24  Richard Henderson  
+
+   * config/alpha/predicates.md (input_operand): Revert last change;
+   update comment to mention 32-bit VMS rather than Windows.
+
 2011-03-24  Nathan Froyd  
 
* function.c (instantiate_virtual_regs): Use FOR_EACH_BB and
diff --git a/gcc/config/alpha/predicates.md b/gcc/config/alpha/predicates.md
index 9514b8a..da76d4f 100644
--- a/gcc/config/alpha/predicates.md
+++ b/gcc/config/alpha/predicates.md
@@ -195,7 +195,8 @@
  || gotdtp_symbolic_operand (op, mode)
  || gottp_symbolic_operand (op, mode));
}
-  return mode == Pmode;
+  /* VMS still has a 32-bit mode.  */
+  return mode == ptr_mode || mode == Pmode;
 
 case HIGH:
   return (TARGET_EXPLICIT_RELOCS

[alpha] Revert input_operand change for vms

[Richard Henderson]

While purging Windows code, I failed to remember that VMS has a 32-bit
mode as well, and thus this line still matters.


r~
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 38d40b5..abd96c7 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -177,6 +177,19 @@
 
 (define_attr "cannot_copy" "false,true"
   (const_string "false"))
+
+;; Used to control the "enabled" attribute on a per-instruction basis.
+(define_attr "isa" "base,bwx,max,fix,cix,vms"
+  (const_string "base"))
+
+(define_attr "enabled" ""
+  (cond [(eq_attr "isa" "bwx") (symbol_ref "TARGET_BWX")
+(eq_attr "isa" "max")  (symbol_ref "TARGET_MAX")
+(eq_attr "isa" "fix")  (symbol_ref "TARGET_FIX")
+(eq_attr "isa" "cix")  (symbol_ref "TARGET_CIX")
+(eq_attr "isa" "vms")  (symbol_ref "TARGET_ABI_OPEN_VMS")
+   ]
+   (const_int 1)))
 
 ;; Include scheduling descriptions.
   
@@ -1092,130 +1105,60 @@
   operands[4] = GEN_INT (mask2);
 })
 
-(define_expand "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-   (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-{
-  if (! TARGET_BWX)
-operands[1] = force_reg (QImode, operands[1]);
-})
-
-(define_insn "*zero_extendqihi2_bwx"
+(define_insn "zero_extendqihi2"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
-   (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
-  "TARGET_BWX"
+   (zero_extend:HI
+ (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))]
+  ""
   "@
and %1,0xff,%0
ldbu %0,%1"
-  [(set_attr "type" "ilog,ild")])
-
-(define_insn "*zero_extendqihi2_nobwx"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-   (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
-  "! TARGET_BWX"
-  "and %1,0xff,%0"
-  [(set_attr "type" "ilog")])
-
-(define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-   (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-{
-  if (! TARGET_BWX)
-operands[1] = force_reg (QImode, operands[1]);
-})
+  [(set_attr "type" "ilog,ild")
+   (set_attr "isa" "*,bwx")])
 
-(define_insn "*zero_extendqisi2_bwx"
+(define_insn "zero_extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
-   (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
-  "TARGET_BWX"
+   (zero_extend:SI
+ (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))]
+  ""
   "@
and %1,0xff,%0
ldbu %0,%1"
-  [(set_attr "type" "ilog,ild")])
-
-(define_insn "*zero_extendqisi2_nobwx"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-   (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
-  "! TARGET_BWX"
-  "and %1,0xff,%0"
-  [(set_attr "type" "ilog")])
-
-(define_expand "zero_extendqidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-   (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-{
-  if (! TARGET_BWX)
-operands[1] = force_reg (QImode, operands[1]);
-})
+  [(set_attr "type" "ilog,ild")
+   (set_attr "isa" "*,bwx")])
 
-(define_insn "*zero_extendqidi2_bwx"
+(define_insn "zero_extendqidi2"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
-   (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
-  "TARGET_BWX"
+   (zero_extend:DI
+ (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))]
+  ""
   "@
and %1,0xff,%0
ldbu %0,%1"
-  [(set_attr "type" "ilog,ild")])
-
-(define_insn "*zero_extendqidi2_nobwx"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-   (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
-  "! TARGET_BWX"
-  "and %1,0xff,%0"
-  [(set_attr "type" "ilog")])
+  [(set_attr "type" "ilog,ild")
+   (set_attr "isa" "*,bwx")])
 
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-   (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
-  ""
-{
-  if (! TARGET_BWX)
-operands[1] = force_reg (HImode, operands[1]);
-})
-
-(define_insn "*zero_extendhisi2_bwx"
+(define_insn "zero_extendhisi2"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
-   (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
-  "TARGET_BWX"
+   (zero_extend:SI
+ (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))]
+  ""
   "@
zapnot %1,3,%0
ldwu %0,%1"
-  [(set_attr "type" "shift,ild")])
-
-(define_insn "*zero_extendhisi2_nobwx"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-   (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
-  "! TARGET_BWX"
-  "zapnot %1,3,%0"
-  [(set_attr "type" "shift")])
-
-(define_expand "zero_extendhidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-   (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
-  ""
-{
-  if (! TARGET_BWX)
-operands[1] = force_reg (HImode, operands[1]);
-})
+  [(set_attr "type" "shift,ild")
+   (s