Re: [committed] Update extract and insert patterns on PA

[John David Anglin]

Forgot this hunk in last change.

Dave
-- 
J. David Anglin  dave.ang...@nrc-cnrc.gc.ca
National Research Council of Canada  (613) 990-0752 (FAX: 952-6602)

2013-01-09  John David Anglin  dave.ang...@nrc-cnrc.gc.ca

* config/pa/pa.c (pa_emit_move_sequence): Replace calls to gen_insv
with calls to gen_insvsi/gen_insvdi.

Index: config/pa/pa.c
===
--- config/pa/pa.c  (revision 195003)
+++ config/pa/pa.c  (working copy)
@@ -2190,8 +2190,12 @@
  emit_insn (gen_rtx_SET (VOIDmode, temp,
  gen_rtx_HIGH (mode, operand1)));
  emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
- emit_insn (gen_insv (operand0, GEN_INT (32),
-  const0_rtx, temp));
+ if (mode == DImode)
+   emit_insn (gen_insvdi (operand0, GEN_INT (32),
+  const0_rtx, temp));
+ else
+   emit_insn (gen_insvsi (operand0, GEN_INT (32),
+  const0_rtx, temp));
}
  else
{
@@ -2212,8 +2216,12 @@
  pos -= 1;
}
 
- emit_insn (gen_insv (operand0, GEN_INT (len),
-  GEN_INT (pos), GEN_INT (v5)));
+ if (mode == DImode)
+   emit_insn (gen_insvdi (operand0, GEN_INT (len),
+  GEN_INT (pos), GEN_INT (v5)));
+ else
+   emit_insn (gen_insvsi (operand0, GEN_INT (len),
+  GEN_INT (pos), GEN_INT (v5)));
 
  len = pos  0  pos  5 ? pos : 5;
  pos -= len;

[committed] Update extract and insert patterns on PA

[John David Anglin]

The attached change updates the extract and insert patterns on HP PA.
It removes the deprecated extzv, extv and insv expanders, replacing them
with SI and DI mode variant.  Operand predicates are tightened in these
and related insn patterns.  Predicates are also tightened some shift
patterns.

Two new shift patterns are introduced which I plan to use to support
misalign loads.

Tested on hppa2.0w-hp-hpux11.11 and hppa64-hp-hpux11.11 with no observed
regressions.

Committed to trunk.

Dave
-- 
J. David Anglin  dave.ang...@nrc-cnrc.gc.ca
National Research Council of Canada  (613) 990-0752 (FAX: 952-6602)

2013-01-08  John David Anglin  dave.ang...@nrc-cnrc.gc.ca

* config/pa/pa.h (VAL_U6_BITS_P): Define.
(INT_U6_BITS): Likewise.
* config/pa/predicates.md (uint6_operand): New predicate.
(shift5_operand, shift6_operand): Likewise.
* config/pa/pa.md (lshrsi3, rotrsi3): Use shift5_operand instead of
arith32_operand.
(lshrdi3): Use shift6_operand.
(shrpsi4, shrpdi4): New insn patterns.
(extzv): Delete expander.
(extzvsi, extzvdi): New expanders.  Use uint5_operand and uint6_operand
predicates in unamed zero extract patterns.  Tighten common constraint.
(extv): Delete expander.
(extvsi, extvdi): New expanders.  Use uint5_operand and uint6_operand
predicates in unamed sign extract patterns.  Tighten common constraint.
(insv): Delete expander.
(insvsi, insvdi): New expanders.  Use uint5_operand and uint6_operand
predicates in unamed insert patterns.  Tighten common constraint.
Change uint32_operand predicate to uint6_operand predicate in unamed
DImode pattern to insert constant values of type 1...1.

Index: config/pa/pa.h
===
--- config/pa/pa.h  (revision 195003)
+++ config/pa/pa.h  (working copy)
@@ -956,6 +956,9 @@
 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X)  0x20)
 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
 
+#define VAL_U6_BITS_P(X) ((unsigned HOST_WIDE_INT)(X)  0x40)
+#define INT_U6_BITS(X) VAL_U6_BITS_P (INTVAL (X))
+
 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400  0x800)
 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
 
Index: config/pa/predicates.md
===
--- config/pa/predicates.md (revision 195003)
+++ config/pa/predicates.md (working copy)
@@ -32,6 +32,13 @@
(match_test INT_U5_BITS (op
 
 ;; Return truth value of whether OP is an integer which fits the range
+;; constraining 6-bit unsigned immediate operands in three-address insns.
+
+(define_predicate uint6_operand
+  (and (match_code const_int)
+   (match_test INT_U6_BITS (op
+
+;; Return truth value of whether OP is an integer which fits the range
 ;; constraining 11-bit signed immediate operands in three-address insns.
 
 (define_predicate int11_operand
@@ -125,6 +132,20 @@
   (ior (match_operand 0 register_operand)
(match_code const_int)))
 
+;; Return truth value of whether OP can be used as a shift operand in
+;; a shift insn that accepts registers of mode MODE or 5-bit shift amounts.
+
+(define_predicate shift5_operand
+  (ior (match_operand 0 register_operand)
+   (match_operand 0 uint5_operand)))
+
+;; Return truth value of whether OP can be used as a shift operand in
+;; a shift insn that accepts registers of mode MODE or 6-bit shift amounts.
+
+(define_predicate shift6_operand
+  (ior (match_operand 0 register_operand)
+   (match_operand 0 uint6_operand)))
+
 ;; True iff OP can be used as an operand in an adddi3 insn.
 
 (define_predicate adddi3_operand
Index: config/pa/pa.md
===
--- config/pa/pa.md (revision 195003)
+++ config/pa/pa.md (working copy)
@@ -6584,7 +6584,7 @@
 (define_insn lshrsi3
   [(set (match_operand:SI 0 register_operand =r,r)
(lshiftrt:SI (match_operand:SI 1 register_operand r,r)
-(match_operand:SI 2 arith32_operand q,n)))]
+(match_operand:SI 2 shift5_operand q,n)))]
   
   @
{vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
@@ -6595,7 +6595,7 @@
 (define_insn lshrdi3
   [(set (match_operand:DI 0 register_operand =r,r)
(lshiftrt:DI (match_operand:DI 1 register_operand r,r)
-(match_operand:DI 2 arith32_operand q,n)))]
+(match_operand:DI 2 shift6_operand q,n)))]
   TARGET_64BIT
   @
shrpd %%r0,%1,%%sar,%0
@@ -6603,10 +6603,40 @@
   [(set_attr type shift)
(set_attr length 4)])
 
+; Shift right pair word 0 to 31 bits.
+(define_insn shrpsi4
+  [(set (match_operand:SI 0 register_operand =r,r)
+   (ior:SI (ashift:SI (match_operand:SI 1 register_operand r,r)
+  (minus:SI (const_int 32)
+