Re: Add support for bitwise reductions

[Christophe Lyon]

On 26 January 2018 at 10:33, Richard Sandiford
 wrote:
> Christophe Lyon  writes:
>> On 25 January 2018 at 11:24, Richard Sandiford
>>  wrote:
>>> Rainer Orth  writes:
 Jeff Law  writes:
> On 11/22/2017 11:12 AM, Richard Sandiford wrote:
>> Richard Sandiford  writes:
>>> This patch adds support for the SVE bitwise reduction instructions
>>> (ANDV, ORV and EORV).  It's a fairly mechanical extension of existing
>>> REDUC_* operators.
>>>
>>> Tested on aarch64-linux-gnu (with and without SVE), x86_64-linux-gnu
>>> and powerpc64le-linux-gnu.
>>
>> Here's an updated version that applies on top of the recent
>> removal of REDUC_*_EXPR.  Tested as before.
>>
>> Thanks,
>> Richard
>>
>>
>> 2017-11-22  Richard Sandiford  
>> Alan Hayward  
>> David Sherwood  
>>
>> gcc/
>> * optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab)
>> (reduc_xor_scal_optab): New optabs.
>> * doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m})
>> (reduc_xor_scal_@var{m}): Document.
>> * doc/sourcebuild.texi (vect_logical_reduc): Likewise.
>> * internal-fn.def (IFN_REDUC_AND, IFN_REDUC_IOR, IFN_REDUC_XOR): New
>> internal functions.
>> * fold-const-call.c (fold_const_call): Handle them.
>> * tree-vect-loop.c (reduction_fn_for_scalar_code): Return the new
>> internal functions for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR.
>> * config/aarch64/aarch64-sve.md (reduc__scal_):
>> (*reduc__scal_): New patterns.
>> * config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV)
>> (UNSPEC_XORV): New unspecs.
>> (optab): Add entries for them.
>> (BITWISEV): New int iterator.
>> (bit_reduc_op): New int attributes.
>>
>> gcc/testsuite/
>> * lib/target-supports.exp 
>> (check_effective_target_vect_logical_reduc):
>> New proc.
>> * gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc
>> and add an associated scan-dump test.  Prevent vectorization
>> of the first two loops.
>> * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>> * gcc.target/aarch64/sve_reduc_1.c: Add AND, IOR and XOR reductions.
>> * gcc.target/aarch64/sve_reduc_2.c: Likewise.
>> * gcc.target/aarch64/sve_reduc_1_run.c: Likewise.
>> (INIT_VECTOR): Tweak initial value so that some bits are always set.
>> * gcc.target/aarch64/sve_reduc_2_run.c: Likewise.
> OK.
> Jeff

 Two tests have regressed on sparc-sun-solaris2.*:

 +FAIL: gcc.dg/vect/vect-reduc-or_1.c -flto -ffat-lto-objects
 scan-tree-dump vect "Reduce using vector shifts"
 +FAIL: gcc.dg/vect/vect-reduc-or_1.c scan-tree-dump vect "Reduce using
 vector shifts"
 +FAIL: gcc.dg/vect/vect-reduc-or_2.c -flto -ffat-lto-objects
 scan-tree-dump vect "Reduce using vector shifts"
 +FAIL: gcc.dg/vect/vect-reduc-or_2.c scan-tree-dump vect "Reduce using
 vector shifts"
>>>
>>> Bah, I think I broke this yesterday in:
>>>
>>> 2018-01-24  Richard Sandiford  
>>>
>>> PR testsuite/83889
>>> [...]
>>> * gcc.dg/vect/vect-reduc-or_1.c: Remove conditional dg-do run.
>>> * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>>>
>>> (r257022), which removed:
>>>
>>>   /* { dg-do run { target { whole_vector_shift || vect_logical_reduc } } } 
>>> */
>>>
>>> I'd somehow thought that the dump lines in these two tests were already
>>> guarded, but they weren't.
>>>
>>> Tested on aarch64-linux-gnu and x86_64-linux-gnu and applied as obvious.
>>> Sorry for the breakage.
>>>
>>> Richard
>>>
>>>
>>
>> Hi Richard,
>>
>> While this fixes the regression on armeb (same as on sparc), the
>> effect on arm-none-linux-gnueabi and arm-none-eabi
>> is that the tests are now skipped, while they used to pass.
>> Is this expected? Or is the guard you added too restrictive?
>
> I think that means that the tests went from UNSUPPORTED to PASS on
> the last two targets with r257022.  Is that right?
>
Yes, that's what I meant.

> It's expected in the sense that whole_vector_shift isn't true for
> any arm*-*-* target, and historically this test was restricted to
> whole_vector_shift (apart from the blip this week).
>
OK, then. Just surprising to see PASS disappear.

Thanks,

Christophe

> Thanks,
> Richard
>
>> Thanks,
>>
>> Christophe
>>
>>> 2018-01-25  Richard Sandiford  
>>>
>>> gcc/testsuite/
>>> * gcc.dg/vect/vect-reduc-or_1.c: Require whole_vector_shift for
>>> the shift dump line.
>>> * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>>>
>>> Index: 

Re: Add support for bitwise reductions

[Richard Sandiford]

Christophe Lyon  writes:
> On 25 January 2018 at 11:24, Richard Sandiford
>  wrote:
>> Rainer Orth  writes:
>>> Jeff Law  writes:
 On 11/22/2017 11:12 AM, Richard Sandiford wrote:
> Richard Sandiford  writes:
>> This patch adds support for the SVE bitwise reduction instructions
>> (ANDV, ORV and EORV).  It's a fairly mechanical extension of existing
>> REDUC_* operators.
>>
>> Tested on aarch64-linux-gnu (with and without SVE), x86_64-linux-gnu
>> and powerpc64le-linux-gnu.
>
> Here's an updated version that applies on top of the recent
> removal of REDUC_*_EXPR.  Tested as before.
>
> Thanks,
> Richard
>
>
> 2017-11-22  Richard Sandiford  
> Alan Hayward  
> David Sherwood  
>
> gcc/
> * optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab)
> (reduc_xor_scal_optab): New optabs.
> * doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m})
> (reduc_xor_scal_@var{m}): Document.
> * doc/sourcebuild.texi (vect_logical_reduc): Likewise.
> * internal-fn.def (IFN_REDUC_AND, IFN_REDUC_IOR, IFN_REDUC_XOR): New
> internal functions.
> * fold-const-call.c (fold_const_call): Handle them.
> * tree-vect-loop.c (reduction_fn_for_scalar_code): Return the new
> internal functions for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR.
> * config/aarch64/aarch64-sve.md (reduc__scal_):
> (*reduc__scal_): New patterns.
> * config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV)
> (UNSPEC_XORV): New unspecs.
> (optab): Add entries for them.
> (BITWISEV): New int iterator.
> (bit_reduc_op): New int attributes.
>
> gcc/testsuite/
> * lib/target-supports.exp (check_effective_target_vect_logical_reduc):
> New proc.
> * gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc
> and add an associated scan-dump test.  Prevent vectorization
> of the first two loops.
> * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
> * gcc.target/aarch64/sve_reduc_1.c: Add AND, IOR and XOR reductions.
> * gcc.target/aarch64/sve_reduc_2.c: Likewise.
> * gcc.target/aarch64/sve_reduc_1_run.c: Likewise.
> (INIT_VECTOR): Tweak initial value so that some bits are always set.
> * gcc.target/aarch64/sve_reduc_2_run.c: Likewise.
 OK.
 Jeff
>>>
>>> Two tests have regressed on sparc-sun-solaris2.*:
>>>
>>> +FAIL: gcc.dg/vect/vect-reduc-or_1.c -flto -ffat-lto-objects
>>> scan-tree-dump vect "Reduce using vector shifts"
>>> +FAIL: gcc.dg/vect/vect-reduc-or_1.c scan-tree-dump vect "Reduce using
>>> vector shifts"
>>> +FAIL: gcc.dg/vect/vect-reduc-or_2.c -flto -ffat-lto-objects
>>> scan-tree-dump vect "Reduce using vector shifts"
>>> +FAIL: gcc.dg/vect/vect-reduc-or_2.c scan-tree-dump vect "Reduce using
>>> vector shifts"
>>
>> Bah, I think I broke this yesterday in:
>>
>> 2018-01-24  Richard Sandiford  
>>
>> PR testsuite/83889
>> [...]
>> * gcc.dg/vect/vect-reduc-or_1.c: Remove conditional dg-do run.
>> * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>>
>> (r257022), which removed:
>>
>>   /* { dg-do run { target { whole_vector_shift || vect_logical_reduc } } } */
>>
>> I'd somehow thought that the dump lines in these two tests were already
>> guarded, but they weren't.
>>
>> Tested on aarch64-linux-gnu and x86_64-linux-gnu and applied as obvious.
>> Sorry for the breakage.
>>
>> Richard
>>
>>
>
> Hi Richard,
>
> While this fixes the regression on armeb (same as on sparc), the
> effect on arm-none-linux-gnueabi and arm-none-eabi
> is that the tests are now skipped, while they used to pass.
> Is this expected? Or is the guard you added too restrictive?

I think that means that the tests went from UNSUPPORTED to PASS on
the last two targets with r257022.  Is that right?

It's expected in the sense that whole_vector_shift isn't true for
any arm*-*-* target, and historically this test was restricted to
whole_vector_shift (apart from the blip this week).

Thanks,
Richard

> Thanks,
>
> Christophe
>
>> 2018-01-25  Richard Sandiford  
>>
>> gcc/testsuite/
>> * gcc.dg/vect/vect-reduc-or_1.c: Require whole_vector_shift for
>> the shift dump line.
>> * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>>
>> Index: gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c
>> ===
>> --- gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c 2018-01-24 
>> 16:22:31.724089913 +
>> +++ gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c 2018-01-25 
>> 10:16:16.283500281 +
>> @@ -45,5 +45,5 @@ main 

Re: Add support for bitwise reductions

[Christophe Lyon]

On 25 January 2018 at 11:24, Richard Sandiford
 wrote:
> Rainer Orth  writes:
>> Jeff Law  writes:
>>> On 11/22/2017 11:12 AM, Richard Sandiford wrote:
 Richard Sandiford  writes:
> This patch adds support for the SVE bitwise reduction instructions
> (ANDV, ORV and EORV).  It's a fairly mechanical extension of existing
> REDUC_* operators.
>
> Tested on aarch64-linux-gnu (with and without SVE), x86_64-linux-gnu
> and powerpc64le-linux-gnu.

 Here's an updated version that applies on top of the recent
 removal of REDUC_*_EXPR.  Tested as before.

 Thanks,
 Richard


 2017-11-22  Richard Sandiford  
 Alan Hayward  
 David Sherwood  

 gcc/
 * optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab)
 (reduc_xor_scal_optab): New optabs.
 * doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m})
 (reduc_xor_scal_@var{m}): Document.
 * doc/sourcebuild.texi (vect_logical_reduc): Likewise.
 * internal-fn.def (IFN_REDUC_AND, IFN_REDUC_IOR, IFN_REDUC_XOR): New
 internal functions.
 * fold-const-call.c (fold_const_call): Handle them.
 * tree-vect-loop.c (reduction_fn_for_scalar_code): Return the new
 internal functions for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR.
 * config/aarch64/aarch64-sve.md (reduc__scal_):
 (*reduc__scal_): New patterns.
 * config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV)
 (UNSPEC_XORV): New unspecs.
 (optab): Add entries for them.
 (BITWISEV): New int iterator.
 (bit_reduc_op): New int attributes.

 gcc/testsuite/
 * lib/target-supports.exp (check_effective_target_vect_logical_reduc):
 New proc.
 * gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc
 and add an associated scan-dump test.  Prevent vectorization
 of the first two loops.
 * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
 * gcc.target/aarch64/sve_reduc_1.c: Add AND, IOR and XOR reductions.
 * gcc.target/aarch64/sve_reduc_2.c: Likewise.
 * gcc.target/aarch64/sve_reduc_1_run.c: Likewise.
 (INIT_VECTOR): Tweak initial value so that some bits are always set.
 * gcc.target/aarch64/sve_reduc_2_run.c: Likewise.
>>> OK.
>>> Jeff
>>
>> Two tests have regressed on sparc-sun-solaris2.*:
>>
>> +FAIL: gcc.dg/vect/vect-reduc-or_1.c -flto -ffat-lto-objects
>> scan-tree-dump vect "Reduce using vector shifts"
>> +FAIL: gcc.dg/vect/vect-reduc-or_1.c scan-tree-dump vect "Reduce using
>> vector shifts"
>> +FAIL: gcc.dg/vect/vect-reduc-or_2.c -flto -ffat-lto-objects
>> scan-tree-dump vect "Reduce using vector shifts"
>> +FAIL: gcc.dg/vect/vect-reduc-or_2.c scan-tree-dump vect "Reduce using
>> vector shifts"
>
> Bah, I think I broke this yesterday in:
>
> 2018-01-24  Richard Sandiford  
>
> PR testsuite/83889
> [...]
> * gcc.dg/vect/vect-reduc-or_1.c: Remove conditional dg-do run.
> * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>
> (r257022), which removed:
>
>   /* { dg-do run { target { whole_vector_shift || vect_logical_reduc } } } */
>
> I'd somehow thought that the dump lines in these two tests were already
> guarded, but they weren't.
>
> Tested on aarch64-linux-gnu and x86_64-linux-gnu and applied as obvious.
> Sorry for the breakage.
>
> Richard
>
>

Hi Richard,

While this fixes the regression on armeb (same as on sparc), the
effect on arm-none-linux-gnueabi and arm-none-eabi
is that the tests are now skipped, while they used to pass.
Is this expected? Or is the guard you added too restrictive?

Thanks,

Christophe

> 2018-01-25  Richard Sandiford  
>
> gcc/testsuite/
> * gcc.dg/vect/vect-reduc-or_1.c: Require whole_vector_shift for
> the shift dump line.
> * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>
> Index: gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c
> ===
> --- gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c 2018-01-24 16:22:31.724089913 
> +
> +++ gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c 2018-01-25 10:16:16.283500281 
> +
> @@ -45,5 +45,5 @@ main (unsigned char argc, char **argv)
>return 0;
>  }
>
> -/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" { target 
> { ! vect_logical_reduc } } } } */
> +/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" { target 
> { whole_vector_shift && { ! vect_logical_reduc } } } } } */
>  /* { dg-final { scan-tree-dump "Reduce using direct vector reduction" "vect" 
> { target vect_logical_reduc } } } */
> Index: gcc/testsuite/gcc.dg/vect/vect-reduc-or_2.c
> 

Re: Add support for bitwise reductions

[Richard Sandiford]

Rainer Orth  writes:
> Jeff Law  writes:
>> On 11/22/2017 11:12 AM, Richard Sandiford wrote:
>>> Richard Sandiford  writes:
 This patch adds support for the SVE bitwise reduction instructions
 (ANDV, ORV and EORV).  It's a fairly mechanical extension of existing
 REDUC_* operators.

 Tested on aarch64-linux-gnu (with and without SVE), x86_64-linux-gnu
 and powerpc64le-linux-gnu.
>>> 
>>> Here's an updated version that applies on top of the recent
>>> removal of REDUC_*_EXPR.  Tested as before.
>>> 
>>> Thanks,
>>> Richard
>>> 
>>> 
>>> 2017-11-22  Richard Sandiford  
>>> Alan Hayward  
>>> David Sherwood  
>>> 
>>> gcc/
>>> * optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab)
>>> (reduc_xor_scal_optab): New optabs.
>>> * doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m})
>>> (reduc_xor_scal_@var{m}): Document.
>>> * doc/sourcebuild.texi (vect_logical_reduc): Likewise.
>>> * internal-fn.def (IFN_REDUC_AND, IFN_REDUC_IOR, IFN_REDUC_XOR): New
>>> internal functions.
>>> * fold-const-call.c (fold_const_call): Handle them.
>>> * tree-vect-loop.c (reduction_fn_for_scalar_code): Return the new
>>> internal functions for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR.
>>> * config/aarch64/aarch64-sve.md (reduc__scal_):
>>> (*reduc__scal_): New patterns.
>>> * config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV)
>>> (UNSPEC_XORV): New unspecs.
>>> (optab): Add entries for them.
>>> (BITWISEV): New int iterator.
>>> (bit_reduc_op): New int attributes.
>>> 
>>> gcc/testsuite/
>>> * lib/target-supports.exp (check_effective_target_vect_logical_reduc):
>>> New proc.
>>> * gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc
>>> and add an associated scan-dump test.  Prevent vectorization
>>> of the first two loops.
>>> * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>>> * gcc.target/aarch64/sve_reduc_1.c: Add AND, IOR and XOR reductions.
>>> * gcc.target/aarch64/sve_reduc_2.c: Likewise.
>>> * gcc.target/aarch64/sve_reduc_1_run.c: Likewise.
>>> (INIT_VECTOR): Tweak initial value so that some bits are always set.
>>> * gcc.target/aarch64/sve_reduc_2_run.c: Likewise.
>> OK.
>> Jeff
>
> Two tests have regressed on sparc-sun-solaris2.*:
>
> +FAIL: gcc.dg/vect/vect-reduc-or_1.c -flto -ffat-lto-objects
> scan-tree-dump vect "Reduce using vector shifts"
> +FAIL: gcc.dg/vect/vect-reduc-or_1.c scan-tree-dump vect "Reduce using
> vector shifts"
> +FAIL: gcc.dg/vect/vect-reduc-or_2.c -flto -ffat-lto-objects
> scan-tree-dump vect "Reduce using vector shifts"
> +FAIL: gcc.dg/vect/vect-reduc-or_2.c scan-tree-dump vect "Reduce using
> vector shifts"

Bah, I think I broke this yesterday in:

2018-01-24  Richard Sandiford  

PR testsuite/83889
[...]
* gcc.dg/vect/vect-reduc-or_1.c: Remove conditional dg-do run.
* gcc.dg/vect/vect-reduc-or_2.c: Likewise.

(r257022), which removed:

  /* { dg-do run { target { whole_vector_shift || vect_logical_reduc } } } */

I'd somehow thought that the dump lines in these two tests were already
guarded, but they weren't.

Tested on aarch64-linux-gnu and x86_64-linux-gnu and applied as obvious.
Sorry for the breakage.

Richard


2018-01-25  Richard Sandiford  

gcc/testsuite/
* gcc.dg/vect/vect-reduc-or_1.c: Require whole_vector_shift for
the shift dump line.
* gcc.dg/vect/vect-reduc-or_2.c: Likewise.

Index: gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c
===
--- gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c 2018-01-24 16:22:31.724089913 
+
+++ gcc/testsuite/gcc.dg/vect/vect-reduc-or_1.c 2018-01-25 10:16:16.283500281 
+
@@ -45,5 +45,5 @@ main (unsigned char argc, char **argv)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" { target { 
! vect_logical_reduc } } } } */
+/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" { target { 
whole_vector_shift && { ! vect_logical_reduc } } } } } */
 /* { dg-final { scan-tree-dump "Reduce using direct vector reduction" "vect" { 
target vect_logical_reduc } } } */
Index: gcc/testsuite/gcc.dg/vect/vect-reduc-or_2.c
===
--- gcc/testsuite/gcc.dg/vect/vect-reduc-or_2.c 2018-01-24 16:22:31.724089913 
+
+++ gcc/testsuite/gcc.dg/vect/vect-reduc-or_2.c 2018-01-25 10:16:16.284500239 
+
@@ -44,5 +44,5 @@ main (unsigned char argc, char **argv)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" { target { 
! vect_logical_reduc } } } } */
+/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" { target { 

Re: Add support for bitwise reductions

[Rainer Orth]

Jeff Law  writes:

> On 11/22/2017 11:12 AM, Richard Sandiford wrote:
>> Richard Sandiford  writes:
>>> This patch adds support for the SVE bitwise reduction instructions
>>> (ANDV, ORV and EORV).  It's a fairly mechanical extension of existing
>>> REDUC_* operators.
>>>
>>> Tested on aarch64-linux-gnu (with and without SVE), x86_64-linux-gnu
>>> and powerpc64le-linux-gnu.
>> 
>> Here's an updated version that applies on top of the recent
>> removal of REDUC_*_EXPR.  Tested as before.
>> 
>> Thanks,
>> Richard
>> 
>> 
>> 2017-11-22  Richard Sandiford  
>>  Alan Hayward  
>>  David Sherwood  
>> 
>> gcc/
>>  * optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab)
>>  (reduc_xor_scal_optab): New optabs.
>>  * doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m})
>>  (reduc_xor_scal_@var{m}): Document.
>>  * doc/sourcebuild.texi (vect_logical_reduc): Likewise.
>>  * internal-fn.def (IFN_REDUC_AND, IFN_REDUC_IOR, IFN_REDUC_XOR): New
>>  internal functions.
>>  * fold-const-call.c (fold_const_call): Handle them.
>>  * tree-vect-loop.c (reduction_fn_for_scalar_code): Return the new
>>  internal functions for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR.
>>  * config/aarch64/aarch64-sve.md (reduc__scal_):
>>  (*reduc__scal_): New patterns.
>>  * config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV)
>>  (UNSPEC_XORV): New unspecs.
>>  (optab): Add entries for them.
>>  (BITWISEV): New int iterator.
>>  (bit_reduc_op): New int attributes.
>> 
>> gcc/testsuite/
>>  * lib/target-supports.exp (check_effective_target_vect_logical_reduc):
>>  New proc.
>>  * gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc
>>  and add an associated scan-dump test.  Prevent vectorization
>>  of the first two loops.
>>  * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>>  * gcc.target/aarch64/sve_reduc_1.c: Add AND, IOR and XOR reductions.
>>  * gcc.target/aarch64/sve_reduc_2.c: Likewise.
>>  * gcc.target/aarch64/sve_reduc_1_run.c: Likewise.
>>  (INIT_VECTOR): Tweak initial value so that some bits are always set.
>>  * gcc.target/aarch64/sve_reduc_2_run.c: Likewise.
> OK.
> Jeff

Two tests have regressed on sparc-sun-solaris2.*:

+FAIL: gcc.dg/vect/vect-reduc-or_1.c -flto -ffat-lto-objects  scan-tree-dump 
vect "Reduce using vector shifts"
+FAIL: gcc.dg/vect/vect-reduc-or_1.c scan-tree-dump vect "Reduce using vector 
shifts"
+FAIL: gcc.dg/vect/vect-reduc-or_2.c -flto -ffat-lto-objects  scan-tree-dump 
vect "Reduce using vector shifts"
+FAIL: gcc.dg/vect/vect-reduc-or_2.c scan-tree-dump vect "Reduce using vector 
shifts"

Rainer

-- 
-
Rainer Orth, Center for Biotechnology, Bielefeld University

Re: Add support for bitwise reductions

[James Greenhalgh]

On Thu, Dec 14, 2017 at 12:36:58AM +, Jeff Law wrote:
> On 11/22/2017 11:12 AM, Richard Sandiford wrote:
> > Richard Sandiford  writes:
> >> This patch adds support for the SVE bitwise reduction instructions
> >> (ANDV, ORV and EORV).  It's a fairly mechanical extension of existing
> >> REDUC_* operators.
> >>
> >> Tested on aarch64-linux-gnu (with and without SVE), x86_64-linux-gnu
> >> and powerpc64le-linux-gnu.
> > 
> > Here's an updated version that applies on top of the recent
> > removal of REDUC_*_EXPR.  Tested as before.
> > 
> > Thanks,
> > Richard
> > 
> > 
> > 2017-11-22  Richard Sandiford  
> > Alan Hayward  
> > David Sherwood  
> > 
> > gcc/
> > * optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab)
> > (reduc_xor_scal_optab): New optabs.
> > * doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m})
> > (reduc_xor_scal_@var{m}): Document.
> > * doc/sourcebuild.texi (vect_logical_reduc): Likewise.
> > * internal-fn.def (IFN_REDUC_AND, IFN_REDUC_IOR, IFN_REDUC_XOR): New
> > internal functions.
> > * fold-const-call.c (fold_const_call): Handle them.
> > * tree-vect-loop.c (reduction_fn_for_scalar_code): Return the new
> > internal functions for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR.
> > * config/aarch64/aarch64-sve.md (reduc__scal_):
> > (*reduc__scal_): New patterns.
> > * config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV)
> > (UNSPEC_XORV): New unspecs.
> > (optab): Add entries for them.
> > (BITWISEV): New int iterator.
> > (bit_reduc_op): New int attributes.
> > 
> > gcc/testsuite/
> > * lib/target-supports.exp (check_effective_target_vect_logical_reduc):
> > New proc.
> > * gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc
> > and add an associated scan-dump test.  Prevent vectorization
> > of the first two loops.
> > * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
> > * gcc.target/aarch64/sve_reduc_1.c: Add AND, IOR and XOR reductions.
> > * gcc.target/aarch64/sve_reduc_2.c: Likewise.
> > * gcc.target/aarch64/sve_reduc_1_run.c: Likewise.
> > (INIT_VECTOR): Tweak initial value so that some bits are always set.
> > * gcc.target/aarch64/sve_reduc_2_run.c: Likewise.
> OK.
> Jeff

I'm also OK with the AArch64 parts.

James

Re: Add support for bitwise reductions

[Jeff Law]

On 11/22/2017 11:12 AM, Richard Sandiford wrote:
> Richard Sandiford  writes:
>> This patch adds support for the SVE bitwise reduction instructions
>> (ANDV, ORV and EORV).  It's a fairly mechanical extension of existing
>> REDUC_* operators.
>>
>> Tested on aarch64-linux-gnu (with and without SVE), x86_64-linux-gnu
>> and powerpc64le-linux-gnu.
> 
> Here's an updated version that applies on top of the recent
> removal of REDUC_*_EXPR.  Tested as before.
> 
> Thanks,
> Richard
> 
> 
> 2017-11-22  Richard Sandiford  
>   Alan Hayward  
>   David Sherwood  
> 
> gcc/
>   * optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab)
>   (reduc_xor_scal_optab): New optabs.
>   * doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m})
>   (reduc_xor_scal_@var{m}): Document.
>   * doc/sourcebuild.texi (vect_logical_reduc): Likewise.
>   * internal-fn.def (IFN_REDUC_AND, IFN_REDUC_IOR, IFN_REDUC_XOR): New
>   internal functions.
>   * fold-const-call.c (fold_const_call): Handle them.
>   * tree-vect-loop.c (reduction_fn_for_scalar_code): Return the new
>   internal functions for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR.
>   * config/aarch64/aarch64-sve.md (reduc__scal_):
>   (*reduc__scal_): New patterns.
>   * config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV)
>   (UNSPEC_XORV): New unspecs.
>   (optab): Add entries for them.
>   (BITWISEV): New int iterator.
>   (bit_reduc_op): New int attributes.
> 
> gcc/testsuite/
>   * lib/target-supports.exp (check_effective_target_vect_logical_reduc):
>   New proc.
>   * gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc
>   and add an associated scan-dump test.  Prevent vectorization
>   of the first two loops.
>   * gcc.dg/vect/vect-reduc-or_2.c: Likewise.
>   * gcc.target/aarch64/sve_reduc_1.c: Add AND, IOR and XOR reductions.
>   * gcc.target/aarch64/sve_reduc_2.c: Likewise.
>   * gcc.target/aarch64/sve_reduc_1_run.c: Likewise.
>   (INIT_VECTOR): Tweak initial value so that some bits are always set.
>   * gcc.target/aarch64/sve_reduc_2_run.c: Likewise.
OK.
Jeff

Re: Add support for bitwise reductions

[Richard Sandiford]

Richard Sandiford  writes:
> This patch adds support for the SVE bitwise reduction instructions
> (ANDV, ORV and EORV).  It's a fairly mechanical extension of existing
> REDUC_* operators.
>
> Tested on aarch64-linux-gnu (with and without SVE), x86_64-linux-gnu
> and powerpc64le-linux-gnu.

Here's an updated version that applies on top of the recent
removal of REDUC_*_EXPR.  Tested as before.

Thanks,
Richard


2017-11-22  Richard Sandiford  
Alan Hayward  
David Sherwood  

gcc/
* optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab)
(reduc_xor_scal_optab): New optabs.
* doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m})
(reduc_xor_scal_@var{m}): Document.
* doc/sourcebuild.texi (vect_logical_reduc): Likewise.
* internal-fn.def (IFN_REDUC_AND, IFN_REDUC_IOR, IFN_REDUC_XOR): New
internal functions.
* fold-const-call.c (fold_const_call): Handle them.
* tree-vect-loop.c (reduction_fn_for_scalar_code): Return the new
internal functions for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR.
* config/aarch64/aarch64-sve.md (reduc__scal_):
(*reduc__scal_): New patterns.
* config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV)
(UNSPEC_XORV): New unspecs.
(optab): Add entries for them.
(BITWISEV): New int iterator.
(bit_reduc_op): New int attributes.

gcc/testsuite/
* lib/target-supports.exp (check_effective_target_vect_logical_reduc):
New proc.
* gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc
and add an associated scan-dump test.  Prevent vectorization
of the first two loops.
* gcc.dg/vect/vect-reduc-or_2.c: Likewise.
* gcc.target/aarch64/sve_reduc_1.c: Add AND, IOR and XOR reductions.
* gcc.target/aarch64/sve_reduc_2.c: Likewise.
* gcc.target/aarch64/sve_reduc_1_run.c: Likewise.
(INIT_VECTOR): Tweak initial value so that some bits are always set.
* gcc.target/aarch64/sve_reduc_2_run.c: Likewise.

Index: gcc/optabs.def
===
--- gcc/optabs.def  2017-11-22 18:05:58.624329338 +
+++ gcc/optabs.def  2017-11-22 18:06:54.516061226 +
@@ -292,6 +292,9 @@ OPTAB_D (reduc_smin_scal_optab, "reduc_s
 OPTAB_D (reduc_plus_scal_optab, "reduc_plus_scal_$a")
 OPTAB_D (reduc_umax_scal_optab, "reduc_umax_scal_$a")
 OPTAB_D (reduc_umin_scal_optab, "reduc_umin_scal_$a")
+OPTAB_D (reduc_and_scal_optab,  "reduc_and_scal_$a")
+OPTAB_D (reduc_ior_scal_optab,  "reduc_ior_scal_$a")
+OPTAB_D (reduc_xor_scal_optab,  "reduc_xor_scal_$a")
 
 OPTAB_D (sdot_prod_optab, "sdot_prod$I$a")
 OPTAB_D (ssum_widen_optab, "widen_ssum$I$a3")
Index: gcc/doc/md.texi
===
--- gcc/doc/md.texi 2017-11-22 18:05:58.620520950 +
+++ gcc/doc/md.texi 2017-11-22 18:06:54.515109580 +
@@ -5244,6 +5244,17 @@ Compute the sum of the elements of a vec
 operand 0 is the scalar result, with mode equal to the mode of the elements of
 the input vector.
 
+@cindex @code{reduc_and_scal_@var{m}} instruction pattern
+@item @samp{reduc_and_scal_@var{m}}
+@cindex @code{reduc_ior_scal_@var{m}} instruction pattern
+@itemx @samp{reduc_ior_scal_@var{m}}
+@cindex @code{reduc_xor_scal_@var{m}} instruction pattern
+@itemx @samp{reduc_xor_scal_@var{m}}
+Compute the bitwise @code{AND}/@code{IOR}/@code{XOR} reduction of the elements
+of a vector of mode @var{m}.  Operand 1 is the vector input and operand 0
+is the scalar result.  The mode of the scalar result is the same as one
+element of @var{m}.
+
 @cindex @code{sdot_prod@var{m}} instruction pattern
 @item @samp{sdot_prod@var{m}}
 @cindex @code{udot_prod@var{m}} instruction pattern
Index: gcc/doc/sourcebuild.texi
===
--- gcc/doc/sourcebuild.texi2017-11-22 18:05:58.621473047 +
+++ gcc/doc/sourcebuild.texi2017-11-22 18:06:54.515109580 +
@@ -1570,6 +1570,9 @@ Target supports 16- and 8-bytes vectors.
 
 @item vect_sizes_32B_16B
 Target supports 32- and 16-bytes vectors.
+
+@item vect_logical_reduc
+Target supports AND, IOR and XOR reduction on vectors.
 @end table
 
 @subsubsection Thread Local Storage attributes
Index: gcc/internal-fn.def
===
--- gcc/internal-fn.def 2017-11-22 18:05:51.545487816 +
+++ gcc/internal-fn.def 2017-11-22 18:06:54.516061226 +
@@ -137,6 +137,12 @@ DEF_INTERNAL_SIGNED_OPTAB_FN (REDUC_MAX,
  reduc_smax_scal, reduc_umax_scal, unary)
 DEF_INTERNAL_SIGNED_OPTAB_FN (REDUC_MIN, ECF_CONST | ECF_NOTHROW, first,
  reduc_smin_scal, reduc_umin_scal, unary)
+DEF_INTERNAL_OPTAB_FN (REDUC_AND, ECF_CONST | 

Add support for bitwise reductions

[Richard Sandiford]

This patch adds support for the SVE bitwise reduction instructions
(ANDV, ORV and EORV).  It's a fairly mechanical extension of existing
REDUC_* operators.

Tested on aarch64-linux-gnu (with and without SVE), x86_64-linux-gnu
and powerpc64le-linux-gnu.

Richard


2017-11-17  Richard Sandiford  
Alan Hayward  
David Sherwood  

gcc/
* tree.def (REDUC_AND_EXPR, REDUC_IOR_EXPR, REDUC_XOR_EXPR): New
tree codes.
* doc/md.texi (reduc_and_scal_@var{m}, reduc_ior_scal_@var{m})
(reduc_xor_scal_@var{m}): Document.
* doc/sourcebuild.texi (vect_logical_reduc): Likewise.
* doc/generic.texi (REDUC_MAX_EXPR, REDUC_MIN_EXPR, REDUC_PLUS_EXPR)
(REDUC_AND_EXPR, REDUC_IOR_EXPR, REDUC_XOR_EXPR): Likewise.
* optabs.def (reduc_and_scal_optab, reduc_ior_scal_optab)
(reduc_xor_scal_optab): New optabs.
* cfgexpand.c (expand_debug_expr): Handle the new tree codes.
* expr.c (expand_expr_real_2): Likewise.
* fold-const.c (const_unop): Likewise.
* optabs-tree.c (optab_for_tree_code): Likewise.
* tree-cfg.c (verify_gimple_assign_unary): Likewise.
* tree-inline.c (estimate_operator_cost): Likewise.
* tree-pretty-print.c (dump_generic_node): Likewise.  Reuse
generic unary code for REDUC_MAX_EXPR, REDUC_MIN_EXPR and
REDUC_PLUS_EXPR.
* tree-vect-loop.c (reduction_code_for_scalar_code): Return the
new reduction codes for BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR.
* config/aarch64/aarch64-sve.md (reduc__scal_):
(*reduc__scal_): New patterns.
* config/aarch64/iterators.md (UNSPEC_ANDV, UNSPEC_ORV)
(UNSPEC_XORV): New unspecs.
(optab): Add entries for them.
(BITWISEV): New int iterator.
(bit_reduc_op): New int attributes.

gcc/testsuite/
* lib/target-supports.exp (check_effective_target_vect_logical_reduc):
New proc.
* gcc.dg/vect/vect-reduc-or_1.c: Also run for vect_logical_reduc
and add an associated scan-dump test.  Prevent vectorization
of the first two loops.
* gcc.dg/vect/vect-reduc-or_2.c: Likewise.
* gcc.target/aarch64/sve_reduc_1.c: Add AND, IOR and XOR reductions.
* gcc.target/aarch64/sve_reduc_2.c: Likewise.
* gcc.target/aarch64/sve_reduc_1_run.c: Likewise.
(INIT_VECTOR): Tweak initial value so that some bits are always set.
* gcc.target/aarch64/sve_reduc_2_run.c: Likewise.

Index: gcc/tree.def
===
--- gcc/tree.def2017-11-17 09:40:43.533167007 +
+++ gcc/tree.def2017-11-17 09:49:36.196354636 +
@@ -1298,6 +1298,9 @@ DEFTREECODE (TRANSACTION_EXPR, "transact
 DEFTREECODE (REDUC_MAX_EXPR, "reduc_max_expr", tcc_unary, 1)
 DEFTREECODE (REDUC_MIN_EXPR, "reduc_min_expr", tcc_unary, 1)
 DEFTREECODE (REDUC_PLUS_EXPR, "reduc_plus_expr", tcc_unary, 1)
+DEFTREECODE (REDUC_AND_EXPR, "reduc_and_expr", tcc_unary, 1)
+DEFTREECODE (REDUC_IOR_EXPR, "reduc_ior_expr", tcc_unary, 1)
+DEFTREECODE (REDUC_XOR_EXPR, "reduc_xor_expr", tcc_unary, 1)
 
 /* Widening dot-product.
The first two arguments are of type t1.
Index: gcc/doc/md.texi
===
--- gcc/doc/md.texi 2017-11-17 09:44:46.386606597 +
+++ gcc/doc/md.texi 2017-11-17 09:49:36.189354637 +
@@ -5244,6 +5244,17 @@ Compute the sum of the elements of a vec
 operand 0 is the scalar result, with mode equal to the mode of the elements of
 the input vector.
 
+@cindex @code{reduc_and_scal_@var{m}} instruction pattern
+@item @samp{reduc_and_scal_@var{m}}
+@cindex @code{reduc_ior_scal_@var{m}} instruction pattern
+@itemx @samp{reduc_ior_scal_@var{m}}
+@cindex @code{reduc_xor_scal_@var{m}} instruction pattern
+@itemx @samp{reduc_xor_scal_@var{m}}
+Compute the bitwise @code{AND}/@code{IOR}/@code{XOR} reduction of the elements
+of a vector of mode @var{m}.  Operand 1 is the vector input and operand 0
+is the scalar result.  The mode of the scalar result is the same as one
+element of @var{m}.
+
 @cindex @code{sdot_prod@var{m}} instruction pattern
 @item @samp{sdot_prod@var{m}}
 @cindex @code{udot_prod@var{m}} instruction pattern
Index: gcc/doc/sourcebuild.texi
===
--- gcc/doc/sourcebuild.texi2017-11-09 15:19:05.427168565 +
+++ gcc/doc/sourcebuild.texi2017-11-17 09:49:36.190354637 +
@@ -1570,6 +1570,9 @@ Target supports 16- and 8-bytes vectors.
 
 @item vect_sizes_32B_16B
 Target supports 32- and 16-bytes vectors.
+
+@item vect_logical_reduc
+Target supports AND, IOR and XOR reduction on vectors.
 @end table
 
 @subsubsection Thread Local Storage attributes
Index: gcc/doc/generic.texi
===
--- gcc/doc/generic.texi