Re: [PATCH, AArch64] Compare instruction in shift_extend mode
OK. Thank you. /Marcus On 17 April 2013 11:05, Hurugalawadi, Naveen wrote: > Hi, > >>> I suggest for this one test case either making it compile only and >>> dropping main() such that the pattern match only looks in the >>> assembled output of the cmp_* functions > > The testcase will check only for assembly pattern of the instruction > as per your suggestion. > > Please find attached the modified patch let me know if there should > be any further modifications in it. > > Thanks, > Naveen >
RE: [PATCH, AArch64] Compare instruction in shift_extend mode
Hi,
>> I suggest for this one test case either making it compile only and
>> dropping main() such that the pattern match only looks in the
>> assembled output of the cmp_* functions
The testcase will check only for assembly pattern of the instruction
as per your suggestion.
Please find attached the modified patch let me know if there should
be any further modifications in it.
Thanks,
Naveen
--- gcc/config/aarch64/aarch64.md 2013-04-17 11:18:29.453576713 +0530
+++ gcc/config/aarch64/aarch64.md 2013-04-17 15:22:36.161492471 +0530
@@ -2311,6 +2311,18 @@
(set_attr "mode" "")]
)
+(define_insn "*cmp_swp__shft_"
+ [(set (reg:CC_SWP CC_REGNUM)
+ (compare:CC_SWP (ashift:GPI
+ (ANY_EXTEND:GPI
+ (match_operand:ALLX 0 "register_operand" "r"))
+ (match_operand:QI 1 "aarch64_shift_imm_" "n"))
+ (match_operand:GPI 2 "register_operand" "r")))]
+ ""
+ "cmp\\t%2, %0, xt %1"
+ [(set_attr "v8type" "alus_ext")
+ (set_attr "mode" "")]
+)
;; ---
;; Store-flag and conditional select insns
--- gcc/testsuite/gcc.target/aarch64/cmp.c 1970-01-01 05:30:00.0 +0530
+++ gcc/testsuite/gcc.target/aarch64/cmp.c 2013-04-17 15:23:36.121492125 +0530
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+cmp_si_test1 (int a, int b, int c)
+{
+ if (a > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+int
+cmp_si_test2 (int a, int b, int c)
+{
+ if ((a >> 3) > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+typedef long long s64;
+
+s64
+cmp_di_test1 (s64 a, s64 b, s64 c)
+{
+ if (a > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+s64
+cmp_di_test2 (s64 a, s64 b, s64 c)
+{
+ if ((a >> 3) > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+int
+cmp_di_test3 (int a, s64 b, s64 c)
+{
+ if (a > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+int
+cmp_di_test4 (int a, s64 b, s64 c)
+{
+ if (((s64)a << 3) > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+/* { dg-final { scan-assembler-times "cmp\tw\[0-9\]+, w\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 4 } } */
Re: [PATCH, AArch64] Compare instruction in shift_extend mode
On 15/04/13 05:37, Hurugalawadi, Naveen wrote: Hi, Same issue as my previous reply applies here. Thanks for the suggestion. Please find attached the modified patch as per your suggestions. Please review the same and let me know if there should be any further modifications in it. Thanks, Naveen Hi, The .md pattern looks OK. I'm not happy about the test case. It is too fragile. For example, adding -fno-inline such that main does not get optimized away breaks the pattern match. When we run the testsuites here we often do a run with -fPIC in order to increase coverage, that option will also break this test case. I suggest for this one test case either making it compile only and dropping main() such that the pattern match only looks in the assembled output of the cmp_* functions, or leaving the test case execute but removing the pattern match... Cheers /Marcus
RE: [PATCH, AArch64] Compare instruction in shift_extend mode
Hi,
>> Same issue as my previous reply applies here.
Thanks for the suggestion.
Please find attached the modified patch as per your suggestions.
Please review the same and let me know if there should be any
further modifications in it.
Thanks,
Naveen
--- gcc/config/aarch64/aarch64.md 2013-04-15 09:41:29.711014628 +0530
+++ gcc/config/aarch64/aarch64.md 2013-04-15 09:51:08.027015641 +0530
@@ -2205,6 +2205,18 @@
(set_attr "mode" "")]
)
+(define_insn "*cmp_swp__shft_"
+ [(set (reg:CC_SWP CC_REGNUM)
+ (compare:CC_SWP (ashift:GPI
+ (ANY_EXTEND:GPI
+ (match_operand:ALLX 0 "register_operand" "r"))
+ (match_operand:QI 1 "aarch64_shift_imm_" "n"))
+ (match_operand:GPI 2 "register_operand" "r")))]
+ ""
+ "cmp\\t%2, %0, xt %1"
+ [(set_attr "v8type" "alus_ext")
+ (set_attr "mode" "")]
+)
;; ---
;; Store-flag and conditional select insns
--- gcc/testsuite/gcc.target/aarch64/cmp.c 1970-01-01 05:30:00.0 +0530
+++ gcc/testsuite/gcc.target/aarch64/cmp.c 2013-04-15 09:54:29.471015995 +0530
@@ -0,0 +1,135 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+int
+cmp_si_test1 (int a, int b, int c)
+{
+ if (a > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+int
+cmp_si_test2 (int a, int b, int c)
+{
+ if ((a >> 3) > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+typedef long long s64;
+
+s64
+cmp_di_test1 (s64 a, s64 b, s64 c)
+{
+ if (a > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+s64
+cmp_di_test2 (s64 a, s64 b, s64 c)
+{
+ if ((a >> 3) > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+int
+cmp_di_test3 (int a, s64 b, s64 c)
+{
+ if (a > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+int
+cmp_di_test4 (int a, s64 b, s64 c)
+{
+ if (((s64)a << 3) > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+int main ()
+{
+ int x;
+ s64 y;
+
+ x = cmp_si_test1 (2, 12, 5);
+ if (x != 19)
+abort ();
+
+ x = cmp_si_test1 (1, 2, 32);
+ if (x != 35)
+abort ();
+
+ x = cmp_si_test2 (7, 5, 15);
+ if (x != 27)
+abort ();
+
+ x = cmp_si_test2 (12, 1, 3);
+ if (x != 16)
+abort ();
+
+ y = cmp_di_test1 (0x20202020ll,
+ 0x65161611ll,
+ 0x42434243ll);
+ if (y != 0xc7797874ll)
+abort ();
+
+ y = cmp_di_test1 (0x1010101010101ll,
+ 0x123456789abcdll,
+ 0x5ll);
+ if (y != 0x7799bbde00223ll)
+abort ();
+
+ y = cmp_di_test2 (0x31313131ll,
+ 0x35466561ll,
+ 0x42434243ll);
+ if (y != 0xa8bad8d5ll)
+abort ();
+
+ y = cmp_di_test2 (0x101010101ll,
+ 0x123456789ll,
+ 0x5ll);
+ if (y != 0x7799bbddfll)
+abort ();
+
+ x = cmp_di_test3 (6252,
+0x64234978ll,
+0x12345123ll);
+ if (x != 1985458951)
+abort ();
+
+ x = cmp_di_test3 (7635,
+0x10101010ll,
+0x21212121ll);
+ if (x != 825315076)
+abort ();
+
+ x = cmp_di_test4 (202,
+0x984210421ll,
+0x18181818181ll);
+ if (x != 94537324)
+abort ();
+
+ x = cmp_di_test4 (167,
+0x987987987987ll,
+0x12312312ll);
+ if (x != -1714840256)
+abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "cmp\tw\[0-9\]+, w\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 4 } } */
Re: [PATCH, AArch64] Compare instruction in shift_extend mode
On 12/04/13 12:44, Hurugalawadi, Naveen wrote:
Hi,
Please find attached the patch that implements compare instruction in
shift_extend mode for aarch64 target.
Testcase has been added for compare instructions.
Please review the same and let me know if there should be any
modifications in the patch.
Build and tested on aarch64-thunder-elf (using Cavium's internal
simulator). No new regressions.
Thanks,
Naveen
gcc/
2013-04-12 Naveen H.S
* config/aarch64/aarch64.md
(*cmp_swp__shft_): New pattern.
gcc/testsuite/
2013-04-12 Naveen H.S
* gcc.target/aarch64/cmp.c: New.
--- gcc/testsuite/gcc.target/aarch64/cmp.c 1970-01-01 05:30:00.0
+0530
+++ gcc/testsuite/gcc.target/aarch64/cmp.c 2013-04-12 16:36:57.232943520
+0530
@@ -0,0 +1,138 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+int
+cmp_si_test1 (int a, int b, int c)
+{
+ /* { dg-final { scan-assembler "cmp\tw\[0-9\]+, w\[0-9\]+" } } */
+ if (a > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+int
+cmp_si_test2 (int a, int b, int c)
+{
+ /* { dg-final { scan-assembler "cmp\tw\[0-9\]+, w\[0-9\]+, asr 3" } } */
+ if ((a >> 3) > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+typedef long long s64;
+
+s64
+cmp_di_test1 (s64 a, s64 b, s64 c)
+{
+ /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+" } } */
+ if (a > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+s64
+cmp_di_test2 (s64 a, s64 b, s64 c)
+{
+ /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+, asr 3" } } */
+ if ((a >> 3) > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+int
+cmp_di_test3 (int a, s64 b, s64 c)
+{
+ /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+, sxtw" } } */
+ if (a > b)
+return a + c;
+ else
+return a + b + c;
+}
+
+int
+cmp_di_test4 (int a, s64 b, s64 c)
+{
+ /* { dg-final { scan-assembler "cmp\tx\[0-9\]+, x\[0-9\]+, sxtw 3" } } */
+ if (((s64)a << 3) > b)
+return a + c;
+ else
+return a + b + c;
+}
+
Same issue as my previous reply applies here.
R.
