Re: [PATCH][AArch64] Improve spill code - swap order in shl pattern
On Mon, Jul 27, 2015 at 03:38:40PM +0100, Wilco Dijkstra wrote: > ping > > Various instructions are supported as integer operations as well as SIMD on > > AArch64. When > > register pressure is high, lra-constraints inserts spill code without > > taking the allocation > > class into account, and basically chooses the first available pattern that > > matches. Since this > > instruction has the SIMD version first it is usually chosen eventhough some > > of the operands > > are eventually allocated to integer registers. The result is inefficient > > code not only due to > > the higher latency of SIMD instructions but also due to the extra int<->FP > > moves. Placing the > > integer variant first in the shl pattern generates far more optimal spill > > code. A few more > > patterns are the wrong way around, which I'll address in a separate patch. > > I'm also looking > > into fixing lra-constraints to generate the expected code by taking the > > allocno class into > > account in the cost calculations during spilling. > > > > 2015-04-27 Wilco Dijkstra > > > > * gcc/config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_3): > > Place integer variant first. I approved this in April ( https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01652.html ). I've committed it on your behalf as revision 226247. Thanks, James > > -Original Message- > > From: Wilco Dijkstra [mailto:wdijk...@arm.com] > > Sent: 27 April 2015 14:37 > > To: GCC Patches > > Subject: [PATCH][AArch64] Improve spill code - swap order in shl pattern > > > > --- > > gcc/config/aarch64/aarch64.md | 14 +++--- > > 1 file changed, 7 insertions(+), 7 deletions(-) > > > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > > index 7163025..baef56a 100644 > > --- a/gcc/config/aarch64/aarch64.md > > +++ b/gcc/config/aarch64/aarch64.md > > @@ -3334,17 +3334,17 @@ > > > > ;; Logical left shift using SISD or Integer instruction > > (define_insn "*aarch64_ashl_sisd_or_int_3" > > - [(set (match_operand:GPI 0 "register_operand" "=w,w,r") > > + [(set (match_operand:GPI 0 "register_operand" "=r,w,w") > > (ashift:GPI > > - (match_operand:GPI 1 "register_operand" "w,w,r") > > - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" > > "Us,w,rUs")))] > > + (match_operand:GPI 1 "register_operand" "r,w,w") > > + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" > > "rUs,Us,w")))] > >"" > >"@ > > + lsl\t%0, %1, %2 > > shl\t%0, %1, %2 > > - ushl\t%0, %1, %2 > > - lsl\t%0, %1, %2" > > - [(set_attr "simd" "yes,yes,no") > > - (set_attr "type" "neon_shift_imm, neon_shift_reg,shift_reg")] > > + ushl\t%0, %1, %2" > > + [(set_attr "simd" "no,yes,yes") > > + (set_attr "type" "shift_reg,neon_shift_imm, neon_shift_reg")] > > ) > > > > ;; Logical right shift using SISD or Integer instruction > > -- > > 1.9.1 > >
RE: [PATCH][AArch64] Improve spill code - swap order in shl pattern
ping > -Original Message- > From: Wilco Dijkstra [mailto:wdijk...@arm.com] > Sent: 27 April 2015 14:37 > To: GCC Patches > Subject: [PATCH][AArch64] Improve spill code - swap order in shl pattern > > Various instructions are supported as integer operations as well as SIMD on > AArch64. When > register pressure is high, lra-constraints inserts spill code without taking > the allocation > class into account, and basically chooses the first available pattern that > matches. Since this > instruction has the SIMD version first it is usually chosen eventhough some > of the operands > are eventually allocated to integer registers. The result is inefficient code > not only due to > the higher latency of SIMD instructions but also due to the extra int<->FP > moves. Placing the > integer variant first in the shl pattern generates far more optimal spill > code. A few more > patterns are the wrong way around, which I'll address in a separate patch. > I'm also looking > into fixing lra-constraints to generate the expected code by taking the > allocno class into > account in the cost calculations during spilling. > > 2015-04-27 Wilco Dijkstra > > * gcc/config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_3): > Place integer variant first. > > --- > gcc/config/aarch64/aarch64.md | 14 +++--- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 7163025..baef56a 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -3334,17 +3334,17 @@ > > ;; Logical left shift using SISD or Integer instruction > (define_insn "*aarch64_ashl_sisd_or_int_3" > - [(set (match_operand:GPI 0 "register_operand" "=w,w,r") > + [(set (match_operand:GPI 0 "register_operand" "=r,w,w") > (ashift:GPI > - (match_operand:GPI 1 "register_operand" "w,w,r") > - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" > "Us,w,rUs")))] > + (match_operand:GPI 1 "register_operand" "r,w,w") > + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" > "rUs,Us,w")))] >"" >"@ > + lsl\t%0, %1, %2 > shl\t%0, %1, %2 > - ushl\t%0, %1, %2 > - lsl\t%0, %1, %2" > - [(set_attr "simd" "yes,yes,no") > - (set_attr "type" "neon_shift_imm, neon_shift_reg,shift_reg")] > + ushl\t%0, %1, %2" > + [(set_attr "simd" "no,yes,yes") > + (set_attr "type" "shift_reg,neon_shift_imm, neon_shift_reg")] > ) > > ;; Logical right shift using SISD or Integer instruction > -- > 1.9.1
Re: [PATCH][AArch64] Improve spill code - swap order in shl pattern
On Mon, Apr 27, 2015 at 02:37:12PM +0100, Wilco Dijkstra wrote: > Various instructions are supported as integer operations as well as SIMD on > AArch64. When register pressure is high, lra-constraints inserts spill code > without taking the allocation class into account, and basically chooses the > first available pattern that matches. Since this instruction has the SIMD > version first it is usually chosen eventhough some of the operands are > eventually allocated to integer registers. The result is inefficient code not > only due to the higher latency of SIMD instructions but also due to the extra > int<->FP moves. Placing the integer variant first in the shl pattern > generates far more optimal spill code. A few more patterns are the wrong way > around, which I'll address in a separate patch. I'm also looking into fixing > lra-constraints to generate the expected code by taking the allocno class > into account in the cost calculations during spilling. > > 2015-04-27 Wilco Dijkstra > > * gcc/config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_3): > Place integer variant first. OK, thanks for the fix. Cheers, James
