RE: [PATCH 4/6] Support Intel AVX-NE-CONVERT

2022-10-30 Thread Liu, Hongtao via Gcc-patches 


> -Original Message-
> From: Kong, Lingling 
> Sent: Friday, October 28, 2022 4:57 PM
> To: Hongtao Liu 
> Cc: Liu, Hongtao ; gcc-patches@gcc.gnu.org; Jiang,
> Haochen 
> Subject: RE: [PATCH 4/6] Support Intel AVX-NE-CONVERT
> 
> Hi,
> 
> Because we  switch intrinsics for avx512bf16 to the new type __bf16. Now we
> could use m128/256bh for vector bf16 type instead of m128/256bf16.
> And unified builtin for avx512bf16/avxneconvert.
Ok.
> 
> Thanks,
> Lingling
> 
> > -Original Message-
> > From: Hongtao Liu 
> > Sent: Tuesday, October 25, 2022 1:23 PM
> > To: Kong, Lingling 
> > Cc: Liu, Hongtao ; gcc-patches@gcc.gnu.org;
> > Jiang, Haochen 
> > Subject: Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT
> >
> > On Mon, Oct 24, 2022 at 2:20 PM Kong, Lingling
> > 
> > wrote:
> > >
> > > > From: Gcc-patches
> > > > 
> > > > On Behalf Of Hongtao Liu via Gcc-patches
> > > > Sent: Monday, October 17, 2022 1:47 PM
> > > > To: Jiang, Haochen 
> > > > Cc: Liu, Hongtao ; gcc-patches@gcc.gnu.org
> > > > Subject: Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT
> > > >
> > > > On Fri, Oct 14, 2022 at 3:58 PM Haochen Jiang via Gcc-patches
> > > >  wrote:
> > > > >
> > > > > From: Kong Lingling 
> > > > > +(define_insn "vbcstne2ps_"
> > > > > +  [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
> > > > > +(vec_duplicate:VF1_128_256
> > > > > + (unspec:SF
> > > > > +  [(match_operand:HI 1 "memory_operand" "m")]
> > > > > +  VBCSTNE)))]
> > > > > +  "TARGET_AVXNECONVERT"
> > > > > +  "vbcstne2ps\t{%1, %0|%0, %1}"
> > > > > +  [(set_attr "prefix" "vex")
> > > > > +  (set_attr "mode" "")])
> > > > Since jakub has support bf16 software emulation, can we rewrite it
> > > > with general rtl ir without unspec?
> > > > Like (float_extend:SF (match_operand:BF "memory_operand" "m")
> > > > > +
> > > > > +(define_int_iterator VCVTNEBF16
> > > > > +  [UNSPEC_VCVTNEEBF16SF
> > > > > +   UNSPEC_VCVTNEOBF16SF])
> > > > > +
> > > > > +(define_int_attr vcvtnebf16type
> > > > > +  [(UNSPEC_VCVTNEEBF16SF "ebf16")
> > > > > +   (UNSPEC_VCVTNEOBF16SF "obf16")]) (define_insn
> > > > > +"vcvtne2ps_"
> > > > > +  [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
> > > > > +(unspec:VF1_128_256
> > > > > +  [(match_operand: 1 "memory_operand" "m")]
> > > > > + VCVTNEBF16))]
> > > > > +  "TARGET_AVXNECONVERT"
> > > > > +  "vcvtne2ps\t{%1, %0|%0, %1}"
> > > > > +  [(set_attr "prefix" "vex")
> > > > > +   (set_attr "mode" "")])
> > > > Similar for this one and all those patterns below.
> > >
> > > That's great! Thanks for the review!
> > > Now rewrite it without unspec and use float_extend for new define_insn.
> > Ok.
> > >
> > > Thanks
> > > Lingling
> > >
> > >
> >
> >
> > --
> > BR,
> > Hongtao

RE: [PATCH 4/6] Support Intel AVX-NE-CONVERT

2022-10-28 Thread Kong, Lingling via Gcc-patches 
Hi,

Because we  switch intrinsics for avx512bf16 to the new type __bf16. Now we 
could use m128/256bh for vector bf16 type instead of m128/256bf16.
And unified builtin for avx512bf16/avxneconvert.

Thanks,
Lingling

> -Original Message-
> From: Hongtao Liu 
> Sent: Tuesday, October 25, 2022 1:23 PM
> To: Kong, Lingling 
> Cc: Liu, Hongtao ; gcc-patches@gcc.gnu.org; Jiang,
> Haochen 
> Subject: Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT
> 
> On Mon, Oct 24, 2022 at 2:20 PM Kong, Lingling 
> wrote:
> >
> > > From: Gcc-patches
> > > 
> > > On Behalf Of Hongtao Liu via Gcc-patches
> > > Sent: Monday, October 17, 2022 1:47 PM
> > > To: Jiang, Haochen 
> > > Cc: Liu, Hongtao ; gcc-patches@gcc.gnu.org
> > > Subject: Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT
> > >
> > > On Fri, Oct 14, 2022 at 3:58 PM Haochen Jiang via Gcc-patches
> > >  wrote:
> > > >
> > > > From: Kong Lingling 
> > > > +(define_insn "vbcstne2ps_"
> > > > +  [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
> > > > +(vec_duplicate:VF1_128_256
> > > > + (unspec:SF
> > > > +  [(match_operand:HI 1 "memory_operand" "m")]
> > > > +  VBCSTNE)))]
> > > > +  "TARGET_AVXNECONVERT"
> > > > +  "vbcstne2ps\t{%1, %0|%0, %1}"
> > > > +  [(set_attr "prefix" "vex")
> > > > +  (set_attr "mode" "")])
> > > Since jakub has support bf16 software emulation, can we rewrite it
> > > with general rtl ir without unspec?
> > > Like (float_extend:SF (match_operand:BF "memory_operand" "m")
> > > > +
> > > > +(define_int_iterator VCVTNEBF16
> > > > +  [UNSPEC_VCVTNEEBF16SF
> > > > +   UNSPEC_VCVTNEOBF16SF])
> > > > +
> > > > +(define_int_attr vcvtnebf16type
> > > > +  [(UNSPEC_VCVTNEEBF16SF "ebf16")
> > > > +   (UNSPEC_VCVTNEOBF16SF "obf16")]) (define_insn
> > > > +"vcvtne2ps_"
> > > > +  [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
> > > > +(unspec:VF1_128_256
> > > > +  [(match_operand: 1 "memory_operand" "m")]
> > > > + VCVTNEBF16))]
> > > > +  "TARGET_AVXNECONVERT"
> > > > +  "vcvtne2ps\t{%1, %0|%0, %1}"
> > > > +  [(set_attr "prefix" "vex")
> > > > +   (set_attr "mode" "")])
> > > Similar for this one and all those patterns below.
> >
> > That's great! Thanks for the review!
> > Now rewrite it without unspec and use float_extend for new define_insn.
> Ok.
> >
> > Thanks
> > Lingling
> >
> >
> 
> 
> --
> BR,
> Hongtao


0001-Support-Intel-AVX-NE-CONVERT.patch
Description: 0001-Support-Intel-AVX-NE-CONVERT.patch

Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT

2022-10-24 Thread Hongtao Liu via Gcc-patches 
On Mon, Oct 24, 2022 at 2:20 PM Kong, Lingling  wrote:
>
> > From: Gcc-patches 
> > On Behalf Of Hongtao Liu via Gcc-patches
> > Sent: Monday, October 17, 2022 1:47 PM
> > To: Jiang, Haochen 
> > Cc: Liu, Hongtao ; gcc-patches@gcc.gnu.org
> > Subject: Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT
> >
> > On Fri, Oct 14, 2022 at 3:58 PM Haochen Jiang via Gcc-patches
> >  wrote:
> > >
> > > From: Kong Lingling 
> > > +(define_insn "vbcstne2ps_"
> > > +  [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
> > > +(vec_duplicate:VF1_128_256
> > > + (unspec:SF
> > > +  [(match_operand:HI 1 "memory_operand" "m")]
> > > +  VBCSTNE)))]
> > > +  "TARGET_AVXNECONVERT"
> > > +  "vbcstne2ps\t{%1, %0|%0, %1}"
> > > +  [(set_attr "prefix" "vex")
> > > +  (set_attr "mode" "")])
> > Since jakub has support bf16 software emulation, can we rewrite it
> > with general rtl ir without unspec?
> > Like (float_extend:SF (match_operand:BF "memory_operand" "m")
> > > +
> > > +(define_int_iterator VCVTNEBF16
> > > +  [UNSPEC_VCVTNEEBF16SF
> > > +   UNSPEC_VCVTNEOBF16SF])
> > > +
> > > +(define_int_attr vcvtnebf16type
> > > +  [(UNSPEC_VCVTNEEBF16SF "ebf16")
> > > +   (UNSPEC_VCVTNEOBF16SF "obf16")])
> > > +(define_insn "vcvtne2ps_"
> > > +  [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
> > > +(unspec:VF1_128_256
> > > +  [(match_operand: 1 "memory_operand" "m")]
> > > + VCVTNEBF16))]
> > > +  "TARGET_AVXNECONVERT"
> > > +  "vcvtne2ps\t{%1, %0|%0, %1}"
> > > +  [(set_attr "prefix" "vex")
> > > +   (set_attr "mode" "")])
> > Similar for this one and all those patterns below.
>
> That's great! Thanks for the review!
> Now rewrite it without unspec and use float_extend for new define_insn.
Ok.
>
> Thanks
> Lingling
>
>


-- 
BR,
Hongtao

RE: [PATCH 4/6] Support Intel AVX-NE-CONVERT

2022-10-23 Thread Kong, Lingling via Gcc-patches 
> From: Gcc-patches 
> On Behalf Of Hongtao Liu via Gcc-patches
> Sent: Monday, October 17, 2022 1:47 PM
> To: Jiang, Haochen 
> Cc: Liu, Hongtao ; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT
>
> On Fri, Oct 14, 2022 at 3:58 PM Haochen Jiang via Gcc-patches
>  wrote:
> >
> > From: Kong Lingling 
> > +(define_insn "vbcstne2ps_"
> > +  [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
> > +(vec_duplicate:VF1_128_256
> > + (unspec:SF
> > +  [(match_operand:HI 1 "memory_operand" "m")]
> > +  VBCSTNE)))]
> > +  "TARGET_AVXNECONVERT"
> > +  "vbcstne2ps\t{%1, %0|%0, %1}"
> > +  [(set_attr "prefix" "vex")
> > +  (set_attr "mode" "")])
> Since jakub has support bf16 software emulation, can we rewrite it
> with general rtl ir without unspec?
> Like (float_extend:SF (match_operand:BF "memory_operand" "m")
> > +
> > +(define_int_iterator VCVTNEBF16
> > +  [UNSPEC_VCVTNEEBF16SF
> > +   UNSPEC_VCVTNEOBF16SF])
> > +
> > +(define_int_attr vcvtnebf16type
> > +  [(UNSPEC_VCVTNEEBF16SF "ebf16")
> > +   (UNSPEC_VCVTNEOBF16SF "obf16")])
> > +(define_insn "vcvtne2ps_"
> > +  [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
> > +(unspec:VF1_128_256
> > +  [(match_operand: 1 "memory_operand" "m")]
> > + VCVTNEBF16))]
> > +  "TARGET_AVXNECONVERT"
> > +  "vcvtne2ps\t{%1, %0|%0, %1}"
> > +  [(set_attr "prefix" "vex")
> > +   (set_attr "mode" "")])
> Similar for this one and all those patterns below.

That's great! Thanks for the review! 
Now rewrite it without unspec and use float_extend for new define_insn.

Thanks
Lingling




0001-Support-Intel-AVX-NE-CONVERT.patch
Description: 0001-Support-Intel-AVX-NE-CONVERT.patch

Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT

2022-10-16 Thread Hongtao Liu via Gcc-patches 
On Fri, Oct 14, 2022 at 3:58 PM Haochen Jiang via Gcc-patches
 wrote:
>
> From: Kong Lingling 
>
> gcc/ChangeLog:
>
> * common/config/i386/i386-common.cc
> (OPTION_MASK_ISA2_AVXNECONVERT_SET,
> OPTION_MASK_ISA2_AVXNECONVERT_UNSET): New.
> (ix86_handle_option): Handle -mavxneconvert, unset
> avxneconvert when avx2 is disabled.
> * common/config/i386/i386-cpuinfo.h (processor_types): Add
> FEATURE_AVXNECONVERT.
> * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
> avxneconvert.
> * common/config/i386/cpuinfo.h (get_available_features):
> Detect avxneconvert.
> * config.gcc: Add avxneconvertintrin.h
> * config/i386/avxneconvertintrin.h: New.
> * config/i386/cpuid.h (bit_AVXNECONVERT): New.
> * config/i386/i386-builtin-types.def: Add
> DEF_POINTER_TYPE (PCV8HF, V8HF, CONST),
> DEF_POINTER_TYPE (PCV16HF, V16HF, CONST),
> DEF_FUNCTION_TYPE (V4SF, PCSHORT),
> DEF_FUNCTION_TYPE (V8SF, PCSHORT),
> DEF_FUNCTION_TYPE (V4SF, PCV8BF),
> DEF_FUNCTION_TYPE (V4SF, PCV8BF),
> DEF_FUNCTION_TYPE (V8SF, PCV16HF),
> DEF_FUNCTION_TYPE (V8SF, PCV16BF).
> * config/i386/i386-builtin.def: Add new builtins.
> * config/i386/i386-c.cc (ix86_target_macros_internal): Define
> __AVXNECONVERT__.
> * config/i386/i386-expand.cc (ix86_expand_special_args_builtin):
> Handle V4SF_FTYPE_PCSHORT,V8SF_FTYPE_PCSHORT,V4SF_FTYPE_PCV8BF,
> V4SF_FTYPE_PCV8HF,V8SF_FTYPE_PCV16BF,V8SF_FTYPE_PCV16HF.
> * config/i386/i386-isa.def : Add DEF_PTA(AVXNECONVERT) New.
> * config/i386/i386-options.cc (isa2_opts): Add -mavxneconvert.
> (ix86_valid_target_attribute_inner_p): Handle avxneconvert.
> * config/i386/i386.opt: Add option -mavxneconvert.
> * config/i386/immintrin.h: Inculde avxneconvertintrin.h.
> * config/i386/sse.md: (avx_vbcstne2ps_),
> (avx_vcvtne2ps_),
> (avx_vcvtne2ps_),
> (avx_vcvtneps2bf16_): New define_insn
> (avx512f_cvtneps2bf16_):Ditto.
> (avx512f_cvtneps2bf16__mask):Ditto.
> * doc/invoke.texi: Document -mavxneconvert.
> * doc/extend.texi: Document avxneconvert.
> * doc/sourcebuild.texi: Document target avxneconvert.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/avx-check.h: Add avxneconvert check.
> * gcc.target/i386/funcspec-56.inc: Add new target attribute.
> * gcc.target/i386/sse-12.c: Add -mavxneconvert.
> * gcc.target/i386/sse-13.c: Ditto.
> * gcc.target/i386/sse-14.c: Ditto.
> * gcc.target/i386/sse-22.c: Ditto.
> * gcc.target/i386/sse-23.c: Ditto.
> * g++.dg/other/i386-2.C: Ditto.
> * g++.dg/other/i386-3.C: Ditto.
> * lib/target-supports.exp:add check_effective_target_avxneconvert.
> * gcc.target/i386/avx-ne-convert-1.c: New test.
> * gcc.target/i386/avx-ne-convert-vbcstnebf162ps-2.c: Ditto.
> * gcc.target/i386/avx-ne-convert-vbcstnesh2ps-2.c: Ditto.
> * gcc.target/i386/avx-ne-convert-vcvtneebf162ps-2.c: Ditto.
> * gcc.target/i386/avx-ne-convert-vcvtneeph2ps-2.c: Ditto.
> * gcc.target/i386/avx-ne-convert-vcvtneobf162ps-2.c: Ditto.
> * gcc.target/i386/avx-ne-convert-vcvtneoph2ps-2.c: Ditto.
> * gcc.target/i386/avx-ne-convert-vcvtneps2bf16-2.c: Ditto.
> * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1.c: Rename..
> * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1a.c: To this.
> * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1b.c: New test.
> ---
>  gcc/common/config/i386/cpuinfo.h  |   2 +
>  gcc/common/config/i386/i386-common.cc |  21 ++-
>  gcc/common/config/i386/i386-cpuinfo.h |   1 +
>  gcc/common/config/i386/i386-isas.h|   2 +
>  gcc/config.gcc|   2 +-
>  gcc/config/i386/avxneconvertintrin.h  | 140 ++
>  gcc/config/i386/cpuid.h   |   1 +
>  gcc/config/i386/i386-builtin-types.def|  17 +++
>  gcc/config/i386/i386-builtin.def  |  18 +++
>  gcc/config/i386/i386-c.cc |   2 +
>  gcc/config/i386/i386-expand.cc|   8 +
>  gcc/config/i386/i386-isa.def  |   1 +
>  gcc/config/i386/i386-options.cc   |   4 +-
>  gcc/config/i386/i386.opt  |   5 +
>  gcc/config/i386/immintrin.h   |   4 +
>  gcc/config/i386/sse.md| 100 -
>  gcc/doc/extend.texi   |   5 +
>  gcc/doc/invoke.texi   |   9 +-
>  gcc/doc/sourcebuild.texi  |   3 +
>  gcc/testsuite/g++.dg/other/i386-2.C   |   2 +-
>  gcc/testsuite/g++.dg/other/i386-3.C   |   2 +-
>  gcc/testsuite/gcc.target/i386/avx-check.h |   3 +
>  .../gcc