RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
Thank you for information. Updated the v3 version as below.
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616154.html
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, April 19, 2023 4:52 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com;
richard.sandif...@arm.com; Wang, Yanzhang
Subject: RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
On Wed, 19 Apr 2023, Li, Pan2 wrote:
> Hi Richard,
>
> Do you have any idea about this? I leverage git gcc-commit-mklog, it
> will generate something as below. It looks no text after colon. I am
> not sure if I need to add something by myself.
Well, you need to add a description of your change!
> gcc/ChangeLog:
>
> * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
> <=== no text here.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/mask_insn_shortcut.c:
><=== no text here.
> * gcc.target/riscv/simplify_ior_optimization.c: New test.
>
> # Please enter the commit message for your changes. Lines starting #
> with '#' will be ignored, and an empty message aborts the commit.
> #
> # On branch master
> # Your branch is up to date with 'origin/master'.
> #
> # Changes to be committed:
> #...modified: gcc/simplify-rtx.cc
> #...modified:
> gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> #...new file: gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
>
> Pan
>
> -Original Message-
> From: Li, Pan2
> Sent: Wednesday, April 19, 2023 2:47 PM
> To: Richard Biener
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai;
> kito.ch...@sifive.com; richard.sandif...@arm.com; Wang, Yanzhang
>
> Subject: RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1)
> optimization
>
> Oh, I see. The message need to be re-generated. Thank you for pointing out,
> will update ASPA.
>
> Pan
>
> -Original Message-
> From: Richard Biener
> Sent: Wednesday, April 19, 2023 2:40 PM
> To: Li, Pan2
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai;
> kito.ch...@sifive.com; richard.sandif...@arm.com; Wang, Yanzhang
>
> Subject: Re: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1)
> optimization
>
> On Tue, 18 Apr 2023, pan2...@intel.com wrote:
>
> > From: Pan Li
> >
> > This patch add the optimization for the vector IOR(V1, NOT V1).
> > Assume we have below sample code.
> >
> > vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t
> > vl) {
> > return __riscv_vmorn_mm_b32(v1, v1, vl); }
> >
> > Before this patch:
> > vsetvli a5,zero,e8,mf4,ta,ma
> > vlm.vv24,0(a1)
> > vsetvli zero,a2,e8,mf4,ta,ma
> > vmorn.mm v24,v24,v24
> > vsetvli a5,zero,e8,mf4,ta,ma
> > vsm.vv24,0(a0)
> > ret
> >
> > After this patch:
> > vsetvli zero,a2,e8,mf4,ta,ma
> > vmset.m v24
> > vsetvli a5,zero,e8,mf4,ta,ma
> > vsm.v v24,0(a0)
> > ret
> >
> > Or in RTL's perspective,
> > from:
> > (ior:VNx2BI (reg/v:VNx2BI 137 [ v1 ]) (not:VNx2BI (reg/v:VNx2BI 137
> > [
> > v1 ])))
> > to:
> > (const_vector:VNx2BI repeat [ (const_int 1 [0x1]) ])
> >
> > The similar optimization like VMANDN has enabled already. There
> > should be no difference execpt the operator when compare the VMORN
> > and VMANDN for such kind of optimization. The patch allows the
> > VECTOR_BOOL IOR(V1, NOT V1) simplification besides the existing SCALAR_INT
> > mode.
> >
> > gcc/ChangeLog:
> >
> > * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
>
> This needs some text
>
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/base/mask_insn_shortcut.c:
>
> Likewise.
>
> OK with that fixed.
>
> > * gcc.target/riscv/simplify_ior_optimization.c: New test.
> >
> > Signed-off-by: Pan Li
> > ---
> > gcc/simplify-rtx.cc | 4 +-
> > .../riscv/rvv/base/mask_insn_shortcut.c | 3 +-
> > .../riscv/simplify_ior_optimization.c | 50 +++
> > 3 files changed, 53 insertions(+), 4 deletions(-) create mode
> > 100644 gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
> >
> > diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index
> > ee75079917f..3bc9b2f55ea 100644
> > --- a/gcc/simplify-rtx.cc
> > +++ b/gcc/simplify-rtx.cc
> > @@ -3332,8 +3332,8 @@ simplify_context::simplify_binary_operation_1
> > (rtx_code code,
RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
On Wed, 19 Apr 2023, Li, Pan2 wrote:
> Hi Richard,
>
> Do you have any idea about this? I leverage git gcc-commit-mklog, it
> will generate something as below. It looks no text after colon. I am not
> sure if I need to add something by myself.
Well, you need to add a description of your change!
> gcc/ChangeLog:
>
> * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
> <=== no text here.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/mask_insn_shortcut.c:
><=== no text here.
> * gcc.target/riscv/simplify_ior_optimization.c: New test.
>
> # Please enter the commit message for your changes. Lines starting
> # with '#' will be ignored, and an empty message aborts the commit.
> #
> # On branch master
> # Your branch is up to date with 'origin/master'.
> #
> # Changes to be committed:
> #...modified: gcc/simplify-rtx.cc
> #...modified:
> gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> #...new file: gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
>
> Pan
>
> -Original Message-
> From: Li, Pan2
> Sent: Wednesday, April 19, 2023 2:47 PM
> To: Richard Biener
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com;
> richard.sandif...@arm.com; Wang, Yanzhang
> Subject: RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
>
> Oh, I see. The message need to be re-generated. Thank you for pointing out,
> will update ASPA.
>
> Pan
>
> -Original Message-
> From: Richard Biener
> Sent: Wednesday, April 19, 2023 2:40 PM
> To: Li, Pan2
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com;
> richard.sandif...@arm.com; Wang, Yanzhang
> Subject: Re: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
>
> On Tue, 18 Apr 2023, pan2...@intel.com wrote:
>
> > From: Pan Li
> >
> > This patch add the optimization for the vector IOR(V1, NOT V1). Assume
> > we have below sample code.
> >
> > vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t
> > vl) {
> > return __riscv_vmorn_mm_b32(v1, v1, vl); }
> >
> > Before this patch:
> > vsetvli a5,zero,e8,mf4,ta,ma
> > vlm.vv24,0(a1)
> > vsetvli zero,a2,e8,mf4,ta,ma
> > vmorn.mm v24,v24,v24
> > vsetvli a5,zero,e8,mf4,ta,ma
> > vsm.vv24,0(a0)
> > ret
> >
> > After this patch:
> > vsetvli zero,a2,e8,mf4,ta,ma
> > vmset.m v24
> > vsetvli a5,zero,e8,mf4,ta,ma
> > vsm.v v24,0(a0)
> > ret
> >
> > Or in RTL's perspective,
> > from:
> > (ior:VNx2BI (reg/v:VNx2BI 137 [ v1 ]) (not:VNx2BI (reg/v:VNx2BI 137 [
> > v1 ])))
> > to:
> > (const_vector:VNx2BI repeat [ (const_int 1 [0x1]) ])
> >
> > The similar optimization like VMANDN has enabled already. There should
> > be no difference execpt the operator when compare the VMORN and VMANDN
> > for such kind of optimization. The patch allows the VECTOR_BOOL
> > IOR(V1, NOT V1) simplification besides the existing SCALAR_INT mode.
> >
> > gcc/ChangeLog:
> >
> > * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
>
> This needs some text
>
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/base/mask_insn_shortcut.c:
>
> Likewise.
>
> OK with that fixed.
>
> > * gcc.target/riscv/simplify_ior_optimization.c: New test.
> >
> > Signed-off-by: Pan Li
> > ---
> > gcc/simplify-rtx.cc | 4 +-
> > .../riscv/rvv/base/mask_insn_shortcut.c | 3 +-
> > .../riscv/simplify_ior_optimization.c | 50 +++
> > 3 files changed, 53 insertions(+), 4 deletions(-) create mode 100644
> > gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
> >
> > diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index
> > ee75079917f..3bc9b2f55ea 100644
> > --- a/gcc/simplify-rtx.cc
> > +++ b/gcc/simplify-rtx.cc
> > @@ -3332,8 +3332,8 @@ simplify_context::simplify_binary_operation_1
> > (rtx_code code,
> >if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1))
> >|| (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0)))
> > && ! side_effects_p (op0)
> > - && SCALAR_INT_MODE_P (mode))
> > - return constm1_rtx;
> > + && GET_MODE_CLASS (mode) != MODE_CC)
> > + return CONSTM1_RTX (mode);
> >
> >/* (ior A C) is C if all bits o
RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
Hi Richard,
Do you have any idea about this? I leverage git gcc-commit-mklog, it will
generate something as below. It looks no text after colon. I am not sure if I
need to add something by myself.
gcc/ChangeLog:
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
<=== no text here.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c:
<=== no text here.
* gcc.target/riscv/simplify_ior_optimization.c: New test.
# Please enter the commit message for your changes. Lines starting
# with '#' will be ignored, and an empty message aborts the commit.
#
# On branch master
# Your branch is up to date with 'origin/master'.
#
# Changes to be committed:
#...modified: gcc/simplify-rtx.cc
#...modified: gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
#...new file: gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, April 19, 2023 2:47 PM
To: Richard Biener
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com;
richard.sandif...@arm.com; Wang, Yanzhang
Subject: RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
Oh, I see. The message need to be re-generated. Thank you for pointing out,
will update ASPA.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, April 19, 2023 2:40 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com;
richard.sandif...@arm.com; Wang, Yanzhang
Subject: Re: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
On Tue, 18 Apr 2023, pan2...@intel.com wrote:
> From: Pan Li
>
> This patch add the optimization for the vector IOR(V1, NOT V1). Assume
> we have below sample code.
>
> vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t
> vl) {
> return __riscv_vmorn_mm_b32(v1, v1, vl); }
>
> Before this patch:
> vsetvli a5,zero,e8,mf4,ta,ma
> vlm.vv24,0(a1)
> vsetvli zero,a2,e8,mf4,ta,ma
> vmorn.mm v24,v24,v24
> vsetvli a5,zero,e8,mf4,ta,ma
> vsm.vv24,0(a0)
> ret
>
> After this patch:
> vsetvli zero,a2,e8,mf4,ta,ma
> vmset.m v24
> vsetvli a5,zero,e8,mf4,ta,ma
> vsm.v v24,0(a0)
> ret
>
> Or in RTL's perspective,
> from:
> (ior:VNx2BI (reg/v:VNx2BI 137 [ v1 ]) (not:VNx2BI (reg/v:VNx2BI 137 [
> v1 ])))
> to:
> (const_vector:VNx2BI repeat [ (const_int 1 [0x1]) ])
>
> The similar optimization like VMANDN has enabled already. There should
> be no difference execpt the operator when compare the VMORN and VMANDN
> for such kind of optimization. The patch allows the VECTOR_BOOL
> IOR(V1, NOT V1) simplification besides the existing SCALAR_INT mode.
>
> gcc/ChangeLog:
>
> * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
This needs some text
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/mask_insn_shortcut.c:
Likewise.
OK with that fixed.
> * gcc.target/riscv/simplify_ior_optimization.c: New test.
>
> Signed-off-by: Pan Li
> ---
> gcc/simplify-rtx.cc | 4 +-
> .../riscv/rvv/base/mask_insn_shortcut.c | 3 +-
> .../riscv/simplify_ior_optimization.c | 50 +++
> 3 files changed, 53 insertions(+), 4 deletions(-) create mode 100644
> gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
>
> diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index
> ee75079917f..3bc9b2f55ea 100644
> --- a/gcc/simplify-rtx.cc
> +++ b/gcc/simplify-rtx.cc
> @@ -3332,8 +3332,8 @@ simplify_context::simplify_binary_operation_1 (rtx_code
> code,
>if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1))
> || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0)))
> && ! side_effects_p (op0)
> - && SCALAR_INT_MODE_P (mode))
> - return constm1_rtx;
> + && GET_MODE_CLASS (mode) != MODE_CC)
> + return CONSTM1_RTX (mode);
>
>/* (ior A C) is C if all bits of A that might be nonzero are on in C.
> */
>if (CONST_INT_P (op1)
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> index 83cc4a1b5a5..57d0241675a 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> @@ -233,9 +233,8 @@ vbool64_t
> test_shortcut_for_riscv_vmxnor_case_6(vbool64_t v1, size_t vl) {
> /* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+} }
> } */
> /* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+} }
> } */
> /* { dg-final {
RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
Oh, I see. The message need to be re-generated. Thank you for pointing out,
will update ASPA.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, April 19, 2023 2:40 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com;
richard.sandif...@arm.com; Wang, Yanzhang
Subject: Re: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
On Tue, 18 Apr 2023, pan2...@intel.com wrote:
> From: Pan Li
>
> This patch add the optimization for the vector IOR(V1, NOT V1). Assume
> we have below sample code.
>
> vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t
> vl) {
> return __riscv_vmorn_mm_b32(v1, v1, vl); }
>
> Before this patch:
> vsetvli a5,zero,e8,mf4,ta,ma
> vlm.vv24,0(a1)
> vsetvli zero,a2,e8,mf4,ta,ma
> vmorn.mm v24,v24,v24
> vsetvli a5,zero,e8,mf4,ta,ma
> vsm.vv24,0(a0)
> ret
>
> After this patch:
> vsetvli zero,a2,e8,mf4,ta,ma
> vmset.m v24
> vsetvli a5,zero,e8,mf4,ta,ma
> vsm.v v24,0(a0)
> ret
>
> Or in RTL's perspective,
> from:
> (ior:VNx2BI (reg/v:VNx2BI 137 [ v1 ]) (not:VNx2BI (reg/v:VNx2BI 137 [
> v1 ])))
> to:
> (const_vector:VNx2BI repeat [ (const_int 1 [0x1]) ])
>
> The similar optimization like VMANDN has enabled already. There should
> be no difference execpt the operator when compare the VMORN and VMANDN
> for such kind of optimization. The patch allows the VECTOR_BOOL
> IOR(V1, NOT V1) simplification besides the existing SCALAR_INT mode.
>
> gcc/ChangeLog:
>
> * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
This needs some text
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/mask_insn_shortcut.c:
Likewise.
OK with that fixed.
> * gcc.target/riscv/simplify_ior_optimization.c: New test.
>
> Signed-off-by: Pan Li
> ---
> gcc/simplify-rtx.cc | 4 +-
> .../riscv/rvv/base/mask_insn_shortcut.c | 3 +-
> .../riscv/simplify_ior_optimization.c | 50 +++
> 3 files changed, 53 insertions(+), 4 deletions(-) create mode 100644
> gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
>
> diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index
> ee75079917f..3bc9b2f55ea 100644
> --- a/gcc/simplify-rtx.cc
> +++ b/gcc/simplify-rtx.cc
> @@ -3332,8 +3332,8 @@ simplify_context::simplify_binary_operation_1 (rtx_code
> code,
>if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1))
> || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0)))
> && ! side_effects_p (op0)
> - && SCALAR_INT_MODE_P (mode))
> - return constm1_rtx;
> + && GET_MODE_CLASS (mode) != MODE_CC)
> + return CONSTM1_RTX (mode);
>
>/* (ior A C) is C if all bits of A that might be nonzero are on in C.
> */
>if (CONST_INT_P (op1)
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> index 83cc4a1b5a5..57d0241675a 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> @@ -233,9 +233,8 @@ vbool64_t
> test_shortcut_for_riscv_vmxnor_case_6(vbool64_t v1, size_t vl) {
> /* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+} }
> } */
> /* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+} }
> } */
> /* { dg-final { scan-assembler-not {vmnor\.mm\s+v[0-9]+,\s*v[0-9]+} }
> } */
> -/* { dg-final { scan-assembler-times
> {vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
> /* { dg-final { scan-assembler-not {vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+}
> } } */
> /* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 14 } } */
> -/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 7 } } */
> +/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 14 } } */
> /* { dg-final { scan-assembler-times {vmmv\.m\s+v[0-9]+,\s*v[0-9]+}
> 14 } } */
> /* { dg-final { scan-assembler-times {vmnot\.m\s+v[0-9]+,\s*v[0-9]+}
> 14 } } */ diff --git
> a/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
> b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
> new file mode 100644
> index 000..ec3bd0baf03
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
> @@ -0,0 +1,50 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
> +
> +#include
> +
> +uint8_t test_simplify_ior_scalar_case_0 (uint8_t a) {
> + return a | ~a;
> +}
> +
> +uint16_t test_simplify_ior_
Re: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization
On Tue, 18 Apr 2023, pan2...@intel.com wrote:
> From: Pan Li
>
> This patch add the optimization for the vector IOR(V1, NOT V1). Assume
> we have below sample code.
>
> vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t vl)
> {
> return __riscv_vmorn_mm_b32(v1, v1, vl);
> }
>
> Before this patch:
> vsetvli a5,zero,e8,mf4,ta,ma
> vlm.vv24,0(a1)
> vsetvli zero,a2,e8,mf4,ta,ma
> vmorn.mm v24,v24,v24
> vsetvli a5,zero,e8,mf4,ta,ma
> vsm.vv24,0(a0)
> ret
>
> After this patch:
> vsetvli zero,a2,e8,mf4,ta,ma
> vmset.m v24
> vsetvli a5,zero,e8,mf4,ta,ma
> vsm.v v24,0(a0)
> ret
>
> Or in RTL's perspective,
> from:
> (ior:VNx2BI (reg/v:VNx2BI 137 [ v1 ]) (not:VNx2BI (reg/v:VNx2BI 137 [ v1 ])))
> to:
> (const_vector:VNx2BI repeat [ (const_int 1 [0x1]) ])
>
> The similar optimization like VMANDN has enabled already. There should
> be no difference execpt the operator when compare the VMORN and VMANDN
> for such kind of optimization. The patch allows the VECTOR_BOOL IOR(V1, NOT
> V1)
> simplification besides the existing SCALAR_INT mode.
>
> gcc/ChangeLog:
>
> * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
This needs some text
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/mask_insn_shortcut.c:
Likewise.
OK with that fixed.
> * gcc.target/riscv/simplify_ior_optimization.c: New test.
>
> Signed-off-by: Pan Li
> ---
> gcc/simplify-rtx.cc | 4 +-
> .../riscv/rvv/base/mask_insn_shortcut.c | 3 +-
> .../riscv/simplify_ior_optimization.c | 50 +++
> 3 files changed, 53 insertions(+), 4 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
>
> diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
> index ee75079917f..3bc9b2f55ea 100644
> --- a/gcc/simplify-rtx.cc
> +++ b/gcc/simplify-rtx.cc
> @@ -3332,8 +3332,8 @@ simplify_context::simplify_binary_operation_1 (rtx_code
> code,
>if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1))
> || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0)))
> && ! side_effects_p (op0)
> - && SCALAR_INT_MODE_P (mode))
> - return constm1_rtx;
> + && GET_MODE_CLASS (mode) != MODE_CC)
> + return CONSTM1_RTX (mode);
>
>/* (ior A C) is C if all bits of A that might be nonzero are on in C.
> */
>if (CONST_INT_P (op1)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> index 83cc4a1b5a5..57d0241675a 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
> @@ -233,9 +233,8 @@ vbool64_t test_shortcut_for_riscv_vmxnor_case_6(vbool64_t
> v1, size_t vl) {
> /* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
> /* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
> /* { dg-final { scan-assembler-not {vmnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
> -/* { dg-final { scan-assembler-times
> {vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
> /* { dg-final { scan-assembler-not {vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
> /* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 14 } } */
> -/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 7 } } */
> +/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 14 } } */
> /* { dg-final { scan-assembler-times {vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 14 } } */
> /* { dg-final { scan-assembler-times {vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 14 } }
> */
> diff --git a/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
> b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
> new file mode 100644
> index 000..ec3bd0baf03
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c
> @@ -0,0 +1,50 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
> +
> +#include
> +
> +uint8_t test_simplify_ior_scalar_case_0 (uint8_t a)
> +{
> + return a | ~a;
> +}
> +
> +uint16_t test_simplify_ior_scalar_case_1 (uint16_t a)
> +{
> + return a | ~a;
> +}
> +
> +uint32_t test_simplify_ior_scalar_case_2 (uint32_t a)
> +{
> + return a | ~a;
> +}
> +
> +uint64_t test_simplify_ior_scalar_case_3 (uint64_t a)
> +{
> + return a | ~a;
> +}
> +
> +int8_t test_simplify_ior_scalar_case_4 (int8_t a)
> +{
> + return a | ~a;
> +}
> +
> +int16_t test_simplify_ior_scalar_case_5 (int16_t a)
> +{
> + return a | ~a;
> +}
> +
> +int32_t test_simplify_ior_scalar_case_6 (int32_t a)
> +{
> + return a | ~a;
> +}
> +
> +int64_t test_simplify_ior_scalar_case_7 (int64_t a)
> +{
> + return a | ~a;
> +}
> +
> +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*-1} 6 } } */
> +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*255} 1 } } */
> +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*65536} 1 } } */
> +/* { dg-final
