Re: [PATCH, 2/2][ARM]: New CPU support for Marvell Whitney
On Feb 26, 2015, at 10:42 AM, Xingxing Pan xxing...@marvell.com wrote: ... Expand several arm types. 2015-02-26 Xingxing Pan xxing...@marvell.com * config/arm/types.md: (neon_logic): Expand to neon_logic_reg and neon_logic_imm. (neon_logic_q): Expand to neon_logic_reg_q and neon_logic_imm_q. (neon_from_gp): Expand to neon_from_gp and neon_from_gp_scalar. (neon_from_gp_q): Expand to neon_from_gp_q and neon_from_gp_scalar_q. (neon_to_gp): Expand to neon_to_gp and neon_to_gp_scalar. (neon_to_gp_q): Expand to neon_to_gp_q and neon_to_gp_scalar_q. * config/aarch64/aarch64-simd.md: Ditto. * config/aarch64/aarch64.md: Ditto. * config/aarch64/thunderx.md: Ditto. * config/arm/arm.md: Ditto. * config/arm/cortex-a15-neon.md: Ditto. * config/arm/cortex-a17-neon.md: Ditto. * config/arm/cortex-a57.md: Ditto. * config/arm/cortex-a8-neon.md: Ditto. * config/arm/cortex-a9-neon.md: Ditto. * config/arm/marvell-whitney.md: Ditto. * config/arm/neon.md: Ditto. * config/arm/xgene1.md: Ditto. I think you are going overkill with this approach. Instead of encoding operand types in INSN_TYPE_OPERAND_TYPE values, it seems simpler to add a new operand_type attribute and set it on affected insns. (define_attr op_type imm,reg,scalar,other (const_string other)) then in define_insn (example from first hunk of your patch): [(set_attr type neon_load1_1regq, neon_store1_1regq,\ neon_logicq, neon_to_gpq, neon_from_gpq,\ mov_reg, neon_moveq) (set_attr op_type *, *,\ reg, scalar,scalar,\ *, *)] and then in define_insn_reservation: --- a/gcc/config/arm/marvell-whitney.md +++ b/gcc/config/arm/marvell-whitney.md @@ -170,7 +170,7 @@ (const_string wTP41) (eq_attr type neon_permute_q,neon_zip_q) (const_string wTP42) (eq_attr type neon_bsl) (const_string wTP43) (and (eq_attr type neon_logic) (eq_attr op_type imm)) (const_string wTP43) (eq_attr type neon_arith_acc,neon_shift_acc) (if_then_else (match_test The point of this is that definitions of many architectures that don't care about operand type don't need to change. -- Maxim Kuvyrkov www.linaro.org
Re: [PATCH, 2/2][ARM]: New CPU support for Marvell Whitney
Hi, This patch expanding the following RTL types. And it has been merged to the latest code base. (neon_logic): Expand to neon_logic_reg and neon_logic_imm. (neon_logic_q): Expand to neon_logic_reg_q and neon_logic_imm_q. (neon_from_gp): Expand to neon_from_gp and neon_from_gp_scalar. (neon_from_gp_q): Expand to neon_from_gp_q and neon_from_gp_scalar_q. (neon_to_gp): Expand to neon_to_gp and neon_to_gp_scalar. (neon_to_gp_q): Expand to neon_to_gp_q and neon_to_gp_scalar_q. Is it OK for trunk? -- Regards, Xingxing commit b0d0ebf6a2553bc7b6cc8f72fbaa0104938d0d41 Author: Xingxing Pan xxing...@marvell.com Date: Wed Feb 25 14:46:25 2015 +0800 2015-02-25 Xingxing Pan xxing...@marvell.com * config/arm/types.md: (neon_logic): Expand to neon_logic_reg and neon_logic_imm. (neon_logic_q): Expand to neon_logic_reg_q and neon_logic_imm_q. (neon_from_gp): Expand to neon_from_gp and neon_from_gp_scalar. (neon_from_gp_q): Expand to neon_from_gp_q and neon_from_gp_scalar_q. (neon_to_gp): Expand to neon_to_gp and neon_to_gp_scalar. (neon_to_gp_q): Expand to neon_to_gp_q and neon_to_gp_scalar_q. * config/aarch64/aarch64-simd.md: Ditto. * config/aarch64/aarch64.md: Ditto. * config/aarch64/thunderx.md: Ditto. * config/arm/arm.md: Ditto. * config/arm/cortex-a15-neon.md: Ditto. * config/arm/cortex-a17-neon.md: Ditto. * config/arm/cortex-a57.md: Ditto. * config/arm/cortex-a8-neon.md: Ditto. * config/arm/cortex-a9-neon.md: Ditto. * config/arm/marvell-whitney.md: Ditto. * config/arm/neon.md: Ditto. * config/arm/types.md: Ditto. * config/arm/xgene1.md: Ditto. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 0557570..611d14c 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -115,7 +115,7 @@ } } [(set_attr type neon_load1_1regq, neon_store1_1regq,\ - neon_logicq, neon_to_gpq, neon_from_gpq,\ + neon_logic_regq, neon_to_gp_scalarq, neon_from_gp_scalarq,\ mov_reg, neon_moveq)] ) @@ -147,7 +147,7 @@ } } [(set_attr type neon_load1_1regq, neon_store1_1regq,\ - neon_logicq, multiple, multiple, multiple,\ + neon_logic_regq, multiple, multiple, multiple,\ neon_moveq) (set_attr length 4,4,4,8,8,8,4)] ) @@ -218,7 +218,7 @@ (match_operand:VQ 2 vect_par_cnst_lo_half )))] TARGET_SIMD reload_completed umov\t%0, %1.d[0] - [(set_attr type neon_to_gpq) + [(set_attr type neon_to_gp_scalarq) (set_attr length 4) ]) @@ -229,7 +229,7 @@ (match_operand:VQ 2 vect_par_cnst_hi_half )))] TARGET_SIMD reload_completed umov\t%0, %1.d[1] - [(set_attr type neon_to_gpq) + [(set_attr type neon_to_gp_scalarq) (set_attr length 4) ]) @@ -239,7 +239,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD orn\t%0.Vbtype, %2.Vbtype, %1.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn bicmode3 @@ -248,7 +248,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD bic\t%0.Vbtype, %2.Vbtype, %1.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn addmode3 @@ -444,7 +444,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD and\t%0.Vbtype, %1.Vbtype, %2.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn iormode3 @@ -453,7 +453,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD orr\t%0.Vbtype, %1.Vbtype, %2.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn xormode3 @@ -462,7 +462,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD eor\t%0.Vbtype, %1.Vbtype, %2.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn one_cmplmode2 @@ -470,7 +470,7 @@ (not:VDQ_I (match_operand:VDQ_I 1 register_operand w)))] TARGET_SIMD not\t%0.Vbtype, %1.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn aarch64_simd_vec_setmode @@ -496,7 +496,7 @@ gcc_unreachable (); } } - [(set_attr type neon_from_gpq, neon_insq, neon_load1_1regq)] + [(set_attr type neon_from_gp_scalarq, neon_insq, neon_load1_1regq)] ) (define_insn aarch64_simd_lshrmode @@ -816,7 +816,7 @@ gcc_unreachable (); } } - [(set_attr type neon_from_gp, neon_ins_q)] + [(set_attr type neon_from_gp_scalar, neon_ins_q)] ) (define_expand vec_setv2di @@ -2426,7 +2426,7 @@ operands[2] = GEN_INT (ENDIAN_LANE_N (MODEmode, INTVAL (operands[2]))); return smov\\t%GPI:w0, %1.VDQQH:Vetype[%2]; } - [(set_attr type neon_to_gpq)]
Re: [PATCH, 2/2][ARM]: New CPU support for Marvell Whitney
On 02/25/2015 09:42 PM, Xingxing Pan wrote: Hi, This patch expanding the following RTL types. And it has been merged to the latest code base. (neon_logic): Expand to neon_logic_reg and neon_logic_imm. (neon_logic_q): Expand to neon_logic_reg_q and neon_logic_imm_q. (neon_from_gp): Expand to neon_from_gp and neon_from_gp_scalar. (neon_from_gp_q): Expand to neon_from_gp_q and neon_from_gp_scalar_q. (neon_to_gp): Expand to neon_to_gp and neon_to_gp_scalar. (neon_to_gp_q): Expand to neon_to_gp_q and neon_to_gp_scalar_q. Is it OK for trunk? Fix typos in commit message. -- Regards, Xingxing commit b0d0ebf6a2553bc7b6cc8f72fbaa0104938d0d41 Author: Xingxing Pan xxing...@marvell.com Date: Wed Feb 25 14:46:25 2015 +0800 2015-02-25 Xingxing Pan xxing...@marvell.com * config/arm/types.md: (neon_logic): Expand to neon_logic_reg and neon_logic_imm. (neon_logic_q): Expand to neon_logic_reg_q and neon_logic_imm_q. (neon_from_gp): Expand to neon_from_gp and neon_from_gp_scalar. (neon_from_gp_q): Expand to neon_from_gp_q and neon_from_gp_scalar_q. (neon_to_gp): Expand to neon_to_gp and neon_to_gp_scalar. (neon_to_gp_q): Expand to neon_to_gp_q and neon_to_gp_scalar_q. * config/aarch64/aarch64-simd.md: Ditto. * config/aarch64/aarch64.md: Ditto. * config/aarch64/thunderx.md: Ditto. * config/arm/arm.md: Ditto. * config/arm/cortex-a15-neon.md: Ditto. * config/arm/cortex-a17-neon.md: Ditto. * config/arm/cortex-a57.md: Ditto. * config/arm/cortex-a8-neon.md: Ditto. * config/arm/cortex-a9-neon.md: Ditto. * config/arm/marvell-whitney.md: Ditto. * config/arm/neon.md: Ditto. * config/arm/xgene1.md: Ditto. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 0557570..611d14c 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -115,7 +115,7 @@ } } [(set_attr type neon_load1_1regq, neon_store1_1regq,\ - neon_logicq, neon_to_gpq, neon_from_gpq,\ + neon_logic_regq, neon_to_gp_scalarq, neon_from_gp_scalarq,\ mov_reg, neon_moveq)] ) @@ -147,7 +147,7 @@ } } [(set_attr type neon_load1_1regq, neon_store1_1regq,\ - neon_logicq, multiple, multiple, multiple,\ + neon_logic_regq, multiple, multiple, multiple,\ neon_moveq) (set_attr length 4,4,4,8,8,8,4)] ) @@ -218,7 +218,7 @@ (match_operand:VQ 2 vect_par_cnst_lo_half )))] TARGET_SIMD reload_completed umov\t%0, %1.d[0] - [(set_attr type neon_to_gpq) + [(set_attr type neon_to_gp_scalarq) (set_attr length 4) ]) @@ -229,7 +229,7 @@ (match_operand:VQ 2 vect_par_cnst_hi_half )))] TARGET_SIMD reload_completed umov\t%0, %1.d[1] - [(set_attr type neon_to_gpq) + [(set_attr type neon_to_gp_scalarq) (set_attr length 4) ]) @@ -239,7 +239,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD orn\t%0.Vbtype, %2.Vbtype, %1.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn bicmode3 @@ -248,7 +248,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD bic\t%0.Vbtype, %2.Vbtype, %1.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn addmode3 @@ -444,7 +444,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD and\t%0.Vbtype, %1.Vbtype, %2.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn iormode3 @@ -453,7 +453,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD orr\t%0.Vbtype, %1.Vbtype, %2.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn xormode3 @@ -462,7 +462,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD eor\t%0.Vbtype, %1.Vbtype, %2.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn one_cmplmode2 @@ -470,7 +470,7 @@ (not:VDQ_I (match_operand:VDQ_I 1 register_operand w)))] TARGET_SIMD not\t%0.Vbtype, %1.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn aarch64_simd_vec_setmode @@ -496,7 +496,7 @@ gcc_unreachable (); } } - [(set_attr type neon_from_gpq, neon_insq, neon_load1_1regq)] + [(set_attr type neon_from_gp_scalarq, neon_insq, neon_load1_1regq)] ) (define_insn aarch64_simd_lshrmode @@ -816,7 +816,7 @@ gcc_unreachable (); } } - [(set_attr type neon_from_gp, neon_ins_q)] + [(set_attr type neon_from_gp_scalar, neon_ins_q)] ) (define_expand vec_setv2di @@ -2426,7 +2426,7 @@ operands[2] = GEN_INT (ENDIAN_LANE_N (MODEmode, INTVAL (operands[2]))); return smov\\t%GPI:w0,
Re: [PATCH, 2/2][ARM]: New CPU support for Marvell Whitney
On Wed, Feb 25, 2015 at 01:42:39PM +, Xingxing Pan wrote: Hi, This patch expanding the following RTL types. And it has been merged to the latest code base. (neon_logic): Expand to neon_logic_reg and neon_logic_imm. (neon_logic_q): Expand to neon_logic_reg_q and neon_logic_imm_q. (neon_from_gp): Expand to neon_from_gp and neon_from_gp_scalar. (neon_from_gp_q): Expand to neon_from_gp_q and neon_from_gp_scalar_q. (neon_to_gp): Expand to neon_to_gp and neon_to_gp_scalar. (neon_to_gp_q): Expand to neon_to_gp_q and neon_to_gp_scalar_q. Is it OK for trunk? -- Regards, Xingxing I've had a look through the AArch64 parts, and they look OK to me (though only Marcus or Richard can approve them), I have one additional comment. ;; In this insn, operand 1 should be low, and operand 2 the high part of the diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 8f157ce..8be2ebf 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -828,7 +828,7 @@ } } [(set_attr type mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\ - neon_from_gpq,neon_from_gpq, neon_dup) + neon_to_gp_scalarq,neon_from_gpq, neon_dup) (set_attr simd *,*,yes,*,*,*,*,yes,yes,yes)] ) Here you change neon_from_gpq to neon_to_gp_scalarq. This looks like the correct thing to do, but would you mind pulling it out to a separate patch, first changing neon_from_gpq to neon_to_gpq? I'd just like to have the bug-fix separate from the bigger infrastructure change. Thanks, James
Re: [PATCH, 2/2][ARM]: New CPU support for Marvell Whitney
On 02/25/2015 10:20 PM, James Greenhalgh wrote: On Wed, Feb 25, 2015 at 01:42:39PM +, Xingxing Pan wrote: Hi, This patch expanding the following RTL types. And it has been merged to the latest code base. (neon_logic): Expand to neon_logic_reg and neon_logic_imm. (neon_logic_q): Expand to neon_logic_reg_q and neon_logic_imm_q. (neon_from_gp): Expand to neon_from_gp and neon_from_gp_scalar. (neon_from_gp_q): Expand to neon_from_gp_q and neon_from_gp_scalar_q. (neon_to_gp): Expand to neon_to_gp and neon_to_gp_scalar. (neon_to_gp_q): Expand to neon_to_gp_q and neon_to_gp_scalar_q. Is it OK for trunk? -- Regards, Xingxing I've had a look through the AArch64 parts, and they look OK to me (though only Marcus or Richard can approve them), I have one additional comment. ;; In this insn, operand 1 should be low, and operand 2 the high part of the diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 8f157ce..8be2ebf 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -828,7 +828,7 @@ } } [(set_attr type mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\ - neon_from_gpq,neon_from_gpq, neon_dup) + neon_to_gp_scalarq,neon_from_gpq, neon_dup) (set_attr simd *,*,yes,*,*,*,*,yes,yes,yes)] ) Here you change neon_from_gpq to neon_to_gp_scalarq. This looks like the correct thing to do, but would you mind pulling it out to a separate patch, first changing neon_from_gpq to neon_to_gpq? I'd just like to have the bug-fix separate from the bigger infrastructure change. Thanks, James Hi James, Thanks for your advice. I have submitted another patch to change the type from neon_from_gpq to neon_to_gpq. See https://gcc.gnu.org/ml/gcc-patches/2015-02/msg01566.html. Attach the updated patch. -- Regards, Xingxing Expand several arm types. 2015-02-26 Xingxing Pan xxing...@marvell.com * config/arm/types.md: (neon_logic): Expand to neon_logic_reg and neon_logic_imm. (neon_logic_q): Expand to neon_logic_reg_q and neon_logic_imm_q. (neon_from_gp): Expand to neon_from_gp and neon_from_gp_scalar. (neon_from_gp_q): Expand to neon_from_gp_q and neon_from_gp_scalar_q. (neon_to_gp): Expand to neon_to_gp and neon_to_gp_scalar. (neon_to_gp_q): Expand to neon_to_gp_q and neon_to_gp_scalar_q. * config/aarch64/aarch64-simd.md: Ditto. * config/aarch64/aarch64.md: Ditto. * config/aarch64/thunderx.md: Ditto. * config/arm/arm.md: Ditto. * config/arm/cortex-a15-neon.md: Ditto. * config/arm/cortex-a17-neon.md: Ditto. * config/arm/cortex-a57.md: Ditto. * config/arm/cortex-a8-neon.md: Ditto. * config/arm/cortex-a9-neon.md: Ditto. * config/arm/marvell-whitney.md: Ditto. * config/arm/neon.md: Ditto. * config/arm/xgene1.md: Ditto. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 0557570..611d14c 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -115,7 +115,7 @@ } } [(set_attr type neon_load1_1regq, neon_store1_1regq,\ - neon_logicq, neon_to_gpq, neon_from_gpq,\ + neon_logic_regq, neon_to_gp_scalarq, neon_from_gp_scalarq,\ mov_reg, neon_moveq)] ) @@ -147,7 +147,7 @@ } } [(set_attr type neon_load1_1regq, neon_store1_1regq,\ - neon_logicq, multiple, multiple, multiple,\ + neon_logic_regq, multiple, multiple, multiple,\ neon_moveq) (set_attr length 4,4,4,8,8,8,4)] ) @@ -218,7 +218,7 @@ (match_operand:VQ 2 vect_par_cnst_lo_half )))] TARGET_SIMD reload_completed umov\t%0, %1.d[0] - [(set_attr type neon_to_gpq) + [(set_attr type neon_to_gp_scalarq) (set_attr length 4) ]) @@ -229,7 +229,7 @@ (match_operand:VQ 2 vect_par_cnst_hi_half )))] TARGET_SIMD reload_completed umov\t%0, %1.d[1] - [(set_attr type neon_to_gpq) + [(set_attr type neon_to_gp_scalarq) (set_attr length 4) ]) @@ -239,7 +239,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD orn\t%0.Vbtype, %2.Vbtype, %1.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn bicmode3 @@ -248,7 +248,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD bic\t%0.Vbtype, %2.Vbtype, %1.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn addmode3 @@ -444,7 +444,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD and\t%0.Vbtype, %1.Vbtype, %2.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn iormode3 @@ -453,7 +453,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD orr\t%0.Vbtype, %1.Vbtype, %2.Vbtype - [(set_attr type neon_logicq)]
Re: [PATCH, 2/2][ARM]: New CPU support for Marvell Whitney
On Fri, Dec 19, 2014 at 08:19:17AM +, Xingxing Pan wrote: Hi, This patch expands the arm types neon_logicq, neon_from_gpq and neon_to_gpq. This change mainly suits to marvell-whitney cores, and will not affect other arm core's pipeline description. neon_logicq is expanded to neon_logic_regq and neon_logic_immq, corresponding respectively to the predicates s_register_operand and imm_for_neon_logic_operand. neon_from/to_gpq is expanded to neon_reg_from/to_gpq and neon_lane_from/to_gpq, decided by whether the neon side is a single register or a register lane. Sorry to ask for churn here, but the naming scheme for lane operations elsewhere in types.md seems to be: neon_operation_scalar_q as in: ; neon_mul_s_scalar ; neon_mul_s_scalar_q I think the types you are introducing should be: neon_from_gp_scalarq neon_to_gp_scalarq Thanks, James
Re: [PATCH, 2/2][ARM]: New CPU support for Marvell Whitney
On 19/12/2014 17:35, James Greenhalgh wrote: On Fri, Dec 19, 2014 at 08:19:17AM +, Xingxing Pan wrote: Hi, This patch expands the arm types neon_logicq, neon_from_gpq and neon_to_gpq. This change mainly suits to marvell-whitney cores, and will not affect other arm core's pipeline description. neon_logicq is expanded to neon_logic_regq and neon_logic_immq, corresponding respectively to the predicates s_register_operand and imm_for_neon_logic_operand. neon_from/to_gpq is expanded to neon_reg_from/to_gpq and neon_lane_from/to_gpq, decided by whether the neon side is a single register or a register lane. Sorry to ask for churn here, but the naming scheme for lane operations elsewhere in types.md seems to be: neon_operation_scalar_q as in: ; neon_mul_s_scalar ; neon_mul_s_scalar_q I think the types you are introducing should be: neon_from_gp_scalarq neon_to_gp_scalarq Thanks, James Hi James, Thanks for your comment. I've changed the type names. Regards, Xingxing 2014-12-19 Xingxing Pan xxing...@marvell.com * config/arm/types.md: (neon_logic): Expand to neon_logic_reg and neon_logic_imm. (neon_logic_q): Expand to neon_logic_reg_q and neon_logic_imm_q. (neon_from_gp): Expand to neon_from_gp and neon_from_gp_scalar. (neon_from_gp_q): Expand to neon_from_gp_q and neon_from_gp_scalar_q. (neon_to_gp): Expand to neon_to_gp and neon_to_gp_scalar. (neon_to_gp_q): Expand to neon_to_gp_q and neon_to_gp_scalar_q. * config/aarch64/aarch64-simd.md: Ditto. * config/aarch64/aarch64.md: Ditto. * config/aarch64/thunderx.md: Ditto. * config/arm/arm.md: Ditto. * config/arm/cortex-a15-neon.md: Ditto. * config/arm/cortex-a17-neon.md: Ditto. * config/arm/cortex-a8-neon.md: Ditto. * config/arm/cortex-a9-neon.md: Ditto. * config/arm/neon.md: Ditto. * config/arm/whitney.md: Ditto. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index d4256a5..63a2b7e 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -115,7 +115,7 @@ } } [(set_attr type neon_load1_1regq, neon_store1_1regq,\ - neon_logicq, neon_to_gpq, neon_from_gpq,\ + neon_logic_regq, neon_to_gp_scalarq, neon_from_gp_scalarq,\ mov_reg, neon_moveq)] ) @@ -147,7 +147,7 @@ } } [(set_attr type neon_load1_1regq, neon_store1_1regq,\ - neon_logicq, multiple, multiple, multiple,\ + neon_logic_regq, multiple, multiple, multiple,\ neon_moveq) (set_attr length 4,4,4,8,8,8,4)] ) @@ -227,7 +227,7 @@ (match_operand:VQ 2 vect_par_cnst_lo_half )))] TARGET_SIMD reload_completed umov\t%0, %1.d[0] - [(set_attr type neon_to_gpq) + [(set_attr type neon_to_gp_scalarq) (set_attr length 4) ]) @@ -238,7 +238,7 @@ (match_operand:VQ 2 vect_par_cnst_hi_half )))] TARGET_SIMD reload_completed umov\t%0, %1.d[1] - [(set_attr type neon_to_gpq) + [(set_attr type neon_to_gp_scalarq) (set_attr length 4) ]) @@ -248,7 +248,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD orn\t%0.Vbtype, %2.Vbtype, %1.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn bicmode3 @@ -257,7 +257,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD bic\t%0.Vbtype, %2.Vbtype, %1.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn addmode3 @@ -440,7 +440,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD and\t%0.Vbtype, %1.Vbtype, %2.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn iormode3 @@ -449,7 +449,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD orr\t%0.Vbtype, %1.Vbtype, %2.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn xormode3 @@ -458,7 +458,7 @@ (match_operand:VDQ_I 2 register_operand w)))] TARGET_SIMD eor\t%0.Vbtype, %1.Vbtype, %2.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn one_cmplmode2 @@ -466,7 +466,7 @@ (not:VDQ_I (match_operand:VDQ_I 1 register_operand w)))] TARGET_SIMD not\t%0.Vbtype, %1.Vbtype - [(set_attr type neon_logicq)] + [(set_attr type neon_logic_regq)] ) (define_insn aarch64_simd_vec_setmode @@ -492,7 +492,7 @@ gcc_unreachable (); } } - [(set_attr type neon_from_gpq, neon_insq, neon_load1_1regq)] + [(set_attr type neon_from_gp_scalarq, neon_insq, neon_load1_1regq)] ) (define_insn aarch64_simd_lshrmode @@ -832,7 +832,7 @@ gcc_unreachable (); } } - [(set_attr type neon_from_gp, neon_ins_q)] + [(set_attr type
