Re: [PATCH, RTL] Prepare ARM build with LRA
below is a trivial patch, which makes both parts of test signed. With this, bootstrap completes on powerpc-darwin9 - however, you might want to check that it still does what you intended. Please install under PR middle-end/58547 if not already done. -- Eric Botcazou
Re: [PATCH, RTL] Prepare ARM build with LRA
Hi Yvan,
On 24 Sep 2013, at 09:29, Yvan Roux wrote:
On 11 September 2013 21:08, Yvan Roux yvan.r...@linaro.org wrote:
Here is the new patch discussed in the other thread.
Thanks
Yvan
2013-09-11 Yvan Roux yvan.r...@linaro.org
Vladimir Makarov vmaka...@redhat.com
* rtlanal.c (lsb_bitfield_op_p): New predicate for bitfield
operations
from the least significant bit.
(strip_address_mutations): Add bitfield operations handling.
(shift_code_p): New predicate for shifting operations.
(must_be_index_p): Add shifting operations handling.
(set_address_index): Likewise.
as discussed on irc, this part (applied as r202914) breaks bootstrap on
powerpc-darwin9 (and, presumably, other BE targets) with a signed/unsigned
compare error at rtlanal.c:5482
below is a trivial patch, which makes both parts of test signed.
With this, bootstrap completes on powerpc-darwin9 - however, you might want to
check that it still does what you intended.
thanks
Iain
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 24cbcd2..0349bcc 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -5476,7 +5476,7 @@ lsb_bitfield_op_p (rtx x)
if (GET_RTX_CLASS (GET_CODE (x)) == RTX_BITFIELD_OPS)
{
enum machine_mode mode = GET_MODE (XEXP (x, 0));
- unsigned HOST_WIDE_INT len = INTVAL (XEXP (x, 1));
+ HOST_WIDE_INT len = INTVAL (XEXP (x, 1));
HOST_WIDE_INT pos = INTVAL (XEXP (x, 2));
return (pos == (BITS_BIG_ENDIAN ? GET_MODE_PRECISION (mode) - len : 0));
Re: [PATCH, RTL] Prepare ARM build with LRA
(Added Eric and Richard)
Sorry for the inconvenience Iain, It's ok for my side.
Thanks,
Yvan
On 26 September 2013 13:18, Iain Sandoe i...@codesourcery.com wrote:
Hi Yvan,
On 24 Sep 2013, at 09:29, Yvan Roux wrote:
On 11 September 2013 21:08, Yvan Roux yvan.r...@linaro.org wrote:
Here is the new patch discussed in the other thread.
Thanks
Yvan
2013-09-11 Yvan Roux yvan.r...@linaro.org
Vladimir Makarov vmaka...@redhat.com
* rtlanal.c (lsb_bitfield_op_p): New predicate for bitfield
operations
from the least significant bit.
(strip_address_mutations): Add bitfield operations handling.
(shift_code_p): New predicate for shifting operations.
(must_be_index_p): Add shifting operations handling.
(set_address_index): Likewise.
as discussed on irc, this part (applied as r202914) breaks bootstrap on
powerpc-darwin9 (and, presumably, other BE targets) with a signed/unsigned
compare error at rtlanal.c:5482
below is a trivial patch, which makes both parts of test signed.
With this, bootstrap completes on powerpc-darwin9 - however, you might want
to check that it still does what you intended.
thanks
Iain
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 24cbcd2..0349bcc 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -5476,7 +5476,7 @@ lsb_bitfield_op_p (rtx x)
if (GET_RTX_CLASS (GET_CODE (x)) == RTX_BITFIELD_OPS)
{
enum machine_mode mode = GET_MODE (XEXP (x, 0));
- unsigned HOST_WIDE_INT len = INTVAL (XEXP (x, 1));
+ HOST_WIDE_INT len = INTVAL (XEXP (x, 1));
HOST_WIDE_INT pos = INTVAL (XEXP (x, 2));
return (pos == (BITS_BIG_ENDIAN ? GET_MODE_PRECISION (mode) - len :
0));
Re: [PATCH, RTL] Prepare ARM build with LRA
Ping On 16 September 2013 10:57, Yvan Roux yvan.r...@linaro.org wrote: Adding Eric and Steven in the loop as it is RTL related. Thanks Yvan On 11 September 2013 21:08, Yvan Roux yvan.r...@linaro.org wrote: Here is the new patch discussed in the other thread. Thanks Yvan 2013-09-11 Yvan Roux yvan.r...@linaro.org Vladimir Makarov vmaka...@redhat.com * rtlanal.c (lsb_bitfield_op_p): New predicate for bitfield operations from the least significant bit. (strip_address_mutations): Add bitfield operations handling. (shift_code_p): New predicate for shifting operations. (must_be_index_p): Add shifting operations handling. (set_address_index): Likewise.
