LGTM.
juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-10-27 03:19 To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai CC: rdapp.gcc Subject: [PATCH] RISC-V: Fix cond_sqrt tests. Hi, as long as we do not have universal Zvfh support in binutils linking against libm does not work out of the box. This patch splits the cond_sqrt tests into non-zvfh and zvfh variants and makes the run-zvfh ones depend on a zvfh target. While at it, I also added Zvfh handling to the testsuite helpers. Regards Robin From f5c43e700c0343ec32d95a28226837e26c1bfdca Mon Sep 17 00:00:00 2001 From: Robin Dapp <rd...@ventanamicro.com> Date: Thu, 26 Oct 2023 20:40:00 +0200 Subject: [PATCH] RISC-V: Fix cond_sqrt tests. As long as we do not have universal Zvfh support in binutils linking against libm does not work out of the box. This patch splits the cond_sqrt tests into non-zvfh and zvfh variants and makes the run-zvfh ones depend on a zvfh target. While at it, I also added Zvfh handling to the testsuite helpers. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Remove Float16. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Ditto. * lib/target-supports.exp: Add zvfh handling. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c: New test. --- .../riscv/rvv/autovec/cond/cond_sqrt-1.c | 5 +- .../riscv/rvv/autovec/cond/cond_sqrt-2.c | 5 +- .../riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c | 21 ++++++++ .../riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c | 22 ++++++++ .../rvv/autovec/cond/cond_sqrt_run-zvfh-1.c | 29 +++++++++++ .../rvv/autovec/cond/cond_sqrt_run-zvfh-2.c | 29 +++++++++++ gcc/testsuite/lib/target-supports.exp | 50 ++++++++++++++++++- 7 files changed, 154 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c index c7bd37e4f0e..ef17d3b25a7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include <stdint-gcc.h> @@ -13,12 +13,11 @@ } #define TEST_ALL(T) \ - T (_Float16, __builtin_sqrtf16) \ T (float, __builtin_sqrtf) \ T (double, __builtin_sqrt) TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {\tvfsqrt\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfsqrt\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c index c2fb92fbbbf..5fbd63c32f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ #include <stdint-gcc.h> @@ -13,12 +13,11 @@ } #define TEST_ALL(T) \ - T (_Float16, __builtin_sqrtf16) \ T (float, __builtin_sqrtf) \ T (double, __builtin_sqrt) TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {\tvfsqrt\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfsqrt\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c new file mode 100644 index 00000000000..c632d63ff7a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include <stdint-gcc.h> + +#define DEF_LOOP(TYPE, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = pred[i] ? OP (a[i]) : a[i]; \ + } + +#define TEST_ALL(T) \ + T (_Float16, __builtin_sqrtf16) \ + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tvfsqrt\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ +/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c new file mode 100644 index 00000000000..8e1bc60a0d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include <stdint-gcc.h> + +#define DEF_LOOP(TYPE, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = pred[i] ? OP (a[i]) : b[i]; \ + } + +#define TEST_ALL(T) \ + T (_Float16, __builtin_sqrtf16) \ + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tvfsqrt\.v\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */ + +/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c new file mode 100644 index 00000000000..c96a1a6b099 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c @@ -0,0 +1,29 @@ +/* { dg-do run { target { riscv_zvfh } } } */ +/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */ + +#include "cond_sqrt-zvfh-1.c" +#include <stdio.h> + +#define N 99 + +#define TEST_LOOP(TYPE, OP) \ + { \ + TYPE r[N], a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : 2); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##TYPE##_##OP (r, a, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? OP (a[i]) : a[i])) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c new file mode 100644 index 00000000000..3386242bdad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c @@ -0,0 +1,29 @@ +/* { dg-do run { target { riscv_zvfh } } } */ +/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ + +#include "cond_sqrt-zvfh-2.c" + +#define N 99 + +#define TEST_LOOP(TYPE, OP) \ + { \ + TYPE r[N], a[N], b[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : 2); \ + b[i] = (i % 9) * (i % 7 + 1); \ + pred[i] = (i % 7 < 4); \ + asm volatile("" ::: "memory"); \ + } \ + test_##TYPE##_##OP (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? OP (a[i]) : b[i])) \ + __builtin_abort (); \ + } + +int +main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index f0b692a2e19..50e8004f13b 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1925,6 +1925,17 @@ proc check_effective_target_riscv_v { } { }] } +# Return 1 if the target arch supports the Zvfh extension, 0 otherwise. +# Cache the result. + +proc check_effective_target_riscv_zvfh { } { + return [check_no_compiler_messages riscv_ext_zvfh assembly { + #ifndef __riscv_zvfh + #error "Not __riscv_zvfh" + #endif + }] +} + # Return 1 if the target arch supports half float, 0 otherwise. # Note, this differs from the test performed by # /* dg-skip-if "" { *-*-* } { "*" } { "-march=rv*zfh*" } */ @@ -1990,10 +2001,35 @@ proc check_effective_target_riscv_zfh_ok { } { return 0 } +# Return 1 if we can execute code when using dg-add-options riscv_zvfh + +proc check_effective_target_riscv_zvfh_ok { } { + # If the target already supports v without any added options, + # we may assume we can execute just fine. + if { [check_effective_target_riscv_zvfh] } { + return 1 + } + + # check if we can execute vector insns with the given hardware or + # simulator + set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v] + if { [check_runtime ${gcc_march}_exec { + int main() + { + asm ("vsetivli zero,8,e16,m1,ta,ma"); + asm ("vfadd.vv v8,v8,v16" : : : "v8"); + return 0; + } } "-march=${gcc_march}"] } { + return 1 + } + + return 0 +} + proc riscv_get_arch { } { set gcc_march "" # ??? do we neeed to add more extensions to the list below? - foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs } { + foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvfh } { if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] { #ifndef DEF #error "Not DEF" @@ -2052,6 +2088,18 @@ proc add_options_for_riscv_zfh { flags } { return "$flags -march=[riscv_get_arch]_zfh" } +proc add_options_for_riscv_zvfh { flags } { + if { [lsearch $flags -march=*] >= 0 } { + # If there are multiple -march flags, we have to adjust all of them. + set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zvfh ] + return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zvfh[[:alnum:]_.]*)_zvfh} $flags \\1 ] + } + if { [check_effective_target_riscv_zvfh] } { + return "$flags" + } + return "$flags -march=[riscv_get_arch]_zvfh" +} + # Return 1 if the target OS supports running SSE executables, 0 # otherwise. Cache the result. -- 2.41.0