LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-20 15:03
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Reorganize and rename combine patterns in
autovec-opt.md
This patch reorganize and rename the combine patterns in autovec-opt.md
by category. There shouldn't be any functional changes.
The current classification includes the following categories:
- Combine op + vmerge to cond_op
- Combine binop + trunc to narrow_binop
- Combine extend + binop to widen_binop
- Combine extend + ternop to widen_ternop
- Misc combine patterns
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*not): Move and rename.
(*n): Ditto.
(*vtrunc): Ditto.
(*trunc): Ditto.
(*narrow_): Ditto.
(*narrow__scalar): Ditto.
(*single_widen_mult): Ditto.
(*single_widen_mul): Ditto.
(*single_widen_mult): Ditto.
(*single_widen_mul): Ditto.
(*dual_widen_fma): Ditto.
(*dual_widen_fma): Ditto.
(*single_widen_fma): Ditto.
(*single_widen_fma): Ditto.
(*dual_fma): Ditto.
(*single_fma): Ditto.
(*dual_fnma): Ditto.
(*dual_widen_fnma): Ditto.
(*single_fnma): Ditto.
(*single_widen_fnma): Ditto.
(*dual_fms): Ditto.
(*dual_widen_fms): Ditto.
(*single_fms): Ditto.
(*single_widen_fms): Ditto.
(*dual_fnms): Ditto.
(*dual_widen_fnms): Ditto.
(*single_fnms): Ditto.
(*single_widen_fnms): Ditto.
---
gcc/config/riscv/autovec-opt.md | 203 ++--
1 file changed, 91 insertions(+), 112 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 66c77ad6ebb..46a344407c7 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -58,104 +58,6 @@
}
)
-;; -
-;; [BOOL] Binary logical operations (inverted second input)
-;; -
-;; Includes:
-;; - vmandnot.mm
-;; - vmornot.mm
-;; -
-
-(define_insn_and_split "*not"
- [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
- (bitmanip_bitwise:VB_VLS
- (not:VB_VLS (match_operand:VB_VLS 2 "register_operand" " vr"))
- (match_operand:VB_VLS 1 "register_operand" " vr")))]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
- {
-insn_code icode = code_for_pred_not (, mode);
-riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_MASK_OP,
operands);
-DONE;
- }
- [(set_attr "type" "vmalu")
- (set_attr "mode" "")])
-
-;; -
-;; [BOOL] Binary logical operations (inverted result)
-;; -
-;; Includes:
-;; - vmnand.mm
-;; - vmnor.mm
-;; - vmxnor.mm
-;; -
-
-(define_insn_and_split "*n"
- [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
- (not:VB_VLS
- (any_bitwise:VB_VLS
- (match_operand:VB_VLS 1 "register_operand" " vr")
- (match_operand:VB_VLS 2 "register_operand" " vr"]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
- {
-insn_code icode = code_for_pred_n (, mode);
-riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_MASK_OP,
operands);
-DONE;
- }
- [(set_attr "type" "vmalu")
- (set_attr "mode" "")])
-
-;; -
-;; [INT] Binary narrow shifts.
-;; -
-;; Includes:
-;; - vnsrl.wv/vnsrl.wx/vnsrl.wi
-;; - vnsra.wv/vnsra.wx/vnsra.wi
-;; -
-
-(define_insn_and_split "*vtrunc"
- [(set (match_operand: 0 "register_operand" "=vr,vr")
-(truncate:
- (any_shiftrt:VWEXTI
-(match_operand:VWEXTI 1 "register_operand" " vr,vr")
- (any_extend:VWEXTI
- (match_operand: 2 "vector_shift_operand" "
vr,vk")]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- insn_code icode = code_for_pred_narrow (, mode);
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
- DONE;
-}
- [(set_attr "type" "vnshift")
- (set_attr "mode" "")])
-
-(define_insn_and_split "*trunc"
- [(set (match_operand: 0 "register_operand" "=vr")
-(truncate:
- (any_shiftrt:VWEXTI
-(match_operand:VWEXTI 1 "register_operand" " vr")
- (match_operand: 2 "csr_operand" " rK"]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- operands[2] = gen_lowpart (Pmode, operands[2]);
- insn_code icode = code_for_pred_narrow_scalar (,
mode);
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
- DONE;
-}
- [(set_attr "t
