Re: Re: [PATCH V4] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
OK, I will send patch v5.
--
Li Xu
>Ok. Understand.
>
>Could you add wrapper "maybe_require_vxrm_p" and "maybe_require_frm_p" ?
>
>static bool
>maybe_require_frm_p
>return instance.base == bases::vfwredusum || instance.base == bases::vfwredosum
>+ || instance.base == bases::vfadd || instance.base == bases::vfwsub
>+ || instance.base == bases::vfwnmsac || instance.base == bases::vfwnmacc
>+ || instance.base == bases::vfwmul || instance.base == bases::vfcvt_x
>+ || instance.base == bases::vfcvt_f || instance.base == bases::vfcvt_xu
>+ || instance.base == bases::vfwmsac || instance.base == bases::vfwmacc
>+ || instance.base == bases::vfwcvt_x || instance.base == bases::vfwadd
>+ || instance.base == bases::vfsub || instance.base == bases::vfsqrt
>+ || instance.base == bases::vfredusum || instance.base == bases::vfrsub
>+ || instance.base == bases::vfredosum || instance.base == bases::vfrec7
>+ || instance.base == bases::vfrdiv || instance.base == bases::vfnmsub
>+ || instance.base == bases::vfnmsac || instance.base == bases::vfnmadd
>+ || instance.base == bases::vfnmacc || instance.base == bases::vfncvt_f
>+ || instance.base == bases::vfncvt_x || instance.base == bases::vfncvt_xu
>+ || instance.base == bases::vfmul || instance.base == bases::vfmsub
>+ || instance.base == bases::vfmsac || instance.base == bases::vfmadd
>+ || instance.base == bases::vfmacc || instance.base == bases::vfdiv
>+ || instance.base == bases::vfwcvt_xu
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-10-30 18:04
>To: juzhe.zhong; gcc-patches
>CC: kito.cheng; palmer
>Subject: Re: Re: [PATCH V4] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for
>RVV intrinsic
>
>
>
>--
>
>
>
>Li Xu
>
>
>
>>Thanks.
>
>
>
>>
>
>
>
>>I like this 'HASH' solution which is much more reasonable to me.
>
>
>
>>
>
>
>
>>Some comments here:
>
>
>
>>
>
>
>
>>+bool
>
>
>
>>+has_vxrm_or_frm_p (function_instance , const vec
>>)
>
>
>
>>+{
>
>
>
>>+ /* Vector fixed-point arithmetic instructions requiring argument vxrm.
>
>
>
>>+ For example: vuint32m4_t __riscv_vaaddu(vuint32m4_t vs2, vuint32m4_t
>>vs1,
>
>
>
>>+ unsigned int vxrm, size_t vl);
>
>
>
>>+ The user calls vaaddu intrinsic in the form of __riscv_vaaddu(vs2, vs1,
>>2,
>
>
>
>>+ vl). The compiler recognizes that the parameter vxrm is a signed int,
>>which
>
>
>
>>+ is inconsistent with the parameter unsigned int vxrm declared by
>>intrinsic,
>
>
>
>>+ so the parameter vxrm is converted to an unsigned int type in order to
>>get
>
>
>
>>+ correct hash value. */
>
>
>
>>+ if (instance.base == bases::vaadd || instance.base == bases::vaaddu
>
>
>
>>+ || instance.base == bases::vasub || instance.base == bases::vasubu
>
>
>
>>+ || instance.base == bases::vssrl || instance.base == bases::vssra
>
>
>
>>+ || instance.base == bases::vsmul || instance.base == bases::vnclipu
>
>
>
>>+ || instance.base == bases::vnclip)
>
>
>
>>+ return true;
>
>
>
>>+
>
>
>
>>+ /* Vector Floating-Point Instructions requiring argument frm. */
>
>
>
>>+ if (instance.base == bases::vfwredusum || instance.base ==
>>bases::vfwredosum
>
>
>
>>+ || instance.base == bases::vfadd || instance.base == bases::vfwsub
>
>
>
>>+ || instance.base == bases::vfwnmsac || instance.base == bases::vfwnmacc
>
>
>
>>+ || instance.base == bases::vfwmul || instance.base == bases::vfcvt_x
>
>
>
>>+ || instance.base == bases::vfcvt_f || instance.base == bases::vfcvt_xu
>
>
>
>>+ || instance.base == bases::vfwmsac || instance.base == bases::vfwmacc
>
>
>
>>+
Re: Re: [PATCH V4] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
--
Li Xu
>Thanks.
>
>I like this 'HASH' solution which is much more reasonable to me.
>
>Some comments here:
>
>+bool
>+has_vxrm_or_frm_p (function_instance , const vec
>)
>+{
>+ /* Vector fixed-point arithmetic instructions requiring argument vxrm.
>+ For example: vuint32m4_t __riscv_vaaddu(vuint32m4_t vs2, vuint32m4_t vs1,
>+ unsigned int vxrm, size_t vl);
>+ The user calls vaaddu intrinsic in the form of __riscv_vaaddu(vs2, vs1,
>2,
>+ vl). The compiler recognizes that the parameter vxrm is a signed int,
>which
>+ is inconsistent with the parameter unsigned int vxrm declared by
>intrinsic,
>+ so the parameter vxrm is converted to an unsigned int type in order to
>get
>+ correct hash value. */
>+ if (instance.base == bases::vaadd || instance.base == bases::vaaddu
>+ || instance.base == bases::vasub || instance.base == bases::vasubu
>+ || instance.base == bases::vssrl || instance.base == bases::vssra
>+ || instance.base == bases::vsmul || instance.base == bases::vnclipu
>+ || instance.base == bases::vnclip)
>+ return true;
>+
>+ /* Vector Floating-Point Instructions requiring argument frm. */
>+ if (instance.base == bases::vfwredusum || instance.base == bases::vfwredosum
>+ || instance.base == bases::vfadd || instance.base == bases::vfwsub
>+ || instance.base == bases::vfwnmsac || instance.base == bases::vfwnmacc
>+ || instance.base == bases::vfwmul || instance.base == bases::vfcvt_x
>+ || instance.base == bases::vfcvt_f || instance.base == bases::vfcvt_xu
>+ || instance.base == bases::vfwmsac || instance.base == bases::vfwmacc
>+ || instance.base == bases::vfwcvt_x || instance.base == bases::vfwadd
>+ || instance.base == bases::vfsub || instance.base == bases::vfsqrt
>+ || instance.base == bases::vfredusum || instance.base == bases::vfrsub
>+ || instance.base == bases::vfredosum || instance.base == bases::vfrec7
>+ || instance.base == bases::vfrdiv || instance.base == bases::vfnmsub
>+ || instance.base == bases::vfnmsac || instance.base == bases::vfnmadd
>+ || instance.base == bases::vfnmacc || instance.base == bases::vfncvt_f
>+ || instance.base == bases::vfncvt_x || instance.base == bases::vfncvt_xu
>+ || instance.base == bases::vfmul || instance.base == bases::vfmsub
>+ || instance.base == bases::vfmsac || instance.base == bases::vfmadd
>+ || instance.base == bases::vfmacc || instance.base == bases::vfdiv
>+ || instance.base == bases::vfwcvt_xu)
>+ {
>+ /* DEF_RVV_FUNCTION (vfadd, alu, full_preds, f_vvv_ops)
>+ DEF_RVV_FUNCTION (vfadd_frm, alu_frm, full_preds, f_vvv_ops)
>+ Taking vfadd as an example, theoretically we can add base or shape to
>+ the hash value to distinguish whether the frm parameter is required.
>+ vfloat32m1_t __riscv_vfadd(vfloat32m1_t vs2, float32_t rs1, size_t vl);
>+ vfloat32m1_t __riscv_vfadd(vfloat32m1_t vs2, vfloat32m1_t vs1, unsigned
>+ int frm, size_t vl);
>+
>+ However, the current registration mechanism of overloaded intinsic for
>+ gcc limits the intrinsic obtained by entering the hook to always be
>+ vfadd, not vfadd_frm. Therefore, the correct hash value cannot be
>+ obtained through the parameter list and overload name, base or shape.
>+ ++---+---+
>+ | index | name | kind |
>+ ++---+---+
>+ | 124733 | __riscv_vfadd | Overloaded | <- Hook fun
>code
>+ ++---+---+
>+ | 124735 | __riscv_vfadd_vv_f32m1 | Non-overloaded |
>+ ++---+---+
>+ | 124737 | __riscv_vfadd | Placeholder |
>+ ++---+---+
>+ | ... |
>+ ++---+---+
>+ | ... |
>+ ++---+---+
>+ | 125739 | __riscv_vfadd | Overloaded |
>+ ++---+---+
>+ | 125741 | __riscv_vfadd_vv_f32m1_rm | Non-overloaded |
>+ ++---+---+
>+ | 125743 | __riscv_vfadd | Placeholder |
>+ ++---+---+
>+
>+ Therefore, the hash value cannot be added with base or shape, and needs
