Re: Re: [PATCH v2] RISC-V: Update crypto vector ISA info with latest spec
Committed! Thanks Kito.
BR,
Fei
On 2023-12-04 15:01 Kito Cheng wrote:
>
>LGTM again :)
>
>On Mon, Dec 4, 2023 at 2:44 PM Feng Wang wrote:
>>
>> Rebase and resend this patch due to it was not added into patchwork
>> before. Kito had already reviewed it. Please refer to
>> https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg327499.html
>>
>> This patch add the Zvkb subset of crypto vector extension. The
>> corresponding test cases have aslo been modified.
>>
>> gcc/ChangeLog:
>>
>> * common/config/riscv/riscv-common.cc: Add zvkb ISA info.
>> * config/riscv/riscv.opt: Add Mask(ZVKB)
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/zvkn-1.c: Replace zvbb with zvkb.
>> * gcc.target/riscv/zvkn.c: Ditto.
>> * gcc.target/riscv/zvknc-1.c:Ditto.
>> * gcc.target/riscv/zvknc-2.c:Ditto.
>> * gcc.target/riscv/zvknc.c: Ditto.
>> * gcc.target/riscv/zvkng-1.c:Ditto.
>> * gcc.target/riscv/zvkng-2.c:Ditto.
>> * gcc.target/riscv/zvkng.c: Ditto.
>> * gcc.target/riscv/zvks-1.c: Ditto.
>> * gcc.target/riscv/zvks.c: Ditto.
>> * gcc.target/riscv/zvksc-1.c:Ditto.
>> * gcc.target/riscv/zvksc-2.c:Ditto.
>> * gcc.target/riscv/zvksc.c: Ditto.
>> * gcc.target/riscv/zvksg-1.c:Ditto.
>> * gcc.target/riscv/zvksg-2.c:Ditto.
>> * gcc.target/riscv/zvksg.c: Ditto.
>> ---
>> gcc/common/config/riscv/riscv-common.cc | 6 --
>> gcc/config/riscv/riscv.opt | 2 ++
>> gcc/testsuite/gcc.target/riscv/zvkn-1.c | 8
>> gcc/testsuite/gcc.target/riscv/zvkn.c | 4 ++--
>> gcc/testsuite/gcc.target/riscv/zvknc-1.c | 8
>> gcc/testsuite/gcc.target/riscv/zvknc-2.c | 4 ++--
>> gcc/testsuite/gcc.target/riscv/zvknc.c | 4 ++--
>> gcc/testsuite/gcc.target/riscv/zvkng-1.c | 8
>> gcc/testsuite/gcc.target/riscv/zvkng-2.c | 4 ++--
>> gcc/testsuite/gcc.target/riscv/zvkng.c | 4 ++--
>> gcc/testsuite/gcc.target/riscv/zvks-1.c | 8
>> gcc/testsuite/gcc.target/riscv/zvks.c | 4 ++--
>> gcc/testsuite/gcc.target/riscv/zvksc-1.c | 8
>> gcc/testsuite/gcc.target/riscv/zvksc-2.c | 4 ++--
>> gcc/testsuite/gcc.target/riscv/zvksc.c | 4 ++--
>> gcc/testsuite/gcc.target/riscv/zvksg-1.c | 8
>> gcc/testsuite/gcc.target/riscv/zvksg-2.c | 4 ++--
>> gcc/testsuite/gcc.target/riscv/zvksg.c | 4 ++--
>> 18 files changed, 50 insertions(+), 46 deletions(-)
>>
>> diff --git a/gcc/common/config/riscv/riscv-common.cc
>> b/gcc/common/config/riscv/riscv-common.cc
>> index ded85b4c578..6c210412515 100644
>> --- a/gcc/common/config/riscv/riscv-common.cc
>> +++ b/gcc/common/config/riscv/riscv-common.cc
>> @@ -106,7 +106,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>>
>> {"zvkn", "zvkned"},
>> {"zvkn", "zvknhb"},
>> - {"zvkn", "zvbb"},
>> + {"zvkn", "zvkb"},
>> {"zvkn", "zvkt"},
>> {"zvknc", "zvkn"},
>> {"zvknc", "zvbc"},
>> @@ -114,7 +114,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>> {"zvkng", "zvkg"},
>> {"zvks", "zvksed"},
>> {"zvks", "zvksh"},
>> - {"zvks", "zvbb"},
>> + {"zvks", "zvkb"},
>> {"zvks", "zvkt"},
>> {"zvksc", "zvks"},
>> {"zvksc", "zvbc"},
>> @@ -253,6 +253,7 @@ static const struct riscv_ext_version
>> riscv_ext_version_table[] =
>>
>> {"zvbb", ISA_SPEC_CLASS_NONE, 1, 0},
>> {"zvbc", ISA_SPEC_CLASS_NONE, 1, 0},
>> + {"zvkb", ISA_SPEC_CLASS_NONE, 1, 0},
>> {"zvkg", ISA_SPEC_CLASS_NONE, 1, 0},
>> {"zvkned", ISA_SPEC_CLASS_NONE, 1, 0},
>> {"zvknha", ISA_SPEC_CLASS_NONE, 1, 0},
>> @@ -1624,6 +1625,7 @@ static const riscv_ext_flag_table_t
>> riscv_ext_flag_table[] =
>>
>> {"zvbb", &gcc_options::x_riscv_zvb_subext, MASK_ZVBB},
>> {"zvbc", &gcc_options::x_riscv_zvb_subext, MASK_ZVBC},
>> + {"zvkb", &gcc_options::x_riscv_zvb_subext, MASK_ZVKB},
>> {"zvkg", &gcc_options::x_riscv_zvk_subext, MASK_ZVKG},
>> {"zvkned", &gcc_options::x_riscv_zvk_subext, MASK_ZVKNED},
>> {"zvknha", &gcc_options::x_riscv_zvk_subext, MASK_ZVKNHA},
>> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
>> index 0c6517bdc8b..78186fff6c5 100644
>> --- a/gcc/config/riscv/riscv.opt
>> +++ b/gcc/config/riscv/riscv.opt
>> @@ -319,6 +319,8 @@ Mask(ZVBB) Var(riscv_zvb_subext)
>>
>> Mask(ZVBC) Var(riscv_zvb_subext)
>>
>> +Mask(ZVKB) Var(riscv_zvb_subext)
>> +
>> TargetVariable
>> int riscv_zvk_subext
>>
>> diff --git a/gcc/testsuite/gcc.target/riscv/zvkn-1.c
>> b/gcc/testsuite/gcc.target/riscv/zvkn-1.c
>> index 23b255b4779..069a8f66c92 100644
>> --- a/gcc/testsuite/gcc.target/riscv/zvkn-1.c
>> +++ b/gcc/testsuite/gcc.target/riscv/zvkn-1.c
>> @@ -1,6 +1,6 @@
>> /* { dg-do compile } */
>> -/* { dg-options "-march=rv64gc_zvkned_zvknhb_zvbb_zvkt" { target { rv64 } }
>> } */
>> -/* { dg-options "-march=rv32gc_zvkned_zvknhb_zvbb_zvkt" { target { rv32 } }
>> } */
>> +/* { dg-options "-march=rv64gc_zvkned_zvknhb_zvkb_zvkt" {
Re: [PATCH v2] RISC-V: Update crypto vector ISA info with latest spec
LGTM again :)
On Mon, Dec 4, 2023 at 2:44 PM Feng Wang wrote:
>
> Rebase and resend this patch due to it was not added into patchwork
> before. Kito had already reviewed it. Please refer to
> https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg327499.html
>
> This patch add the Zvkb subset of crypto vector extension. The
> corresponding test cases have aslo been modified.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc: Add zvkb ISA info.
> * config/riscv/riscv.opt: Add Mask(ZVKB)
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zvkn-1.c: Replace zvbb with zvkb.
> * gcc.target/riscv/zvkn.c: Ditto.
> * gcc.target/riscv/zvknc-1.c:Ditto.
> * gcc.target/riscv/zvknc-2.c:Ditto.
> * gcc.target/riscv/zvknc.c: Ditto.
> * gcc.target/riscv/zvkng-1.c:Ditto.
> * gcc.target/riscv/zvkng-2.c:Ditto.
> * gcc.target/riscv/zvkng.c: Ditto.
> * gcc.target/riscv/zvks-1.c: Ditto.
> * gcc.target/riscv/zvks.c: Ditto.
> * gcc.target/riscv/zvksc-1.c:Ditto.
> * gcc.target/riscv/zvksc-2.c:Ditto.
> * gcc.target/riscv/zvksc.c: Ditto.
> * gcc.target/riscv/zvksg-1.c:Ditto.
> * gcc.target/riscv/zvksg-2.c:Ditto.
> * gcc.target/riscv/zvksg.c: Ditto.
> ---
> gcc/common/config/riscv/riscv-common.cc | 6 --
> gcc/config/riscv/riscv.opt | 2 ++
> gcc/testsuite/gcc.target/riscv/zvkn-1.c | 8
> gcc/testsuite/gcc.target/riscv/zvkn.c| 4 ++--
> gcc/testsuite/gcc.target/riscv/zvknc-1.c | 8
> gcc/testsuite/gcc.target/riscv/zvknc-2.c | 4 ++--
> gcc/testsuite/gcc.target/riscv/zvknc.c | 4 ++--
> gcc/testsuite/gcc.target/riscv/zvkng-1.c | 8
> gcc/testsuite/gcc.target/riscv/zvkng-2.c | 4 ++--
> gcc/testsuite/gcc.target/riscv/zvkng.c | 4 ++--
> gcc/testsuite/gcc.target/riscv/zvks-1.c | 8
> gcc/testsuite/gcc.target/riscv/zvks.c| 4 ++--
> gcc/testsuite/gcc.target/riscv/zvksc-1.c | 8
> gcc/testsuite/gcc.target/riscv/zvksc-2.c | 4 ++--
> gcc/testsuite/gcc.target/riscv/zvksc.c | 4 ++--
> gcc/testsuite/gcc.target/riscv/zvksg-1.c | 8
> gcc/testsuite/gcc.target/riscv/zvksg-2.c | 4 ++--
> gcc/testsuite/gcc.target/riscv/zvksg.c | 4 ++--
> 18 files changed, 50 insertions(+), 46 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc
> b/gcc/common/config/riscv/riscv-common.cc
> index ded85b4c578..6c210412515 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -106,7 +106,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>
>{"zvkn", "zvkned"},
>{"zvkn", "zvknhb"},
> - {"zvkn", "zvbb"},
> + {"zvkn", "zvkb"},
>{"zvkn", "zvkt"},
>{"zvknc", "zvkn"},
>{"zvknc", "zvbc"},
> @@ -114,7 +114,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>{"zvkng", "zvkg"},
>{"zvks", "zvksed"},
>{"zvks", "zvksh"},
> - {"zvks", "zvbb"},
> + {"zvks", "zvkb"},
>{"zvks", "zvkt"},
>{"zvksc", "zvks"},
>{"zvksc", "zvbc"},
> @@ -253,6 +253,7 @@ static const struct riscv_ext_version
> riscv_ext_version_table[] =
>
>{"zvbb", ISA_SPEC_CLASS_NONE, 1, 0},
>{"zvbc", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"zvkb", ISA_SPEC_CLASS_NONE, 1, 0},
>{"zvkg", ISA_SPEC_CLASS_NONE, 1, 0},
>{"zvkned", ISA_SPEC_CLASS_NONE, 1, 0},
>{"zvknha", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1624,6 +1625,7 @@ static const riscv_ext_flag_table_t
> riscv_ext_flag_table[] =
>
>{"zvbb", &gcc_options::x_riscv_zvb_subext, MASK_ZVBB},
>{"zvbc", &gcc_options::x_riscv_zvb_subext, MASK_ZVBC},
> + {"zvkb", &gcc_options::x_riscv_zvb_subext, MASK_ZVKB},
>{"zvkg", &gcc_options::x_riscv_zvk_subext, MASK_ZVKG},
>{"zvkned", &gcc_options::x_riscv_zvk_subext, MASK_ZVKNED},
>{"zvknha", &gcc_options::x_riscv_zvk_subext, MASK_ZVKNHA},
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 0c6517bdc8b..78186fff6c5 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -319,6 +319,8 @@ Mask(ZVBB) Var(riscv_zvb_subext)
>
> Mask(ZVBC) Var(riscv_zvb_subext)
>
> +Mask(ZVKB) Var(riscv_zvb_subext)
> +
> TargetVariable
> int riscv_zvk_subext
>
> diff --git a/gcc/testsuite/gcc.target/riscv/zvkn-1.c
> b/gcc/testsuite/gcc.target/riscv/zvkn-1.c
> index 23b255b4779..069a8f66c92 100644
> --- a/gcc/testsuite/gcc.target/riscv/zvkn-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/zvkn-1.c
> @@ -1,6 +1,6 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zvkned_zvknhb_zvbb_zvkt" { target { rv64 } }
> } */
> -/* { dg-options "-march=rv32gc_zvkned_zvknhb_zvbb_zvkt" { target { rv32 } }
> } */
> +/* { dg-options "-march=rv64gc_zvkned_zvknhb_zvkb_zvkt" { target { rv64 } }
> } */
> +/* { dg-options "-march=rv32gc_zvkned_zvknhb_zvkb_zvkt" { target { rv32 } }
> } */
>
> #ifndef __riscv_zvkn
> #error "Feature macro for `Zvkn' not defined"
> @@ -14,
