Re: [RFC V2] RISC-V : Support rv64 ilp32
On Mon, May 22, 2023 at 10:51 AM Guo Ren wrote: > > On Fri, May 19, 2023 at 3:35 PM Kito Cheng wrote: > > > > I am concern about we didn't define POINTERS_EXTEND_UNSIGNED here, and > > also concern about the code model stuffs, I know currently Guo-Ren's > > implementation is rely on some MMU trick, but I am not sure does it > > also applicable on embedded applications. > There are two ways: > - Limit address < 2GB. (Fortunately, most MCUs have a limit on their > address of less than 2GB.) > - The zjpm liked hardware extension could mask the highest 32 bits of the > address. I guess your question is: Shall we start the work of the GCC's POINTERS_EXTEND_UNSIGNED? If the SoC's start address of dram > 2GB, we need the GCC's POINTERS_EXTEND_UNSIGNED. > > > > > > > > diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h > > > index b9557a75dc7..4f33c88ef6e 100644 > > > --- a/gcc/config/riscv/linux.h > > > +++ b/gcc/config/riscv/linux.h > > > @@ -58,7 +58,7 @@ along with GCC; see the file COPYING3. If not see > > >"%{mabi=ilp32:_ilp32}" > > > > > > #define LINK_SPEC "\ > > > --melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \ > > > +-melf" ABI_LEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \ > > > %{mno-relax:--no-relax} \ > > > %{mbig-endian:-EB} \ > > > %{mlittle-endian:-EL} \ > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > > index 5f44f6dc5c9..09ab940447d 100644 > > > --- a/gcc/config/riscv/riscv.cc > > > +++ b/gcc/config/riscv/riscv.cc > > > @@ -6291,10 +6291,6 @@ riscv_option_override (void) > > >&& riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E) > > > error ("z*inx requires ABI ilp32, ilp32e or lp64"); > > > > > > - /* We do not yet support ILP32 on RV64. */ > > > - if (BITS_PER_WORD != POINTER_SIZE) > > > -error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); > > > > It seems to also make -march=rv32g -mabi=lp64 become acceptable? > > > > > > > > > -- > Best Regards > Guo Ren -- Best Regards Guo Ren
Re: [RFC V2] RISC-V : Support rv64 ilp32
On Fri, May 19, 2023 at 3:35 PM Kito Cheng wrote: > > I am concern about we didn't define POINTERS_EXTEND_UNSIGNED here, and > also concern about the code model stuffs, I know currently Guo-Ren's > implementation is rely on some MMU trick, but I am not sure does it > also applicable on embedded applications. There are two ways: - Limit address < 2GB. (Fortunately, most MCUs have a limit on their address of less than 2GB.) - The zjpm liked hardware extension could mask highest 32 bits of the address. > > > > diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h > > index b9557a75dc7..4f33c88ef6e 100644 > > --- a/gcc/config/riscv/linux.h > > +++ b/gcc/config/riscv/linux.h > > @@ -58,7 +58,7 @@ along with GCC; see the file COPYING3. If not see > >"%{mabi=ilp32:_ilp32}" > > > > #define LINK_SPEC "\ > > --melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \ > > +-melf" ABI_LEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \ > > %{mno-relax:--no-relax} \ > > %{mbig-endian:-EB} \ > > %{mlittle-endian:-EL} \ > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > index 5f44f6dc5c9..09ab940447d 100644 > > --- a/gcc/config/riscv/riscv.cc > > +++ b/gcc/config/riscv/riscv.cc > > @@ -6291,10 +6291,6 @@ riscv_option_override (void) > >&& riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E) > > error ("z*inx requires ABI ilp32, ilp32e or lp64"); > > > > - /* We do not yet support ILP32 on RV64. */ > > - if (BITS_PER_WORD != POINTER_SIZE) > > -error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); > > It seems to also make -march=rv32g -mabi=lp64 become acceptable? > > > -- Best Regards Guo Ren
Re: [RFC V2] RISC-V : Support rv64 ilp32
Thanks for your advice, Kito. 在 2023/5/19 15:35, Kito Cheng 写道: I am concern about we didn't define POINTERS_EXTEND_UNSIGNED here, and also concern about the code model stuffs, I know currently Guo-Ren's implementation is rely on some MMU trick, but I am not sure does it also applicable on embedded applications. OK,we will verify this in the future. - /* We do not yet support ILP32 on RV64. */ - if (BITS_PER_WORD != POINTER_SIZE) -error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); It seems to also make -march=rv32g -mabi=lp64 become acceptable? Oh, I was negligent and will make improvements in the next patch. Best Regards Liao Shihua
Re: [RFC V2] RISC-V : Support rv64 ilp32
I am concern about we didn't define POINTERS_EXTEND_UNSIGNED here, and also concern about the code model stuffs, I know currently Guo-Ren's implementation is rely on some MMU trick, but I am not sure does it also applicable on embedded applications. > diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h > index b9557a75dc7..4f33c88ef6e 100644 > --- a/gcc/config/riscv/linux.h > +++ b/gcc/config/riscv/linux.h > @@ -58,7 +58,7 @@ along with GCC; see the file COPYING3. If not see >"%{mabi=ilp32:_ilp32}" > > #define LINK_SPEC "\ > --melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \ > +-melf" ABI_LEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \ > %{mno-relax:--no-relax} \ > %{mbig-endian:-EB} \ > %{mlittle-endian:-EL} \ > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 5f44f6dc5c9..09ab940447d 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -6291,10 +6291,6 @@ riscv_option_override (void) >&& riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E) > error ("z*inx requires ABI ilp32, ilp32e or lp64"); > > - /* We do not yet support ILP32 on RV64. */ > - if (BITS_PER_WORD != POINTER_SIZE) > -error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); It seems to also make -march=rv32g -mabi=lp64 become acceptable? >