On 02/24/2017 12:20 PM, Claudiu Zissulescu wrote:
Hi,
Indeed, we are not up to speed regarding updating and cleaning the
documentation.
On 12/02/2017 05:18, Sandra Loosemore wrote:
I noticed a bunch of copy-editing issues in the "ARC Options" section of
invoke.texi. I'm willing to take a stab at fixing them, but I need some
technical assistance since I'm not familiar with the details of this
architecture myself.
* In e.g. "Compile for ARC 600 cpu with norm instruction enabled." is
"norm" literally the name of an instruction, GCC implementor jargon, or
a term that is used and capitalized like that in the processor
documentation? Ditto for "mul32x16", "mul64", "LR", "SR", "mpy", "mac",
"mulu64", "swap", "DIV/REM", "MPY", "MPYU", "MPYW", "MPYUW", "MPY_S",
"MPYM", "MPYMU". For other targets, literal names of instructions are
usually marked up with @code{}, and it would be good to be consistent
All those names are additional instructions support which are not
available in the base ARC configurations. Indeed, we should be
consistent here.
* In "FPX: Generate Double Precision FPX instructions", is "Double
Precision FPX" a proper name literally capitalized like that, or is this
a mistake for "double-precision FPX instructions"? Likewise for "Single
Precision FPX"?
It is a mistake, we should use lower letters.
* In e.g. the discussion of fpuda_div, is "simple precision" a typo for
"single precision"? Likewise is "multiple and add" a typo for "multiply
and add"?
Here are typos.
Thanks for the additional clarifications.
I've committed the attached patch, which has a few more cleanups beyond
the version I posted a couple weeks ago. It's not perfect, but I think
it's at least an incremental improvement overall.
-Sandra
2017-02-28 Sandra Loosemore
gcc/
* doc/invoke.texi (ARC Options): Copy-edit to fix punctuation,
markup, and similar issues. Remove @opindex entries for things
that aren't options. Add missing -mmpy-option entries.
Index: gcc/doc/invoke.texi
===
--- gcc/doc/invoke.texi (revision 245794)
+++ gcc/doc/invoke.texi (working copy)
@@ -14248,70 +14248,58 @@ Compile for ARC EM.
Compile for ARC HS.
@item em
-@opindex em
-Compile for ARC EM cpu with no hardware extension.
+Compile for ARC EM CPU with no hardware extensions.
@item em4
-@opindex em4
-Compile for ARC EM4 cpu.
+Compile for ARC EM4 CPU.
@item em4_dmips
-@opindex em4_dmips
-Compile for ARC EM4 DMIPS cpu.
+Compile for ARC EM4 DMIPS CPU.
@item em4_fpus
-@opindex em4_fpus
-Compile for ARC EM4 DMIPS cpu with single precision floating point
+Compile for ARC EM4 DMIPS CPU with the single-precision floating-point
extension.
@item em4_fpuda
-@opindex em4_fpuda
-Compile for ARC EM4 DMIPS cpu with single precision floating point and
-double assists instructions.
+Compile for ARC EM4 DMIPS CPU with single-precision floating-point and
+double assist instructions.
@item hs
-@opindex hs
-Compile for ARC HS cpu with no hardware extension, except the atomic
+Compile for ARC HS CPU with no hardware extensions except the atomic
instructions.
@item hs34
-@opindex hs34
-Compile for ARC HS34 cpu.
+Compile for ARC HS34 CPU.
@item hs38
-@opindex hs38
-Compile for ARC HS38 cpu.
+Compile for ARC HS38 CPU.
@item hs38_linux
-@opindex hs38_linux
-Compile for ARC HS38 cpu with all hardware extensions on.
+Compile for ARC HS38 CPU with all hardware extensions on.
@item arc600_norm
-@opindex arc600_norm
-Compile for ARC 600 cpu with norm instruction enabled.
+Compile for ARC 600 CPU with @code{norm} instructions enabled.
@item arc600_mul32x16
-@opindex arc600_mul32x16
-Compile for ARC 600 cpu with norm and mul32x16 instructions enabled.
+Compile for ARC 600 CPU with @code{norm} and 32x16-bit multiply
+instructions enabled.
@item arc600_mul64
-@opindex arc600_mul64
-Compile for ARC 600 cpu with norm and mul64 instructions enabled.
+Compile for ARC 600 CPU with @code{norm} and @code{mul64}-family
+instructions enabled.
@item arc601_norm
-@opindex arc601_norm
-Compile for ARC 601 cpu with norm instruction enabled.
+Compile for ARC 601 CPU with @code{norm} instructions enabled.
@item arc601_mul32x16
-@opindex arc601_mul32x16
-Compile for ARC 601 cpu with norm and mul32x16 instructions enabled.
+Compile for ARC 601 CPU with @code{norm} and 32x16-bit multiply
+instructions enabled.
@item arc601_mul64
-@opindex arc601_mul64
-Compile for ARC 601 cpu with norm and mul64 instructions enabled.
+Compile for ARC 601 CPU with @code{norm} and @code{mul64}-family
+instructions enabled.
@item nps400
-@opindex nps400
Compile for ARC 700 on NPS400 chip.
@end table
@@ -14320,52 +14308,54 @@ Compile for ARC 700 on NPS400 chip.
@opindex mdpfp
@itemx -mdpfp-compact
@opindex mdpfp-compact
-FPX: Generate Double Precision FPX instructions, tuned for the compact
+Generate double-precision FPX instructions, tuned for the