commited, thanks kito and juzhe.
-------------- Li Xu >I think it's not make too much sense to back port GCC14's change to >GCC 13, removing phase 6 optimization is reasonable to me, so LGTM :) > >On Mon, Sep 18, 2023 at 2:44 PM juzhe.zh...@rivai.ai ><juzhe.zh...@rivai.ai> wrote: >> >> Thanks for fixing it. >> I am ok remove phase 6 optimization which has many latent bugs (in GCC 14 >> kito has refactored it) there. >> But I think we need kito's more comments about that. >> >> >> >> juzhe.zh...@rivai.ai >> >> From: Li Xu >> Date: 2023-09-18 12:19 >> To: gcc-patches >> CC: kito.cheng; palmer; juzhe.zhong; xuli >> Subject: [PATCH] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412] >> From: xuli <xu...@eswincomputing.com> >> >> vsetvl pass has been refactored in gcc14, and the optimization >> is more reasonable than releases/gcc-13. This problem does not >> exist in gcc14. >> >> Phase 6 of gcc13 is an optimization patch. Due to lack of consideration, >> there will be some hidden bugs, so we decided to remove phase 6. >> Although the generated code will be redundant, the program is correct. >> >> PR target/111412 >> >> gcc/ChangeLog: >> >> * config/riscv/riscv-vsetvl.cc (vector_infos_manager::release): >>Remove. >> (pass_vsetvl::refine_vsetvls): Ditto. >> (pass_vsetvl::cleanup_vsetvls): Ditto. >> (pass_vsetvl::propagate_avl): Ditto. >> (pass_vsetvl::lazy_vsetvl): Ditto. >> * config/riscv/riscv-vsetvl.h: Ditto. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Adjust case. >> * gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Ditto. >> * gcc.target/riscv/rvv/base/pr111412.c: New test. >> --- >> gcc/config/riscv/riscv-vsetvl.cc | 153 +----------------- >> gcc/config/riscv/riscv-vsetvl.h | 2 - >> .../gcc.target/riscv/rvv/base/pr111412.c | 41 +++++ >> .../riscv/rvv/vsetvl/avl_single-79.c | 4 +- >> .../riscv/rvv/vsetvl/avl_single-80.c | 4 +- >> .../riscv/rvv/vsetvl/avl_single-86.c | 4 +- >> .../riscv/rvv/vsetvl/avl_single-87.c | 4 +- >> .../riscv/rvv/vsetvl/avl_single-88.c | 4 +- >> .../riscv/rvv/vsetvl/avl_single-89.c | 4 +- >> .../riscv/rvv/vsetvl/avl_single-90.c | 4 +- >> .../riscv/rvv/vsetvl/vlmax_back_prop-25.c | 10 +- >> .../riscv/rvv/vsetvl/vlmax_back_prop-26.c | 10 +- >> .../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c | 6 +- >> .../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c | 2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c | 2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-5.c | 2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-6.c | 2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-7.c | 2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-8.c | 2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c | 4 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c | 4 +- >> 21 files changed, 80 insertions(+), 190 deletions(-) >> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111412.c >> >> diff --git a/gcc/config/riscv/riscv-vsetvl.cc >> b/gcc/config/riscv/riscv-vsetvl.cc >> index 0cf4bc818e2..9dca2ce709d 100644 >> --- a/gcc/config/riscv/riscv-vsetvl.cc >> +++ b/gcc/config/riscv/riscv-vsetvl.cc >> @@ -2494,8 +2494,6 @@ vector_infos_manager::release (void) >> if (!vector_exprs.is_empty ()) >> vector_exprs.release (); >> - gcc_assert (to_refine_vsetvls.is_empty ()); >> - gcc_assert (to_delete_vsetvls.is_empty ()); >> if (optimize > 0) >> free_bitmap_vectors (); >> } >> @@ -2702,9 +2700,6 @@ private: >> /* Phase 5. */ >> void cleanup_insns (void) const; >> - /* Phase 6. */ >> - void propagate_avl (void) const; >> - >> void init (void); >> void done (void); >> void compute_probabilities (void); >> @@ -3823,10 +3818,8 @@ pass_vsetvl::refine_vsetvls (void) const >> /* We can't refine user vsetvl into vsetvl zero,zero since the dest >> will be used by the following instructions. */ >> if (vector_config_insn_p (rinsn)) >> - { >> - m_vector_manager->to_refine_vsetvls.add (rinsn); >> continue; >> - } >> + >> rinsn = PREV_INSN (rinsn); >> rtx new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, info, >>NULL_RTX); >> change_insn (rinsn, new_pat); >> @@ -3862,10 +3855,7 @@ pass_vsetvl::cleanup_vsetvls () >> /* We can't eliminate user vsetvl since the dest will be used >> * by the following instructions. */ >> if (vector_config_insn_p (insn->rtl ())) >> - { >> - m_vector_manager->to_delete_vsetvls.add (insn->rtl ()); >> - continue; >> - } >> + continue; >> gcc_assert (has_vtype_op (insn->rtl ())); >> rinsn = PREV_INSN (insn->rtl ()); >> @@ -4067,139 +4057,6 @@ pass_vsetvl::cleanup_insns (void) const >> } >> } >> -void >> -pass_vsetvl::propagate_avl (void) const >> -{ >> - /* Rebuild the RTL_SSA according to the new CFG generated by LCM. */ >> - /* Finalization of RTL_SSA. */ >> - free_dominance_info (CDI_DOMINATORS); >> - if (crtl->ssa->perform_pending_updates ()) >> - cleanup_cfg (0); >> - delete crtl->ssa; >> - crtl->ssa = nullptr; >> - /* Initialization of RTL_SSA. */ >> - calculate_dominance_info (CDI_DOMINATORS); >> - df_analyze (); >> - crtl->ssa = new function_info (cfun); >> - >> - hash_set<rtx_insn *> to_delete; >> - for (const bb_info *bb : crtl->ssa->bbs ()) >> - { >> - for (insn_info *insn : bb->real_nondebug_insns ()) >> - { >> - if (vsetvl_discard_result_insn_p (insn->rtl ())) >> - { >> - rtx avl = get_avl (insn->rtl ()); >> - if (!REG_P (avl)) >> - continue; >> - >> - set_info *set = find_access (insn->uses (), REGNO (avl))->def (); >> - insn_info *def_insn = extract_single_source (set); >> - if (!def_insn) >> - continue; >> - >> - /* Handle this case: >> - vsetvli a6,zero,e32,m1,ta,mu >> - li a5,4096 >> - add a7,a0,a5 >> - addi a7,a7,-96 >> - vsetvli t1,zero,e8,mf8,ta,ma >> - vle8.v v24,0(a7) >> - add a5,a3,a5 >> - addi a5,a5,-96 >> - vse8.v v24,0(a5) >> - vsetvli zero,a6,e32,m1,tu,ma >> - */ >> - if (vsetvl_insn_p (def_insn->rtl ())) >> - { >> - vl_vtype_info def_info = get_vl_vtype_info (def_insn); >> - vl_vtype_info info = get_vl_vtype_info (insn); >> - rtx avl = get_avl (def_insn->rtl ()); >> - rtx vl = get_vl (def_insn->rtl ()); >> - if (def_info.get_ratio () == info.get_ratio ()) >> - { >> - if (vlmax_avl_p (def_info.get_avl ())) >> - { >> - info.set_avl_info ( >> - avl_info (def_info.get_avl (), nullptr)); >> - rtx new_pat >> - = gen_vsetvl_pat (VSETVL_NORMAL, info, vl); >> - validate_change (insn->rtl (), >> - &PATTERN (insn->rtl ()), new_pat, >> - false); >> - continue; >> - } >> - if (def_info.has_avl_imm () || rtx_equal_p (avl, vl)) >> - { >> - info.set_avl_info (avl_info (avl, nullptr)); >> - emit_vsetvl_insn (VSETVL_DISCARD_RESULT, EMIT_AFTER, >> - info, NULL_RTX, insn->rtl ()); >> - if (set->single_nondebug_insn_use ()) >> - { >> - to_delete.add (insn->rtl ()); >> - to_delete.add (def_insn->rtl ()); >> - } >> - continue; >> - } >> - } >> - } >> - } >> - >> - /* Change vsetvl rd, rs1 --> vsevl zero, rs1, >> - if rd is not used by any nondebug instructions. >> - Even though this PASS runs after RA and it doesn't help for >> - reduce register pressure, it can help instructions scheduling >> - since we remove the dependencies. */ >> - if (vsetvl_insn_p (insn->rtl ())) >> - { >> - rtx vl = get_vl (insn->rtl ()); >> - rtx avl = get_avl (insn->rtl ()); >> - def_info *def = find_access (insn->defs (), REGNO (vl)); >> - set_info *set = safe_dyn_cast<set_info *> (def); >> - vector_insn_info info; >> - info.parse_insn (insn); >> - gcc_assert (set); >> - if (m_vector_manager->to_delete_vsetvls.contains (insn->rtl ())) >> - { >> - m_vector_manager->to_delete_vsetvls.remove (insn->rtl ()); >> - if (m_vector_manager->to_refine_vsetvls.contains ( >> - insn->rtl ())) >> - m_vector_manager->to_refine_vsetvls.remove (insn->rtl ()); >> - if (!set->has_nondebug_insn_uses ()) >> - { >> - to_delete.add (insn->rtl ()); >> - continue; >> - } >> - } >> - if (m_vector_manager->to_refine_vsetvls.contains (insn->rtl ())) >> - { >> - m_vector_manager->to_refine_vsetvls.remove (insn->rtl ()); >> - if (!set->has_nondebug_insn_uses ()) >> - { >> - rtx new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, >> - info, NULL_RTX); >> - change_insn (insn->rtl (), new_pat); >> - continue; >> - } >> - } >> - if (vlmax_avl_p (avl)) >> - continue; >> - rtx new_pat >> - = gen_vsetvl_pat (VSETVL_DISCARD_RESULT, info, NULL_RTX); >> - if (!set->has_nondebug_insn_uses ()) >> - { >> - validate_change (insn->rtl (), &PATTERN (insn->rtl ()), >> - new_pat, false); >> - continue; >> - } >> - } >> - } >> - } >> - >> - for (rtx_insn *rinsn : to_delete) >> - eliminate_insn (rinsn); >> -} >> - >> void >> pass_vsetvl::init (void) >> { >> @@ -4322,12 +4179,6 @@ pass_vsetvl::lazy_vsetvl (void) >> if (dump_file) >> fprintf (dump_file, "\nPhase 5: Cleanup AVL and VL operands\n"); >> cleanup_insns (); >> - >> - /* Phase 6 - Rebuild RTL_SSA to propagate AVL between vsetvls. */ >> - if (dump_file) >> - fprintf (dump_file, >> - "\nPhase 6: Rebuild RTL_SSA to propagate AVL between vsetvls\n"); >> - propagate_avl (); >> } >> /* Main entry point for this pass. */ >> diff --git a/gcc/config/riscv/riscv-vsetvl.h >> b/gcc/config/riscv/riscv-vsetvl.h >> index 4fe08cfc789..7fec5522227 100644 >> --- a/gcc/config/riscv/riscv-vsetvl.h >> +++ b/gcc/config/riscv/riscv-vsetvl.h >> @@ -418,8 +418,6 @@ public: >> auto_vec<vector_insn_info> vector_insn_infos; >> auto_vec<vector_block_info> vector_block_infos; >> auto_vec<vector_insn_info *> vector_exprs; >> - hash_set<rtx_insn *> to_refine_vsetvls; >> - hash_set<rtx_insn *> to_delete_vsetvls; >> struct edge_list *vector_edge_list; >> sbitmap *vector_kill; >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111412.c >> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111412.c >> new file mode 100644 >> index 00000000000..81cee30c961 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111412.c >> @@ -0,0 +1,41 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ >> + >> +#include "riscv_vector.h" >> + >> +typedef float float32_t; >> +void test (uint32_t blockSize1, float32_t *pDst, uint32_t blkCnt) >> +{ >> + float32_t sum = 0.0f; >> + uint32_t blockSize2 = blockSize1; >> + uint32_t count = 1; >> + vfloat32m1_t temp00m1; >> + >> + while (blockSize1 > 0) >> + { >> + uint32_t vblkCnt = count; >> + size_t l = __riscv_vsetvl_e32m1 (1); >> + temp00m1 = __riscv_vfmv_v_f_f32m1 (1, l); >> + for (; (l = __riscv_vsetvl_e32m8 (vblkCnt)) > 0; vblkCnt -= l); >> + sum += __riscv_vfmv_f_s_f32m1_f32 (temp00m1); >> + count++; >> + blockSize1--; >> + } >> + >> + while (blkCnt > 0) >> + { >> + size_t l = __riscv_vsetvl_e32m1 (blockSize1); >> + temp00m1 = __riscv_vfmv_v_f_f32m1 (0, l); >> + blkCnt--; >> + } >> + >> + while (blockSize2-- > 0) >> + { >> + size_t l = __riscv_vsetvl_e32m1 (1); >> + temp00m1 = __riscv_vfmv_v_f_f32m1 (0, l); >> + sum += __riscv_vfmv_f_s_f32m1_f32 (temp00m1); >> + *pDst++ = sum; >> + } >> +} >> + >> +/* { dg-final { scan-assembler-times >> {vsetivli\s+[a-x0-9]+,\s*1,\s*e32,\s*m1,\s*ta,\s*ma\s*vfmv\.v\.f\s+v[0-9]+,\s*[a-x0-9]+} >> 1 } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c >> index 344909ad322..429cc0652e4 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c >> @@ -18,5 +18,5 @@ void f (int8_t * restrict in, int8_t * restrict out, int >> n, int m, unsigned cond >> } >> } >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts >> "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } >> } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c >> index 0200d72c00a..4e5056d8d5f 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c >> @@ -18,5 +18,5 @@ void f (int8_t * restrict in, int8_t * restrict out, int >> n, int m, unsigned cond >> } >> } >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts >> "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } >> } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c >> index 48636f562f9..a5f4768bd81 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c >> @@ -24,6 +24,6 @@ float f1 (int8_t * restrict in, int8_t * restrict out, int >> n, int m, unsigned co >> return __riscv_vfmv_f_s_f32m1_f32 (v); >> } >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> /* { dg-final { scan-assembler-not {vsetivli} { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c >> index 5463cd86a31..132eeab9679 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c >> @@ -24,7 +24,7 @@ float f (int8_t * restrict in, int8_t * restrict out, int >> n, int m, unsigned con >> return __riscv_vfmv_f_s_f32m1_f32 (v); >> } >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> /* { dg-final { scan-assembler-times >> {vsetivli\s+zero,\s*3,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> /* { dg-final { scan-assembler-times {vsetivli} 2 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c >> index 5b64cfea8d3..30d012d388c 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c >> @@ -24,6 +24,6 @@ float f (int8_t * restrict in, int8_t * restrict out, int >> n, int m, unsigned con >> return __riscv_vfmv_f_s_f32m1_f32 (v); >> } >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> /* { dg-final { scan-assembler-not {vsetivli} { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c >> index a4ef350afc3..7a78217e60b 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c >> @@ -26,6 +26,6 @@ float f (int8_t * restrict in, int8_t * restrict out, int >> n, int m, unsigned con >> } >> /* { dg-final { scan-assembler-times >> {vsetivli\s+zero,\s*3,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> /* { dg-final { scan-assembler-times {vsetivli} 2 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c >> index 92fee67c541..439cbfe7627 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c >> @@ -25,6 +25,6 @@ float f2 (int8_t * restrict in, int8_t * restrict out, int >> n, int m, unsigned co >> return __riscv_vfmv_f_s_f32m1_f32 (v); >> } >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> /* { dg-final { scan-assembler-not {vsetivli} { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts >> "-funroll-loops" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c >> index c566f8a4751..ec08ef0121d 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c >> @@ -88,8 +88,8 @@ void f (void * restrict in, void * restrict out, int n, >> int cond) >> } >> } >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts >> "-g" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 5 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 6 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 4 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 19 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts >> "-g" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c >> index d0e75258188..fe5fd8eebda 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c >> @@ -80,8 +80,8 @@ void f (void * restrict in, void * restrict out, int n, >> int cond) >> } >> } >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts >> "-g" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 5 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 6 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target { >> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts >> "-funroll-loops" no-opts "-g" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 17 { target { no-opts "-O0" >> no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts >> "-g" } } } } */ >> diff --git >> a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c >> index 1fc97f8b6f2..e5506b78b5e 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c >> @@ -33,7 +33,7 @@ void f (void * restrict in, void * restrict out, int32_t * >> a, int32_t * b, int n >> } >> /* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts >> "-Oz" no-opts "-flto" no-opts "-g" } } } } */ >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts >> "-Oz" no-opts "-flto" no-opts "-g" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts >> "-Oz" no-opts "-flto" no-opts "-g" } } } } */ >> /* { dg-final { scan-assembler-times >> {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts >> "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-Oz" >> no-opts "-flto" no-opts "-g" } } } } */ >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts >> "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-Oz" >> no-opts "-flto" no-opts "-g" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" >> "-O1" no-opts "-funroll-loops" no-opts "-Os" no-opts "-Oz" no-opts "-flto" >> no-opts "-g" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts >> "-Oz" no-opts "-flto" no-opts "-g" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0" >> "-O1" no-opts "-funroll-loops" no-opts "-Os" no-opts "-Oz" no-opts "-flto" >> no-opts "-g" } } } } */ >> diff --git >> a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c >> index f3b37661fbe..256b2841ff0 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c >> @@ -45,7 +45,7 @@ void f (void * restrict in, void * restrict out, int32_t * >> a, int32_t * b, int n >> } >> /* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts >> "-Oz" no-opts "-flto" no-opts "-g" } } } } */ >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { >> no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts >> "-Oz" no-opts "-flto" no-opts "-g" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts >> "-Oz" no-opts "-flto" no-opts "-g" } } } } */ >> /* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { >> no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts >> "-Oz" no-opts "-flto" no-opts "-g" } } } } */ >> /* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts >> "-Oz" no-opts "-flto" no-opts "-g" } } } } */ >> /* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts >> "-Oz" no-opts "-flto" no-opts "-g" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c >> index b82e2490815..6c0f6b71ece 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c >> @@ -13,4 +13,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m, >> vbool64_t mask) { >> } >> /* { dg-final { scan-assembler-times >> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-g" no-opts "-funroll-loops" } } } } */ >> \ No newline at end of file >> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" >> no-opts "-g" no-opts "-funroll-loops" } } } } */ >> \ No newline at end of file >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c >> index e84e32b2509..ebc874af011 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c >> @@ -14,4 +14,4 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t >> *out, size_t n, size_ >> /* { dg-final { scan-assembler-times >> {\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } >> } } */ >> /* { dg-final { scan-assembler-times >> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-g" no-opts "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" >> no-opts "-g" no-opts "-funroll-loops" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c >> index fb7abdeb968..e9c54fba392 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c >> @@ -19,4 +19,4 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t >> *out, size_t n, size_ >> /* { dg-final { scan-assembler-times >> {\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 2 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } >> } } */ >> /* { dg-final { scan-assembler-times >> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" >> no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c >> index 5fa2f2bc294..1000c148e82 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c >> @@ -14,4 +14,4 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t >> *out, size_t n, size_ >> /* { dg-final { scan-assembler-times >> {\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } >> } } */ >> /* { dg-final { scan-assembler-times >> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-g" no-opts "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" >> no-opts "-g" no-opts "-funroll-loops" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c >> index 55cc770cfde..aa253785546 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c >> @@ -19,4 +19,4 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t >> *out, size_t n, size_ >> /* { dg-final { scan-assembler-times >> {\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 2 { target { no-opts >> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } >> } } */ >> /* { dg-final { scan-assembler-times >> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" >> no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c >> index 482a48314e2..853ffee1414 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c >> @@ -17,5 +17,5 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t >> *out, size_t n) { >> } >> } >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-g" no-opts "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c >> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c >> index 3b9865e3bab..2a535b5f2a8 100644 >> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c >> @@ -17,5 +17,5 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t >> *out, size_t n) { >> } >> } >> -/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-g" no-opts "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times >> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { >> no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" >> no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ >> -- >> 2.17.1 >> >>