Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
Why do you need to invade existing shapes ? juzhe.zh...@rivai.ai 发件人： joshua 发送时间： 2024-01-10 15:16 收件人： juzhe.zh...@rivai.ai; gcc-patches 抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; jinma; cooper.qu 主题： Re：Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector These xttheadvector speical intrinsics are different from rvv1.0 in determining function name from base name. We cannot directly reuse the existing shapes. In order not to invade existing shapes, we add new shapes for new functions. Also, we create new thead-vector-builtins.cc for xtheadvector function_base implementation. -- 发件人：juzhe.zh...@rivai.ai 发送时间：2024年1月10日(星期三) 15:01 收件人："cooper.joshua"; "gcc-patches" 抄 送：Jim Wilson; palmer; andrew; "philipp.tomsich"; jeffreyalaw; "christoph.muellner"; jinma; "cooper.qu" 主 题：Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector Why do you add theadvector shapes ? I think you can reuse the current existing shapes. +thead-vector-builtins.o: \+ $(srcdir)/config/riscv/thead-vector-builtins.cc \+ $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \+ $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \+ $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) fold-const.h $(GIMPLE_H) \+ gimple-iterator.h gimplify.h explow.h $(EMIT_RTL_H) tree-vector-builder.h \+ rtx-vector-builder.h \+ $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \+ $(srcdir)/config/riscv/riscv-vector-builtins-bases.h \+ $(srcdir)/config/riscv/thead-vector-builtins.h \+ $(RISCV_BUILTINS_H)+ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \+ $(srcdir)/config/riscv/thead-vector-builtins.cc+ Why do you rebuild another new object ? + Copyright (C) 2022-2023 Free Software Foundation, Inc. Incorrect copyright juzhe.zh...@rivai.ai 发件人： joshua 发送时间： 2024-01-10 10:57 收件人： juzhe.zh...@rivai.ai; gcc-patches 抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; jinma; cooper.qu 主题： Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector Hi Juzhe, Thank you for so many useful comments for this patch! There are some more patches to support xtheadvector special instrinsics as well as handle register overlap issue and rewrite assembly output. https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641774.html https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641732.html https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641733.html Also, there is a precedent patch to refactor riscv-vector-builtins-bases.cc https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641530.html Jeff has reviewed it, but didn't have LGTM yet. Joshua -- 发件人：juzhe.zh...@rivai.ai 发送时间：2024年1月10日(星期三) 10:34 收件人："cooper.joshua"; "gcc-patches" 抄 送：Jim Wilson; palmer; andrew; "philipp.tomsich"; jeffreyalaw; "christoph.muellner"; "cooper.joshua"; jinma; "cooper.qu" 主 题：Re: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector Thanks for your patience. LGTM from myside. I think it's pretty clean now. I can image in the future when some day the theadvector is no longer used, we can remove it very easily. And also, the theadvector won't affect our RVV1.0 maintain since it's isolated cleanly. But I'd like to wait for a few more days some body want to chime in. And you should do more things before commit it: 1. Remember you should run the full coverage RVV1.0 API test, the test-generator is downloaded from official intrinsic doc: https://github.com/riscv-non-isa/rvv-intrinsic-doc 2. Also the regression of RV32 an RV64 of GCC testsuite. Do you have more patches of theadvector that I didn't review ? plz point them to me again. Thanks. juzhe.zh...@rivai.ai From: Jun Sha (Joshua) Date: 2024-01-10 10:22 To: gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu Subject: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share same patterns as RVV1.0 instructions, we will use ASM targethook to rewrite the whole string of the instructions in the following patches. For some vector patterns that cannot be avoided, we use "!TARGET_XTHEADVECTOR" to disable them in vector.md in order not to generate instructions that xtheadvector d
Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
Why do you add theadvector shapes ? I think you can reuse the current existing shapes. +thead-vector-builtins.o: \ + $(srcdir)/config/riscv/thead-vector-builtins.cc \ + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \ + $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \ + $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) fold-const.h $(GIMPLE_H) \ + gimple-iterator.h gimplify.h explow.h $(EMIT_RTL_H) tree-vector-builder.h \ + rtx-vector-builder.h \ + $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \ + $(srcdir)/config/riscv/riscv-vector-builtins-bases.h \ + $(srcdir)/config/riscv/thead-vector-builtins.h \ + $(RISCV_BUILTINS_H) + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/riscv/thead-vector-builtins.cc + Why do you rebuild another new object ? + Copyright (C) 2022-2023 Free Software Foundation, Inc. Incorrect copyright juzhe.zh...@rivai.ai 发件人： joshua 发送时间： 2024-01-10 10:57 收件人： juzhe.zh...@rivai.ai; gcc-patches 抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; jinma; cooper.qu 主题： Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector Hi Juzhe, Thank you for so many useful comments for this patch! There are some more patches to support xtheadvector special instrinsics as well as handle register overlap issue and rewrite assembly output. https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641774.html https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641732.html https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641733.html Also, there is a precedent patch to refactor riscv-vector-builtins-bases.cc https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641530.html Jeff has reviewed it, but didn't have LGTM yet. Joshua -- 发件人：juzhe.zh...@rivai.ai 发送时间：2024年1月10日(星期三) 10:34 收件人："cooper.joshua"; "gcc-patches" 抄 送：Jim Wilson; palmer; andrew; "philipp.tomsich"; jeffreyalaw; "christoph.muellner"; "cooper.joshua"; jinma; "cooper.qu" 主 题：Re: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector Thanks for your patience. LGTM from myside. I think it's pretty clean now. I can image in the future when some day the theadvector is no longer used, we can remove it very easily. And also, the theadvector won't affect our RVV1.0 maintain since it's isolated cleanly. But I'd like to wait for a few more days some body want to chime in. And you should do more things before commit it: 1. Remember you should run the full coverage RVV1.0 API test, the test-generator is downloaded from official intrinsic doc: https://github.com/riscv-non-isa/rvv-intrinsic-doc 2. Also the regression of RV32 an RV64 of GCC testsuite. Do you have more patches of theadvector that I didn't review ? plz point them to me again. Thanks. juzhe.zh...@rivai.ai From: Jun Sha (Joshua) Date: 2024-01-10 10:22 To: gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu Subject: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share same patterns as RVV1.0 instructions, we will use ASM targethook to rewrite the whole string of the instructions in the following patches. For some vector patterns that cannot be avoided, we use "!TARGET_XTHEADVECTOR" to disable them in vector.md in order not to generate instructions that xtheadvector does not support, like vmv1r and vsext.vf2. gcc/ChangeLog: * config.gcc: Add files for XTheadVector intrinsics. * config/riscv/autovec.md: Guard XTheadVector. * config/riscv/riscv-c.cc: Add pragma for XTheadVector. * config/riscv/riscv-string.cc (expand_block_move): Guard XTheadVector. * config/riscv/riscv-string.cc (vls_mode_valid_p): Avoid autovec. * config/riscv/riscv-vector-builtins-shapes.cc (check_type): (build_one): New function. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION): (DEF_THEAD_RVV_FUNCTION): Add new marcos. (check_required_extensions): (handle_pragma_vector): * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR): (RVV_REQUIRE_XTHEADVECTOR): Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR. (struct function_group_info): * config/riscv/riscv-vector-switch.def (ENTRY): Disable fractional mode for the XTheadVector extension. (TUPLE_ENTRY): Likewise. * config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector. * config/riscv/riscv.cc (riscv_v_ext_vls_mode_p): Guard XTheadVe
Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641733.html This patch is ok from my side. juzhe.zh...@rivai.ai 发件人： joshua 发送时间： 2024-01-10 10:57 收件人： juzhe.zh...@rivai.ai; gcc-patches 抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; jinma; cooper.qu 主题： Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector Hi Juzhe, Thank you for so many useful comments for this patch! There are some more patches to support xtheadvector special instrinsics as well as handle register overlap issue and rewrite assembly output. https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641774.html https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641732.html https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641733.html Also, there is a precedent patch to refactor riscv-vector-builtins-bases.cc https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641530.html Jeff has reviewed it, but didn't have LGTM yet. Joshua -- 发件人：juzhe.zh...@rivai.ai 发送时间：2024年1月10日(星期三) 10:34 收件人："cooper.joshua"; "gcc-patches" 抄 送：Jim Wilson; palmer; andrew; "philipp.tomsich"; jeffreyalaw; "christoph.muellner"; "cooper.joshua"; jinma; "cooper.qu" 主 题：Re: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector Thanks for your patience. LGTM from myside. I think it's pretty clean now. I can image in the future when some day the theadvector is no longer used, we can remove it very easily. And also, the theadvector won't affect our RVV1.0 maintain since it's isolated cleanly. But I'd like to wait for a few more days some body want to chime in. And you should do more things before commit it: 1. Remember you should run the full coverage RVV1.0 API test, the test-generator is downloaded from official intrinsic doc: https://github.com/riscv-non-isa/rvv-intrinsic-doc 2. Also the regression of RV32 an RV64 of GCC testsuite. Do you have more patches of theadvector that I didn't review ? plz point them to me again. Thanks. juzhe.zh...@rivai.ai From: Jun Sha (Joshua) Date: 2024-01-10 10:22 To: gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu Subject: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share same patterns as RVV1.0 instructions, we will use ASM targethook to rewrite the whole string of the instructions in the following patches. For some vector patterns that cannot be avoided, we use "!TARGET_XTHEADVECTOR" to disable them in vector.md in order not to generate instructions that xtheadvector does not support, like vmv1r and vsext.vf2. gcc/ChangeLog: * config.gcc: Add files for XTheadVector intrinsics. * config/riscv/autovec.md: Guard XTheadVector. * config/riscv/riscv-c.cc: Add pragma for XTheadVector. * config/riscv/riscv-string.cc (expand_block_move): Guard XTheadVector. * config/riscv/riscv-string.cc (vls_mode_valid_p): Avoid autovec. * config/riscv/riscv-vector-builtins-shapes.cc (check_type): (build_one): New function. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION): (DEF_THEAD_RVV_FUNCTION): Add new marcos. (check_required_extensions): (handle_pragma_vector): * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR): (RVV_REQUIRE_XTHEADVECTOR): Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR. (struct function_group_info): * config/riscv/riscv-vector-switch.def (ENTRY): Disable fractional mode for the XTheadVector extension. (TUPLE_ENTRY): Likewise. * config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector. * config/riscv/riscv.cc (riscv_v_ext_vls_mode_p): Guard XTheadVector. (riscv_v_adjust_bytesize): Likewise. (riscv_preferred_simd_mode): Likewsie. (riscv_autovectorize_vector_modes): Likewise. (riscv_vector_mode_supported_any_target_p): Likewise. (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise. * config/riscv/vector.md: Include thead-vector.md. * config/riscv/riscv_th_vector.h: New file. * config/riscv/thead-vector.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector. * gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector. * lib/target-supports.exp: Add target for XTheadVector. Co-authored-by: Jin Ma Co-authored-by: Xianmiao Qu Co-authored-by: Christoph Müllner --- gcc/config.gcc| 2 +- gcc/config/riscv/autovec.md | 2 +- gcc/config/riscv/predicates.md| 4 +- gcc/config/riscv/riscv-c.c
Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp" - [(set (match_operand: 0 "register_operand""=vr, vr, vr, vr") + [(set (match_operand: 0 "register_operand""=vr, vr, vr, vr, , , , ") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") -(match_operand 6 "vector_length_operand" " rK, rK, rK, rK") -(match_operand 7 "const_int_operand" "i,i, i,i") -(match_operand 8 "const_int_operand" "i,i, i,i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") +(match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") +(match_operand 7 "const_int_operand" "i,i, i,i,i,i,i,i") +(match_operand 8 "const_int_operand" "i,i, i,i,i,i,i,i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_ltge_operator" -[(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr") - (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi")]) - (match_operand: 2 "vector_merge_operand"" vu,0, vu,0")))] +[(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr") + (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi, vr, vr, vi, vi")]) + (match_operand: 2 "vector_merge_operand"" vu,0, vu,0, vu,0, vu,0")))] "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.v%o5\t%0,%4,%v5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,th,th,none,none,none,none")]) You are add ", , , " which will be enabled when TARGET_VECTOR. You should disable these constraints when TARGET_VECTOR is enabled. juzhe.zh...@rivai.ai 发件人： joshua 发送时间： 2024-01-10 10:57 收件人： juzhe.zh...@rivai.ai; gcc-patches 抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; jinma; cooper.qu 主题： Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector Hi Juzhe, Thank you for so many useful comments for this patch! There are some more patches to support xtheadvector special instrinsics as well as handle register overlap issue and rewrite assembly output. https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641774.html https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641732.html https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641733.html Also, there is a precedent patch to refactor riscv-vector-builtins-bases.cc https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641530.html Jeff has reviewed it, but didn't have LGTM yet. Joshua -- 发件人：juzhe.zh...@rivai.ai 发送时间：2024年1月10日(星期三) 10:34 收件人："cooper.joshua"; "gcc-patches" 抄 送：Jim Wilson; palmer; andrew; "philipp.tomsich"; jeffreyalaw; "christoph.muellner"; "cooper.joshua"; jinma; "cooper.qu" 主 题：Re: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector Thanks for your patience. LGTM from myside. I think it's pretty clean now. I can image in the future when some day the theadvector is no longer used, we can remove it very easily. And also, the theadvector won't affect our RVV1.0 maintain since it's isolated cleanly. But I'd like to wait for a few more days some body want to chime in. And you should do more things before commit it: 1. Remember you should run the full coverage RVV1.0 API test, the test-generator is downloaded from official intrinsic doc: https://github.com/riscv-non-isa/rvv-intrinsic-doc 2. Also the regression of RV32 an RV64 of GCC testsuite. Do you have more patches of theadvector that I didn't review ? plz point them to me again. Thanks. juzhe.zh...@rivai.ai From: Jun Sha (Joshua) Date: 2024-01-10 10:22 To: gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner;
