My last patch for PR64110 results in LRA crash on ARM on compilation
of some programs. There is no PR for it. Here is the patch fixing the
occurred problem.
The patch was tested and bootstrapped on x86/x86-64 and ARM.
Committed as rev. 218760.
2014-12-15 Vladimir Makarov <vmaka...@redhat.com>
* ira-int.h (ira_prohibited_class_mode_regs): Remove.
(struct target_ira_int): Move x_ira_prohibited_class_mode_regs to
...
* ira.h (struct target_ira): ... here.
(ira_prohibited_class_mode_regs): Define.
* lra-constraints.c (process_alt_operands): Add one more condition
to refuse alternative when reload pseudo of given class can not
hold value of given mode.
Index: ira.h
===================================================================
--- ira.h (revision 218685)
+++ ira.h (working copy)
@@ -110,6 +110,11 @@
/* Function specific hard registers can not be used for the register
allocation. */
HARD_REG_SET x_ira_no_alloc_regs;
+
+ /* Array whose values are hard regset of hard registers available for
+ the allocation of given register class whose HARD_REGNO_MODE_OK
+ values for given mode are zero. */
+ HARD_REG_SET
x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
};
extern struct target_ira default_target_ira;
@@ -155,6 +160,8 @@
(this_target_ira->x_ira_class_singleton)
#define ira_no_alloc_regs \
(this_target_ira->x_ira_no_alloc_regs)
+#define ira_prohibited_class_mode_regs \
+ (this_target_ira->x_ira_prohibited_class_mode_regs)
/* Major structure describing equivalence info for a pseudo. */
struct ira_reg_equiv_s
Index: ira-int.h
===================================================================
--- ira-int.h (revision 218685)
+++ ira-int.h (working copy)
@@ -843,11 +843,6 @@
unavailable for the allocation. */
short x_ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
- /* Array whose values are hard regset of hard registers available for
- the allocation of given register class whose HARD_REGNO_MODE_OK
- values for given mode are zero. */
- HARD_REG_SET
x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
-
/* Index [CL][M] contains R if R appears somewhere in a register of the form:
(reg:M R'), R' not in x_ira_prohibited_class_mode_regs[CL][M]
@@ -939,8 +934,6 @@
(this_target_ira_int->x_ira_non_ordered_class_hard_regs)
#define ira_class_hard_reg_index \
(this_target_ira_int->x_ira_class_hard_reg_index)
-#define ira_prohibited_class_mode_regs \
- (this_target_ira_int->x_ira_prohibited_class_mode_regs)
#define ira_useful_class_mode_regs \
(this_target_ira_int->x_ira_useful_class_mode_regs)
#define ira_important_classes_num \
Index: lra-constraints.c
===================================================================
--- lra-constraints.c (revision 218688)
+++ lra-constraints.c (working copy)
@@ -2269,17 +2269,25 @@
/* Alternative loses if it required class pseudo can not
hold value of required mode. Such insns can be
- described by insn definitions with mode iterators.
- Don't use ira_prohibited_class_mode_regs here as it
- is common practice for constraints to use a class
- which does not have actually enough regs to hold the
- value (e.g. x86 AREG for mode requiring more one
- general reg). */
+ described by insn definitions with mode iterators. */
if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode
&& ! hard_reg_set_empty_p (this_alternative_set)
+ /* It is common practice for constraints to use a
+ class which does not have actually enough regs to
+ hold the value (e.g. x86 AREG for mode requiring
+ more one general reg). Therefore we have 2
+ conditions to check that the reload pseudo can
+ not hold the mode value. */
&& ! HARD_REGNO_MODE_OK (ira_class_hard_regs
[this_alternative][0],
- GET_MODE
(*curr_id->operand_loc[nop])))
+ GET_MODE
(*curr_id->operand_loc[nop]))
+ /* The above condition is not enough as the first
+ reg in ira_class_hard_regs can be not aligned for
+ multi-words mode values. */
+ && hard_reg_set_subset_p (this_alternative_set,
+ ira_prohibited_class_mode_regs
+ [this_alternative]
+ [GET_MODE
(*curr_id->operand_loc[nop])]))
{
if (lra_dump_file != NULL)
fprintf
