[PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]
From: xuli When stride == element width, vlsse should be optimized into vle.v. vsse should be optimized into vse.v. PR target/111450 gcc/ChangeLog: *config/riscv/constraints.md (c01): const_int 1. (c02): const_int 2. (c04): const_int 4. (c08): const_int 8. * config/riscv/predicates.md (vector_eew8_stride_operand): New predicate for stride operand. (vector_eew16_stride_operand): Ditto. (vector_eew32_stride_operand): Ditto. (vector_eew64_stride_operand): Ditto. * config/riscv/vector-iterators.md: New iterator for stride operand. * config/riscv/vector.md: Add stride = element width constraint. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr111450.c: New test. --- gcc/config/riscv/constraints.md | 20 gcc/config/riscv/predicates.md| 18 gcc/config/riscv/vector-iterators.md | 87 +++ gcc/config/riscv/vector.md| 42 +--- .../gcc.target/riscv/rvv/base/pr111450.c | 100 ++ 5 files changed, 250 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111450.c diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 3f52bc76f67..964fdd450c9 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -45,6 +45,26 @@ (and (match_code "const_int") (match_test "ival == 0"))) +(define_constraint "c01" + "Constant value 1." + (and (match_code "const_int") + (match_test "ival == 1"))) + +(define_constraint "c02" + "Constant value 2" + (and (match_code "const_int") + (match_test "ival == 2"))) + +(define_constraint "c04" + "Constant value 4" + (and (match_code "const_int") + (match_test "ival == 4"))) + +(define_constraint "c08" + "Constant value 8" + (and (match_code "const_int") + (match_test "ival == 8"))) + (define_constraint "K" "A 5-bit unsigned immediate for CSR access instructions." (and (match_code "const_int") diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 4bc7ff2c9d8..7845998e430 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -514,6 +514,24 @@ (ior (match_operand 0 "const_0_operand") (match_operand 0 "pmode_register_operand"))) +;; [1, 2, 4, 8] means strided load/store with stride == element width +(define_special_predicate "vector_eew8_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 1 || INTVAL (op) == 0" +(define_special_predicate "vector_eew16_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 2 || INTVAL (op) == 0" +(define_special_predicate "vector_eew32_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 4 || INTVAL (op) == 0" +(define_special_predicate "vector_eew64_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 8 || INTVAL (op) == 0" + ;; A special predicate that doesn't match a particular mode. (define_special_predicate "vector_any_register_operand" (match_code "reg")) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 73df55a69c8..f85d1cc80d1 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -2596,6 +2596,93 @@ (V512DI "V512BI") ]) +(define_mode_attr stride_predicate [ + (RVVM8QI "vector_eew8_stride_operand") (RVVM4QI "vector_eew8_stride_operand") + (RVVM2QI "vector_eew8_stride_operand") (RVVM1QI "vector_eew8_stride_operand") + (RVVMF2QI "vector_eew8_stride_operand") (RVVMF4QI "vector_eew8_stride_operand") + (RVVMF8QI "vector_eew8_stride_operand") + + (RVVM8HI "vector_eew16_stride_operand") (RVVM4HI "vector_eew16_stride_operand") + (RVVM2HI "vector_eew16_stride_operand") (RVVM1HI "vector_eew16_stride_operand") + (RVVMF2HI "vector_eew16_stride_operand") (RVVMF4HI "vector_eew16_stride_operand") + + (RVVM8HF "vector_eew16_stride_operand") (RVVM4HF "vector_eew16_stride_operand") + (RVVM2HF "vector_eew16_stride_operand") (RVVM1HF "vector_eew16_stride_operand") + (RVVMF2HF "vector_eew16_stride_operand") (RVVMF4HF "vector_eew16_stride_operand") + + (RVVM8SI "vector_eew32_stride_operand") (RVVM4SI "vector_eew32_stride_operand") + (RVVM2SI "vector_eew32_stride_operand") (RVVM1SI "vector_eew32_stride_operand") + (RVVMF2SI "vector_eew32_stride_operand") + + (RVVM8SF "vector_eew32_stride_operand") (RVVM4SF "vector_eew32_stride_operand") + (RVVM2SF "vector_eew32_stride_operand") (RVVM1SF "vector_eew32_stride_operand") + (RVVMF2SF
Re: Re: [PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]
Committed, thanks Juzhe. -- Li Xu >Thanks a lot. LGTM. > > > >juzhe.zh...@rivai.ai > >From: Li Xu >Date: 2023-09-21 11:12 >To: gcc-patches >CC: kito.cheng; palmer; juzhe.zhong; xuli >Subject: [PATCH] RISC-V: Optimized for strided load/store with stride == >element width[PR111450] >From: xuli > >When stride == element width, vlsse should be optimized into vle.v. >vsse should be optimized into vse.v. > >PR target/111450 > >gcc/ChangeLog: > >*config/riscv/constraints.md (c01): const_int 1. >(c02): const_int 2. >(c04): const_int 4. >(c08): const_int 8. >* config/riscv/predicates.md (vector_eew8_stride_operand): New predicate for >stride operand. >(vector_eew16_stride_operand): Ditto. >(vector_eew32_stride_operand): Ditto. >(vector_eew64_stride_operand): Ditto. >* config/riscv/vector-iterators.md: New iterator for stride operand. >* config/riscv/vector.md: Add stride = element width constraint. > >gcc/testsuite/ChangeLog: > >* gcc.target/riscv/rvv/base/pr111450.c: New test. >--- >gcc/config/riscv/constraints.md | 20 >gcc/config/riscv/predicates.md | 18 >gcc/config/riscv/vector-iterators.md | 87 +++ >gcc/config/riscv/vector.md | 42 +--- >.../gcc.target/riscv/rvv/base/pr111450.c | 100 ++ >5 files changed, 250 insertions(+), 17 deletions(-) >create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111450.c > >diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md >index 3f52bc76f67..964fdd450c9 100644 >--- a/gcc/config/riscv/constraints.md >+++ b/gcc/config/riscv/constraints.md >@@ -45,6 +45,26 @@ > (and (match_code "const_int") > (match_test "ival == 0"))) >+(define_constraint "c01" >+ "Constant value 1." >+ (and (match_code "const_int") >+ (match_test "ival == 1"))) >+ >+(define_constraint "c02" >+ "Constant value 2" >+ (and (match_code "const_int") >+ (match_test "ival == 2"))) >+ >+(define_constraint "c04" >+ "Constant value 4" >+ (and (match_code "const_int") >+ (match_test "ival == 4"))) >+ >+(define_constraint "c08" >+ "Constant value 8" >+ (and (match_code "const_int") >+ (match_test "ival == 8"))) >+ >(define_constraint "K" > "A 5-bit unsigned immediate for CSR access instructions." > (and (match_code "const_int") >diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md >index 4bc7ff2c9d8..7845998e430 100644 >--- a/gcc/config/riscv/predicates.md >+++ b/gcc/config/riscv/predicates.md >@@ -514,6 +514,24 @@ > (ior (match_operand 0 "const_0_operand") > (match_operand 0 "pmode_register_operand"))) >+;; [1, 2, 4, 8] means strided load/store with stride == element width >+(define_special_predicate "vector_eew8_stride_operand" >+ (ior (match_operand 0 "pmode_register_operand") >+ (and (match_code "const_int") >+ (match_test "INTVAL (op) == 1 || INTVAL (op) == 0" >+(define_special_predicate "vector_eew16_stride_operand" >+ (ior (match_operand 0 "pmode_register_operand") >+ (and (match_code "const_int") >+ (match_test "INTVAL (op) == 2 || INTVAL (op) == 0" >+(define_special_predicate "vector_eew32_stride_operand" >+ (ior (match_operand 0 "pmode_register_operand") >+ (and (match_code "const_int") >+ (match_test "INTVAL (op) == 4 || INTVAL (op) == 0" >+(define_special_predicate "vector_eew64_stride_operand" >+ (ior (match_operand 0 "pmode_register_operand") >+ (and (match_code "const_int") >+ (match_test "INTVAL (op) == 8 || INTVAL (op) == 0" >+ >;; A special predicate that doesn't match a particular mode. >(define_special_predicate "vector_any_register_operand" > (match_code "reg")) >diff --git a/gcc/config/riscv/vector-iterators.md >b/gcc/config/riscv/vector-iterators.md >index 73df55a69c8..f85d1cc80d1 100644 >--- a/gcc/config/riscv/vector-iterators.md >+++ b/gcc/config/riscv/vector-iterators.md >@@ -2596,6 +2596,93 @@ > (V512DI "V512BI") >]) >+(define_mode_attr stride_predicate [ >+ (RVVM8QI "vector_eew8_stride_operand") (RVVM4QI >"vector_eew8_stride_operand") >+ (RVVM2QI "vector_eew8_stride_operand") (RVVM1QI >"vector_eew8_stride_operand") >+ (RVVMF2QI "vector_eew8_stride_operand") (RVVMF4QI >"vector_eew8_stride_operand") >+ (RVVMF8QI "vector_eew8_stride_operand") >+ >+ (RVVM8HI "vector_eew16_stride_operand") (RVVM4HI >"vector_eew16_stride_operand") >+ (RVVM2HI "vector_eew16_stride_operand") (RVVM1HI >"vector_eew16_stride_operand") >+ (RVVMF2HI "vector_eew16_stride_operand") (RVVMF4HI >"vector_eew16_stride_operand") >+ >+ (RVVM8HF "vector_eew16_stride_operand") (RVVM4HF >"vector_eew16_stride_operand") >+ (RVVM2HF "vector_eew16_stride_operand") (RVVM1HF >"vector_eew16_stride_operand") >+ (RVVMF2HF "vector_eew16_stride_operand") (RVVMF4HF >"vector_eew16_stride_operand") >+ >+ (RVVM8SI "vector_eew32_stride_operand") (RVVM4SI >"vector_eew32_stride_operand") >+ (RVVM2SI
Re: [PATCH][_GLIBCXX_INLINE_VERSION] Fix
Tests were successful, ok to commit ? On 20/09/2023 19:51, François Dumont wrote: libstdc++: [_GLIBCXX_INLINE_VERSION] Add handle_contract_violation symbol alias libstdc++-v3/ChangeLog: * src/experimental/contract.cc [_GLIBCXX_INLINE_VERSION](handle_contract_violation): Provide symbol alias without version namespace decoration for gcc. Here is what I'm testing eventually, ok to commit if successful ? François On 20/09/2023 11:32, Jonathan Wakely wrote: On Wed, 20 Sept 2023 at 05:51, François Dumont via Libstdc++ wrote: libstdc++: Remove std::constract_violation from versioned namespace Spelling mistake in contract_violation, and it's not std::contract_violation, it's std::experimental::contract_violation GCC expects this type to be in std namespace directly. Again, it's in std::experimental not in std directly. Will this change cause problems when including another experimental header, which does put experimental below std::__8? I think std::__8::experimental and std::experimental will become ambiguous. Maybe we do want to remove the inline __8 namespace from all experimental headers. That needs a bit more thought though. libstdc++-v3/ChangeLog: * include/experimental/contract: Remove _GLIBCXX_BEGIN_NAMESPACE_VERSION/_GLIBCXX_END_NAMESPACE_VERSION. This line is too long for the changelog. It does fix 29 g++.dg/contracts in gcc testsuite. Ok to commit ? François
Re: [PATCH] check undefine_p for one more vr
> Am 21.09.2023 um 05:10 schrieb Jiufu Guo :
>
> Hi,
>
> The root cause of PR111355 and PR111482 is missing to check if vr0
> is undefined_p before call vr0.lower_bound.
>
> In the pattern "(X + C) / N",
>
>(if (INTEGRAL_TYPE_P (type)
> && get_range_query (cfun)->range_of_expr (vr0, @0))
> (if (...)
> (plus (op @0 @2) { wide_int_to_tree (type, plus_op1 (c)); })
> (if (TYPE_UNSIGNED (type) && c.sign_mask () < 0 ...
>&& wi::geu_p (vr0.lower_bound (), -c))
>
> In "(if (...)", there is code to prevent vr0's undefined_p,
> But in the "else" part, vr0's undefined_p is not checked before
> "wi::geu_p (vr0.lower_bound (), -c)".
>
> Bootstrap & regtest pass on ppc64{,le}.
> Is this ok for trunk?
Ok
Richard
> BR,
> Jeff (Jiufu Guo)
>
>
>PR tree-optimization/111355
>
> gcc/ChangeLog:
>
>* match.pd ((X + C) / N): Update pattern.
>
> gcc/testsuite/ChangeLog:
>
>* gcc.dg/pr111355.c: New test.
>
> ---
> gcc/match.pd| 2 +-
> gcc/testsuite/gcc.dg/pr111355.c | 8
> 2 files changed, 9 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.dg/pr111355.c
>
> diff --git a/gcc/match.pd b/gcc/match.pd
> index 39c9c81966a..5fdfba14d47 100644
> --- a/gcc/match.pd
> +++ b/gcc/match.pd
> @@ -1033,7 +1033,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
> || (vr0.nonnegative_p () && vr3.nonnegative_p ())
> || (vr0.nonpositive_p () && vr3.nonpositive_p (
>(plus (op @0 @2) { wide_int_to_tree (type, plus_op1 (c)); })
> - (if (TYPE_UNSIGNED (type) && c.sign_mask () < 0
> + (if (!vr0.undefined_p () && TYPE_UNSIGNED (type) && c.sign_mask () < 0
>&& exact_mod (-c)
>/* unsigned "X-(-C)" doesn't underflow. */
>&& wi::geu_p (vr0.lower_bound (), -c))
> diff --git a/gcc/testsuite/gcc.dg/pr111355.c b/gcc/testsuite/gcc.dg/pr111355.c
> new file mode 100644
> index 000..8bacbc69d31
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/pr111355.c
> @@ -0,0 +1,8 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O3 -Wno-div-by-zero" } */
> +
> +/* Make sure no ICE. */
> +int main() {
> + unsigned b;
> + return b ? 1 << --b / 0 : 0;
> +}
> --
> 2.25.1
>
