gEDA-user: PCB polygon rectangle practicalities
In fooling with various practice layouts (partial layouts, actually) I think I have the basics of polygons and rectangles sorted out. Now I'm wondering about the practicalities is adjoining poly's. Here is the situation: In my design, there wants to be a polygon patch of analog ground that will have nothing routed through it, although there will be a few clearance vias and thermal-relief joined vias. This polygon will be on the solder side (2 sided design) and will be an island in what I hope will be a fairly continuous chunk of digital ground plane, although I'm planning the solder side as my Y-axis routing layer, so there will be lots of traces cleared out through it. Anyway the point is, while the analog ground patch is easy to draw as a poly, the digital ground wants to be a simple rectangle with an island in it. I presume that the best way to make that happen is to lay down the AGND poly, and then draw several rectangles/poly's for GND until the composite is the shape I want. So... do I need to overlap the GND poly's so that they will join up? Or can I just turn on the grid and draw to the snaps and count on touching to be enough to actually join them? Are there some gotcha's here that I haven't thought of that I am going to trip over? Manufacturability issues? -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Trouble with CONN_USB
HI there. I saw in the list archive that I am not the only one that failsmaking gsch2pcb to accept the CONN_USB landpattern. Is the problem the missing inc-file? Has a problem been solved? Where do I find the solution? Regards Olof ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: smd challenge board status - last step!
Dave McGuire wrote: On Oct 20, 2006, at 8:26 PM, DJ Delorie wrote: I wonder if you can hand-solder SOJ if you start by putting solder paste on the pads, so that you use the tip to reflow the paste? I've done this with a hot-air pencil. I find it a bit easier than doing SOJs with an iron and wire solder. Do you have to control the temperature of a small tube hot air source to keep it from being too hot, or is it just always hot enough to do damage and you take off the heat when you see melting to avoid damage? I have an unregulated air heater intended for plastic welding, and I imagine it could work somewhat with a variac controlling it's heat input, and pressure regulator and trial and error to find settings. How do the kinds Pace and others make work? Do they have a hot box with quick FB control on it's temp, and go from zero flow to preset flow when you want heat? John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: smd challenge board status - last step!
FYI: They still throb too fast to see (30Hz). Those caps are not very precise. U? What's their tolerance spec? They're X5R's, rated at 10%. That board is going about 700Hz+, so they're 5% off, but I've seen them up to 20% off when measuring them with my multimeter, not that my multimeter is a gold standard either. Keep in mind this is the largest capacitance they can fit in that package; it's 0.01uF! Note that the frequencies rely on the resistor tolerance too, although every one I measured was dead on. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB polygon rectangle practicalities
Dave N6NZ wrote: In fooling with various practice layouts (partial layouts, actually) I think I have the basics of polygons and rectangles sorted out. Now I'm wondering about the practicalities is adjoining poly's. Here is the situation: In my design, there wants to be a polygon patch of analog ground that will have nothing routed through it, although there will be a few clearance vias and thermal-relief joined vias. This polygon will be on the solder side (2 sided design) and will be an island in what I hope will be a fairly continuous chunk of digital ground plane, although I'm planning the solder side as my Y-axis routing layer, so there will be lots of traces cleared out through it. Anyway the point is, while the analog ground patch is easy to draw as a poly, the digital ground wants to be a simple rectangle with an island in it. I presume that the best way to make that happen is to lay down the AGND poly, and then draw several rectangles/poly's for GND until the composite is the shape I want. So... do I need to overlap the GND poly's so that they will join up? Or can I just turn on the grid and draw to the snaps and count on touching to be enough to actually join them? Are there some gotcha's here that I haven't thought of that I am going to trip over? Manufacturability issues? Touching is sufficient for the polygons to make contact. However, there is no harm in overlapping them a bit. The new polygon clipping code will dice up any polygon that has holes in it into smaller ones that don't have holes and they just touch, they don't overlap. You should be able to create the larger digital ground plane from only two drawn polygons. Another trick you can use would be to just draw a single rectangle over the board, and use clearing lines (and/or arcs) to isolate the analog ground island. If you are routing a lot of tracks through the ground plane, chances are that you will create other unintentional islands too. You can use the MorphPolygon() command to make new polys from the islands (including the analog ground one, and if you do this then after the morph you can remove the tracks originally used to create the isolation). It will be up to you to connect any islands that don't end up connected. I don't think you'll run into any manufacturing issues. harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: smd challenge board status - last step!
DJ Delorie wrote: I'll give some feed back to that. I was planing on ordering ten. Not that I'm that bad at soldering, but some people at work could use some practice. Note that ten packs aren't cut up; you'll need a scroll saw or other pcb cutter with a narrow kerf. I use a #2 blade. I'm going to cut up the singles first, and if I have any blades left (they dull quickly on fr4) I'll start working on the ten packs. A Hong Kong/Chinese board fabber, YukShing Circuits, sent me some FR-1 that could be good for a product version of The soldering challenge -- Are YOU up to it? advertised in circuit cellar. His company has edges left over from cutting some panels out and they give 2Kg of these away as a way to drum up business... With FR-1 you would have a built in heat indicator if soldering too long and hot -- the paper-phenolic board will scorch. Cutting them is easy -- score and snap. The dust is much less dangerous than the glass dust that FR-4 makes when sawing it hobby-style, (see silicosis). With soldering irons as the main way to assemble, the extra heat of no-lead solder would not be all over the board, just at the hot iron tip, so not likely to even scorch if melted quickly. John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Trouble with CONN_USB
Thanks John, but how do I make these land patterns integrate with symbols I create in gschem? And how do I make gsch2pcb recognize them when I want to create a netlist? Olof - Original Message - From: John Luciani [EMAIL PROTECTED] To: gEDA user mailing list geda-user@moria.seul.org Cc: geda-user@seul.org Sent: Saturday, October 21, 2006 5:42 PM Subject: Re: gEDA-user: Trouble with CONN_USB On 10/21/06, Olof Tångrot [EMAIL PROTECTED] wrote: HI there. Where do I find the solution? Regards Olof I have a USB Type B connector at http://www.luciani.org/geda/pcb/pcb-footprint-list.html#Connector (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: How To Unsubscribe?
I am off for a few months. I don't want email piling up. unsubscribe geda-user@seul.org unsubscribe: unknown list 'geda-user@seul.org'. Help for [EMAIL PROTECTED]: unsubscribe geda-user unsubscribe: unknown list 'geda-user'. Help for [EMAIL PROTECTED]: Both refused. tomdean ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Trouble with CONN_USB
Olof, you'll generally want symbols that match your footprints. the symbols may be very specific, or very generic. In any event, you want the pins on the symbol to coincide with the pins on the footprints. pin 1 needs to match up with pin 1. The symbols only need two attributes to go from gschem to pcb using gsch2pcb: refdes= and footprint=. you can use gattrib to quickly add footprints to the elements in your layout before running gsch2pcb. you can see the script on Luciani's website to see how to force gsch2pcb to find a specific directory of footprints. As for symbols, you can probably get what you need from the geda library included with the program. you WILL have to check the pin-numbering though. As a default each pin in a symbol should have: pinnumber=# pinseq=# pinlabel=# pintype=value usually pinnumber, pinseq, and pinlabel can all be the same, i.e. 1 for pin one on a chip or capacitor. hope this helps. there is file called the 'master attribute document' that's easy to find. the gsch2pcb system seems really slow at first, but it will save you TONS of time down the road. Phil Olof Tångrot wrote: Thanks John, but how do I make these land patterns integrate with symbols I create in gschem? And how do I make gsch2pcb recognize them when I want to create a netlist? Olof - Original Message - From: John Luciani [EMAIL PROTECTED] To: gEDA user mailing list geda-user@moria.seul.org Cc: geda-user@seul.org Sent: Saturday, October 21, 2006 5:42 PM Subject: Re: gEDA-user: Trouble with CONN_USB On 10/21/06, Olof Tångrot [EMAIL PROTECTED] wrote: HI there. Where do I find the solution? Regards Olof I have a USB Type B connector at http://www.luciani.org/geda/pcb/pcb-footprint-list.html#Connector (* jcl *) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: bending design rules for TSSOP20 -- need advice
Thought I just saw a thread on this topic, but I deleted the whole works and can't find it in the archives. I'm trying to reconcile a data sheet for a TSSOP-20, 0.65mm lead pitch package with PCBexpress's design rules. The problem: 26mil l.p. and 10mil pad width leaves 16mil btw pads. The rule: 8mil between mask and copper leaves exactly 0 mils of mask between pins. So can I bend something here and get a reasonable board? Something like: go to an 8mil pad width so that I get 2mil of mask in between. Pad is too skinny, but I guessing should reflow well... those of you with more experience than me at SMT need to clue me up. Will 2mil of mask be too skinny to work well? Other option: live with no mask between pins and hope I don't bridge. Thoughts? -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: bending design rules for TSSOP20 -- need advice
Below a certain pitch, mask becomes almost useless, because the solder will bride from pin to pin anyway. The challenge boards are 0.50m and 0.40mm pitch and neither has mask between the pins. What seems to work for me is to just glob on the solder, then go over it with a desolder braid where needed. That removes the glob on top, but leaves the solder under the pin. This is with a 20 mil needle tip, not the oft-recommended hoof tip. PCB-Pool wants mask to be 0.15mm bigger, then they clarify that it's mask size minus pad size. That means the gap between copper and mask edge is 0.075mm (3mil). They also specify a minimum 0f 0.15mm remaining between masks (6mil). That means you need at least 0.3mm (12 mil) between pad copper to get a mask. I know I interpreted these right because of two 0.65mm pitch parts on my other board, both with exactly the minimum mask, one had mask between pins and the other didn't (implying that one was a little off one way, and the other a little off the other way). Interpreting your data the same way, they want the distance between mask edge and pad copper to be 4 mils, leaving 8 mils for mask. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: bending design rules for TSSOP20 -- need advice
Thanks, very helpful. That seems like the correct interpretation of their use of the word swell. -dave DJ Delorie wrote: Below a certain pitch, mask becomes almost useless, because the solder will bride from pin to pin anyway. The challenge boards are 0.50m and 0.40mm pitch and neither has mask between the pins. What seems to work for me is to just glob on the solder, then go over it with a desolder braid where needed. That removes the glob on top, but leaves the solder under the pin. This is with a 20 mil needle tip, not the oft-recommended hoof tip. PCB-Pool wants mask to be 0.15mm bigger, then they clarify that it's mask size minus pad size. That means the gap between copper and mask edge is 0.075mm (3mil). They also specify a minimum 0f 0.15mm remaining between masks (6mil). That means you need at least 0.3mm (12 mil) between pad copper to get a mask. I know I interpreted these right because of two 0.65mm pitch parts on my other board, both with exactly the minimum mask, one had mask between pins and the other didn't (implying that one was a little off one way, and the other a little off the other way). Interpreting your data the same way, they want the distance between mask edge and pad copper to be 4 mils, leaving 8 mils for mask. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
