Re: gEDA-user: gnucap: how to use .MODEL?
On Fri, Oct 27, 2006 at 07:59:33PM -0400, al davis wrote: On Friday 27 October 2006 17:08, al davis wrote: On Friday 27 October 2006 16:16, Karel Kulhavy wrote: Does anyone know how to simulate BFG410W transistor in Put a blank line at the beginning of the included file. As per a VERY early Spice standard, the first line of any file is a title, which is stored and not used. I answered too quickly .. What version are you using? Get the new one. It no longer ignores the first line, consistent with more recent versions of spice. Gnucap 2005.06.10 RCS 25.28 Was the first line ignorance written in the gnucap documentation? CL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnucap: how to use .MODEL?
On Sunday 29 October 2006 02:33, Karel Kulhavy wrote: Gnucap 2005.06.10 RCS 25.28 Was the first line ignorance written in the gnucap documentation? You have a development snapshot, a rather old one. Things are often out of sync in development snapshots. Development has been happening at a fairly fast pace lately. New snapshots have been released almost monthly. The latest stable version is 0.35, about a month ago. http://www.gnucap.org Based on the almost monthly schedule, that means another development snapshot is coming soon. There is a lot of hidden stuff, base code that will eventually be used for Verilog support. There will be a few little goodies that will be useful now. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB and new thermals syntax error
søn, 29 10 2006 kl. 00:36 -0400, skrev DJ Delorie: PolyArea[2.00] Take this line out. Tnx. Right on the spot; but wasn't it clever if PCB wasn't afraid of those lines, or deleted them automatically. It makes it easier to update old projects. Happy hacking Chris ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB and new thermals syntax error
søn, 29 10 2006 kl. 08:51 -0500, skrev Harry Eaton: Actually this is not due to trouble reading old files. Only the latest cvs creates the PolyArea line, but the read parser was expecting it to appear after the Thermal line, not before. I have corrected the cvs source so that it expects it in the right place. harry Tnx. I'll grab a fast update. Chris ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Current source rail blocking
Hello In my broadband high sensitivity amplifier I have a rail where bases of all current source transistors are hooked up. Each current source is a transistor with an emitter resistor which compensates variance in aplification so that even unmatched transistors produce matched currents. Do you have any recommendations how to block the current sources from picking up some garbage from the air and causing oscillation? Should I block the rail with a single big capacitor against the ground, or use individual capacitor for each transistor placed between emitter and base? CL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Current source rail blocking
Do you have any recommendations how to block the current sources from picking up some garbage from the air and causing oscillation? Should I block the rail with a single big capacitor against the ground, or use individual capacitor for each transistor placed between emitter and base? In my m3a expansion board, I did both. I put big caps near the board's power feed, medium caps on the ends of the rails, and small caps right at each power pin. In your case, you'd want a medium cap at the end of each rail to provide low frequency bypassing, and a small-package cap right at each base for high frequency bypassing. This is based on my guess that smaller packages plus less traces means higher inductance; you'd have to figure out how the trace/package inductance figures in to your RF circuits. http://www.delorie.com/pcb/m3a/board.pcb ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schottky diode?
On Oct 29, 2006, at 11:37 AM, Dan McMahill wrote: to a sun, I would do make g++ CC which would build it twice, once with g++ and then with Sun's own compiler. Should I be on the lookout for one of those ultra sparc's Dan M likes? There are chip co's in my town Maybe could get you one cheap. It might be a stretch to say I like them. When I got mine it was because there was a critical piece of software I needed to run and solaris/sparc was the platform I needed. Linux/x86 versions are available now, but I just can't justify spending money to replace the sun right now. Besides, its a wonderful way to trip over lots of silly bugs in software written by all the worlds an x86 linux box coders Ugh. I can't see replacing a nice modern architecture with something as distasteful as an x86 box. With companies going tits-up all over the place, Real Computers are available SO cheaply anymore due to market saturation...Older but still rather ballsy desktop multiprocessor machines like Ultra2s can be had for twenty bucks. Why bother fighting with a PC? -Dave -- Dave McGuire Cape Coral, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Footprints, pins with 0x09 type
Hello, there exists a few footprints which define mounting holes with 0x09 id. This seems to indicate a mounting hole without copper area and is used for example for the CON_USB_TYPEB__Keystone_924 connector created by John Luciani: Element[0x0 CON_USB_TYPEB__Keystone_924 23700 59000 0 -7000 0 100 0x0] ( Pin[18800 59000 6600 2000 8600 4600 1 0x01] Pin[28600 59000 6600 2000 8600 4600 2 0x01] Pin[28600 51200 6600 2000 8600 4600 3 0x01] Pin[18800 51200 6600 2000 8600 4600 4 0x01] Pin[0 40500 11000 2000 13000 11000 5 0x09] Pin[47400 40500 11000 2000 13000 11000 6 0x09] ElementLine[0 34500 0 0 1000] ElementLine[0 0 47400 0 1000] ElementLine[47400 0 47400 34500 1000] ElementLine[0 46500 0 64000 1000] ElementLine[0 64000 47400 64000 1000] ElementLine[47400 64000 47400 46500 1000] ElementArc[0 40500 6000 6000 0 360 1000] ElementArc[47400 40500 6000 6000 0 360 1000] ) Datasheet of this device is: http://www.keyelco.com/products/specs/spec144.asp Is this type of mounting hole for fixating the device without soldering? (Only bending the metal?) Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Current source rail blocking
Karel Kulhavy wrote: Hello In my broadband high sensitivity amplifier I have a rail where bases of all current source transistors are hooked up. Each current source is a transistor with an emitter resistor which compensates variance in aplification so that even unmatched transistors produce matched currents. If you think the resistor is picking up RF, then you would need a box shield more than caps... or cap at the resistor would be more eff than at rail since RC damped. John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: solder bridges in gschem and pcb
On Sunday 29 October 2006 12:48, Stefan Salewski wrote: what is the best way to handle solder bridges (Lötbrücken in german) in gschem and pcb. Small Zero Ohm resistors. These connections can be removed easlly by removing this drop using a clean hot soldering iron. This allows to use a device in different modes. Depending on how many, and how complex the (re)configuration maybe, it is usually more expedient to use the Zero Ohm resistors. With a good solder mask it can be hard to get the pads to bridge, and you spent more on labor time than you would have on the resistor. -- http://www.softwaresafety.net/ http://www.designer-iii.com/ http://www.unusualresearch.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprints, pins with 0x09 type
Is this type of mounting hole for fixating the device without soldering? (Only bending the metal?) Some devices have plastic clips or screw mounts that use those holes. For screw mounts, you might want to avoid the less-flat surface that HASL leaves, for example. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprints, pins with 0x09 type
On 10/29/06, Stefan Salewski [EMAIL PROTECTED] wrote: Hello, there exists a few footprints which define mounting holes with 0x09 id. This seems to indicate a mounting hole without copper area and is used for example for the CON_USB_TYPEB__Keystone_924 connector created by John Luciani: Element[0x0 CON_USB_TYPEB__Keystone_924 23700 59000 0 -7000 0 100 0x0] ( Pin[18800 59000 6600 2000 8600 4600 1 0x01] Pin[28600 59000 6600 2000 8600 4600 2 0x01] Pin[28600 51200 6600 2000 8600 4600 3 0x01] Pin[18800 51200 6600 2000 8600 4600 4 0x01] Pin[0 40500 11000 2000 13000 11000 5 0x09] Pin[47400 40500 11000 2000 13000 11000 6 0x09] ElementLine[0 34500 0 0 1000] ElementLine[0 0 47400 0 1000] ElementLine[47400 0 47400 34500 1000] ElementLine[0 46500 0 64000 1000] ElementLine[0 64000 47400 64000 1000] ElementLine[47400 64000 47400 46500 1000] ElementArc[0 40500 6000 6000 0 360 1000] ElementArc[47400 40500 6000 6000 0 360 1000] ) Datasheet of this device is: http://www.keyelco.com/products/specs/spec144.asp Is this type of mounting hole for fixating the device without soldering? (Only bending the metal?) Those probably should be pins not mounting holes. The datasheet states that the tabs are snap-in solder tails that hold the connector in place for wavesoldering (which will solder the pins and the tabs). You may want to chnge the flag from 0x09 to 0x01 and add two pins to your gschem symbol (for the case connection). (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: solder bridges in gschem and pcb
On 10/29/06, DJ Delorie [EMAIL PROTECTED] wrote: I'd use a pair of rectangular pads, close together. PCB has no way of making half-rounds, or splitting a pad, or using polygons for pads. The 01005 from your challenge board must be pretty close to a solder bridge already ;-) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: solder bridges in gschem and pcb
The 01005 from your challenge board must be pretty close to a solder bridge already ;-) They're about 7.5 mil gap between the pads, but the pads themselves are too small to reliably support a large solder blob (they're only 11x13 mil). They seem to manage anyway sometimes ;-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: net attribute placement
On Sat, 28 Oct 2006 21:35:08 +0200, Carlos Nieves Ónega wrote: This seems something to do with the automatic placement of attributes feature. However, this new feature only works with objects (yet). Maybe we could add a new hook for nets. Would be appreciated by users who like to name their nets. Alternatively, is it possible to introduce 50 units of vertical offset to attribute placement? Net attributes or object attributes? I meant the net attribute. 50 units seems to be a nice distance from net attribute to net. If you mean object attributes, you can use the automatic placement of attributes. This feature is disabled by default, but you can enable it in your system-gschemrc file, or your gschemrc file. Sound like fiddling with attributes after rotation may not be necessary anymore. I'll be pleased a lot, if this really works. Thank you for hinting. ---(kaimartin)--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Current source rail blocking
Karel Kulhavy wrote: Hello In my broadband high sensitivity amplifier I have a rail where bases of all current source transistors are hooked up. Each current source is a transistor with an emitter resistor which compensates variance in aplification so that even unmatched transistors produce matched currents. Do you have any recommendations how to block the current sources from picking up some garbage from the air and causing oscillation? Should I block the rail with a single big capacitor against the ground, or use individual capacitor for each transistor placed between emitter and base? What sort of transistors are these? Are you seeing oscillations in practice or is this just a concern prior to seeing any real hardware? I'd avoid using transistors which are faster than need be. For example, sticking a 20 GHz device in there may not be a good idea. If you can tolerate some additional noise, you can stick some resistance in series with the base if the transistors themselves are oscillating. If you have some extra capacitance on the emitter and some inductance in the base circuit (without much extra resistive loss), then it's not too hard to build an oscillator. Without knowing some more details anything else would be pure speculation. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
