Re: gEDA-user: about DJ

2006-11-06 Thread DJ Delorie

 I forgot DJ's web URL, so did a google search.  Here's what turned up:
 
 http://en.wikipedia.org/wiki/DJ_Delorie
 
 Pretty cool, DJ.  How'd you get in there?

Don't know.  I know djgpp's been in there for a while.


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Re: gEDA-user: PCB's at 10 GHz or 2.5THz?

2006-11-06 Thread Karel Kulhavy
On Sun, Nov 05, 2006 at 03:57:13PM -0500, Bob Paddock wrote:
 
 Someone asked me if I could do a PCB layout for them
 at 10 GHz.  I know there are a lot of very expensive packages
 out there for doing this kind of thing, those are not in my budget.
 
 How high a frequency has anyone here done?  Any tips or
 suggestions to offer?
 
 Anyone doing anything in the THz range yet (yes, that is a 'T')?

I have done 480THz. But it gets demodulated soon at the beginning of the
signal path.

CL
 
 
 -- 
  http://www.softwaresafety.net/ http://www.designer-iii.com/
  http://www.unusualresearch.com/
 
 
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Re: gEDA-user: no pins in JUMPER10

2006-11-06 Thread Giorgenes Gelatti

I didn't put footprints in some components becouse I didn't get any
error about that. They seem to have a default footprint already.
Is it a problem to leave the default footprints?

2006/11/6, John Luciani [EMAIL PROTECTED]:

On 11/5/06, Giorgenes Gelatti [EMAIL PROTECTED] wrote:
 i'm sending my project. it's very simple.
 Thank you.

One big problem is that a number of your components do not footprints.
For example ---
max1, max2, trans1, uc1. The majority of your connections go to these devices.

You need to pick the appropriate footprints for the devices that you are using.

(* jcl *)

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Re: gEDA-user: replicating pcb layout cells

2006-11-06 Thread John Luciani

On 11/5/06, John Griessen [EMAIL PROTECTED] wrote:

 The script works fine with the latest element file
format even though he made it before it existed.


Thats because the (x,y) data for each type of record type (Element,
Line, .. etc)
is in the same position in the record and all other data is output verbatim.
This could break if the  file format changes. If this happens you could
modify the Pt_fields hash to accept the new format or to accept
multiple formats.



Thanks John L,



Your welcome.

(* jcl *)

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Re: gEDA-user: PIC TQFP symbol

2006-11-06 Thread Vaughn Treude

Mark Rages wrote:

On 11/4/06, Vaughn Treude [EMAIL PROTECTED] wrote:

John Luciani wrote:
 On 11/4/06, Vaughn Treude [EMAIL PROTECTED] wrote:
 Hello all:
 Excuse me if I've missed this in some obvious place, but I can't 
find a

 symbol in standard library for the TQFP version of the PIC18F4420.  I
 know that other gEDA contributors sometimes keep symbols on their own
 sites.  Does anyone have one already done?
 Thanks!
 Vaughn Treude

 I have a footprint which *may* work ---

 QFP-80P-1380L1-1380L2-44N

 0.8mm pitch, 13.8mm lead span, 44 pins

John,
Thanks, but what I was really looking for was the symbol with the TQFP
pinout, which is different than the DIP-40 pinout.
Vaughn



It's not too hard to make your own using djboxsym.
http://www.gedasymbols.org/user/dj_delorie/tools/djboxsym.html



Mark,
Thanks for the suggestion.  I did already make my own, by copying the 
file for the DIP-40 part and changing it, mostly by editing the text in 
emacs and then by moving stuff around in gschem.  Next time I'll have to 
check out djboxsym.

Vaughn


If you don't want to install it, try the interactive interface I made:
http://vivara.net/cgi-bin/djboxsym.cgi

Regards,
Mark
[EMAIL PROTECTED]




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Re: gEDA-user: replicating pcb layout cells

2006-11-06 Thread bumpelo
   The script works fine with the latest element file
  format even though he made it before it existed.
 
 Thats because the (x,y) data for each type of record type (Element,
 Line, .. etc)
 is in the same position in the record and all other data is output verbatim.
 This could break if the  file format changes. If this happens you could
 modify the Pt_fields hash to accept the new format or to accept
 multiple formats.

I'm not sure what your script does, but I would think that the real
because reason is that pcb is fully capable of reading all old format
data. It doesn't matter what new file formats look like so long as
you aren't trying to use new features, write in one format and pcb
will always be able to read it.


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Re: gEDA-user: replicating pcb layout cells

2006-11-06 Thread John Luciani

On 11/6/06, [EMAIL PROTECTED] [EMAIL PROTECTED] wrote:

   The script works fine with the latest element file
  format even though he made it before it existed.

 Thats because the (x,y) data for each type of record type (Element,
 Line, .. etc)
 is in the same position in the record and all other data is output verbatim.
 This could break if the  file format changes. If this happens you could
 modify the Pt_fields hash to accept the new format or to accept
 multiple formats.

I'm not sure what your script does, but I would think that the real
because reason is that pcb is fully capable of reading all old format
data. It doesn't matter what new file formats look like so long as
you aren't trying to use new features, write in one format and pcb
will always be able to read it.


Not correct. The because reason relates to the ability of my program to
input a new file format (for which it wasn't designed) and output a correct
PCB layout not PCB's ability to read new and old file formats.

(* jcl *)

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Re: gEDA-user: no pins in JUMPER10

2006-11-06 Thread Giorgenes Gelatti

I got a simpler circuit that is not working.
I have snap turned on, but can't see a way of making it works :(


2006/11/6, John Luciani [EMAIL PROTECTED]:

On 11/6/06, Giorgenes Gelatti [EMAIL PROTECTED] wrote:
 I didn't put footprints in some components becouse I didn't get any
 error about that. They seem to have a default footprint already.
 Is it a problem to leave the default footprints?

The schematic you posted, programmer.sch, did not have footprints for
the components for max1, max2, trans1, uc1 (there may be others).

Select the component, right-click and go to the edit menu. The only attribute
that is set is refdes.

(* jcl *)


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db2bar.sch
Description: Binary data


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Re: gEDA-user: replicating pcb layout cells

2006-11-06 Thread John Griessen



John Luciani wrote:


   The script works fine with the latest element file
  format even though he made it before it existed.

 Thats because the .

.
.
.
 On 11/6/06, [EMAIL PROTECTED] [EMAIL PROTECTED] wrote:

I'm not sure what your script does, but I would think that the real
because reason is 

.
.
.

Not correct. The because reason relates to the ability

.
.
[jg]Both of you have made code that's change tolerant.  Congratulations!

John G


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Re: gEDA-user: furnace controller I/O port again

2006-11-06 Thread Greg Cunningham
On Fri, 2006-11-03 at 15:36, DJ Delorie wrote:
  Which frequently gets people into trouble when they try to use
  Op-Amps as Comparators:
...
 The lines will (initially, at least) carry 1wire (1-15 uS pulses) and
 RS-232 (9600 baud).
...
DJ, Are you writing code for the Dallas 1-wire protocol?  Neat.  

I cheated.  
I used a PICAXE for my heat pump (Oz-talk for HVACs?) until I get to
develop PIC-level code.  I want to talk to 3x Dallas Temp sensors  soft
start my duct fan (phase controlled start of a MOC30xx-coupled triac). 
Sigh, as usual, THe S/S+N ratio in my life is too high,  I will live
with the PICAXE for another year or so.
-- 
Greg


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Re: gEDA-user: no pins in JUMPER10

2006-11-06 Thread John Luciani

On 11/6/06, Giorgenes Gelatti [EMAIL PROTECTED] wrote:

I got a simpler circuit that is not working.
I have snap turned on, but can't see a way of making it works :(



What specifically isn't working?

the netlist produced ---

unnamed_net9serial-2 pinbar-9
unnamed_net8serial-1 pinbar-10
unnamed_net7serial-4 pinbar-7
unnamed_net6serial-6 pinbar-5
unnamed_net5serial-8 pinbar-3
unnamed_net4serial-3 pinbar-8
unnamed_net3serial-5 pinbar-6
unnamed_net2serial-7 pinbar-4
unnamed_net1serial-9 pinbar-2

which is all of the connections. I do not have the same set of footprints so I
did not check out a PCB file.

(* jcl *)

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Re: gEDA-user: furnace controller I/O port again

2006-11-06 Thread ldoolitt
Friends -

On Mon, Nov 06, 2006 at 07:08:48PM -0500, DJ Delorie wrote:
  DJ, Are you writing code for the Dallas 1-wire protocol?  Neat.  
 Lots of bit banging.

If anyone wants FPGA code for 1-Wire, I have some.  You can
either click through the stupid (but innocuous) licence
agreement at http://recycle.lbl.gov/llc-suite/, or e-mail me.

I have two versions: one is a very simple one-bit transfer,
minimal gates, but takes the real-time burden off the host
computer.  The other does enough sequencing to read a temperature
from a DS1822; all the computer has to do is write the stimulus
message to the FPGA at the beginning, wait 750 ms, and read the
response message at the end.  With C code, tested in hardware,
and including a simulation test bench set up to do regression testing.

- Larry


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gEDA-user: Open SDSL project mailing list

2006-11-06 Thread Michael Sokolov
Since a number of people here have found my open SDSL connectivity
project interesting, I have set up a mailing list for it so that the
interested people can discuss it without cluttering this and other lists
with OT posts.  Send subscription requests to:

[EMAIL PROTECTED]

It's also listed on the project home page:

http://ifctfvax.Harhan.ORG/OpenSDSL/

MS


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