Re: gEDA-user: ratsnest and auto DRC also a bit about poly features was www.66each.com
--- Ben Jackson [EMAIL PROTECTED] wrote: ... I would like the ratsnesting to work in a sane fashion and I'd like auto DRC to let me actually draw traces to pads in the same net... Please explain what is not sane about the rats nest. The auto DRC prevents making connections that alter the network so it will stop you from connecting nets that aren't already connected (with a rat line). pcb doesn't work like a lot of tools and it is intended to be that way. Many people use it without ever creating a netlist for example. It will let you draw arbitrary copper whever you like. It does not mode you in nearly as much as most commercial offerings. It doesn't absolutely require a high end computer to be useful - some people use it successfully on 10 year old computers. These things have their disadvantages as well as their advantages. I'd like to see the feature set have the best of both worlds. I like the idea of having a command to assign a polygon to a net for example ( automagically setting thermals, joins and clearances of objects within it), but I don't want it to be *required* in order to place a polygon. Do you Yahoo!? Everyone is raving about the all-new Yahoo! Mail beta. http://new.mail.yahoo.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
I've used pcbfabexpress many times, both for double sided and 4 layer boards. Not a single problem so far. I used Advanced Circuits only once because their intro offer was good(check out their first $500 free offer). Otherwise Advanced Circuits is way more expensive than just about everyone else I've looked at. Company name can exist for ~$150 in just about any state in the US. Just file an LLC with the state and you are good to go. Usually there's a $25 maintenance fee every year there on out. From: DJ Delorie [EMAIL PROTECTED] Reply-To: gEDA user mailing list geda-user@moria.seul.org To: geda-user@moria.seul.org Subject: Re: gEDA-user: www.66each.com Date: Tue, 13 Feb 2007 02:10:53 -0500 I've recently been shopping for 4 layer options. I haven't tried any of them yet, but the ones that look promising are: http://www.protoexpress.com/content/noTouch.jsp About the same as above, except 60 sq in and 4 day lead for $51/ea (3 min). protoexpress auto-adds copper thieving, which would mess up my isolation gaps (I've emailed them asking about it). I wanted to go with pcbex, but they're closed for the next two weeks. Other vendors on my list are: pcbfabexpress (25 mil minimum SMT pitch) and pcbpool (good if you only need one). BatchPCB.com recently added a 4-layer option, but the cost for my board is higher than the others. And there's an intro offer at www.pcbnet.com for 4 layer 60 sq in, $50 with no minimum. But it is an intro offer... And... company name required ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user _ Dont miss your chance to WIN 10 hours of private jet travel from Microsoft Office Live http://clk.atdmt.com/MRT/go/mcrssaub0540002499mrt/direct/01/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
Oh absolutely. It's just a matter of whether the capabilities, the open nature and the low, low price are enough to overcome the bugs and the, uh, quirks of the user interface. I'm not likely to use 53 layers and a 40 acre board, but I would like the ratsnesting to work in a sane fashion and I'd like auto DRC to let me actually draw traces to pads in the same net... Please be specific about which version and what bugs, as we're doing a lot of work on it these days and bugs are getting fixed all the time. The problems you see may already be fixed in the CVS version, or perhaps we need to work on documenting how some of our features work. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
Otherwise Advanced Circuits is way more expensive than just about everyone else I've looked at. I'm willing to pay a little more for a better company, when it's worth it. Company name can exist for ~$150 in just about any state in the US. Just file an LLC with the state and you are good to go. Usually there's a $25 maintenance fee every year there on out. $150 to get a one-time deal on a PCB, isn't a deal. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
Check the prices from Advanced Circuits, it isn't a little more It's $66 per board. $198 total for 3 boards minimum. Hence the subject line. Compared to $150-165 for 3-5 boards elsewhere, it's not that much more. If you want to compare apples to apples, compare AP's full prototyping service to the other guy's full service. Me, I'm comparing their specials. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: any tool for LVS
Hi All, Can you please suggest any tool (Free software) for doing LVS or netlist to netlist comparision? Thanks Raghu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any tool for LVS
I haven't tired it, but there is this: http://opencircuitdesign.com/netgen/ It allegedly works with Magic and XCircuit (not gEDA, but open-source). Stuart On Tue, 13 Feb 2007, Raghu Kodali wrote: Hi All, Can you please suggest any tool (Free software) for doing LVS or netlist to netlist comparision? Thanks Raghu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
protoexpress auto-adds copper thieving, which would mess up my isolation gaps (I've emailed them asking about it). What is copper thieving? I wanted to go with pcbex, but they're closed for the next two weeks. Other vendors on my list are: pcbfabexpress (25 mil minimum SMT pitch) and pcbpool (good if you only need one). Everyone who sends their boards to Taiwan or China will be closed the next 2 weeks -- its Chinese New Year. Matt ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
What is copper thieving? They add small copper squares to otherwise bare areas to even out the electroplating. Everyone who sends their boards to Taiwan or China will be closed the next 2 weeks -- its Chinese New Year. This is my bad luck - this is the second board in a row that the preferred vendor went on vacation just as I needed to send out a board. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gedasymbols.org lost/stopped serving a cvs user account (kind of)
Hi DJ, I was adding some new PCB footprints I made yesterday and noticed my cvs account does not show up now on gedasymbols.org. The cvs commit I did went without error messages though...and update -d worked and mentioned a new dir created for footprints... hmmm... John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gedasymbols.org lost/stopped serving a cvs user account (kind of)
Looks like you used a WYSIWYG editor for the index.html, which tossed out the standard first line. That's what the script looks for. I.e. the very first line of your index.html must look like this: !--#set var=title value=DJ Delorie -- (with your name, of course). All the DTD stuff can go after it. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: wasteful for all gEDA users to be doing footprint libraries separately
Mark Rages wrote: It seems wasteful for all gEDA users to be doing this. (I also realize that footprint library maintenance is hard work, and I'm not volunteering.) We've talked of ways to set up some hard system that helps raise the trustworthiness of footprints. Would you please review the past archives on it and suggest some new ideas? Most of the ideas are about checklists that people sign when they do a test like send a board to fab and assemble it successfully. Another step to verifying a footprint is comparing against the datasheet package drawing somehow. It gets tricky with surface mount parts where hot air reflow might work differently and best use a different pad shape than IR reflow assembly. Make a specific suggestion. It won't go ignored here. John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: tested library of popular footprints.
Kai-Martin Knaak wrote: I think a board design application should come with a tested library of popular footprints. ack. It should be like that. But alas, The collection at geda-symbols.org is a good idea, too. I will contribute my share, once my I like the gedasymbols.org concept. Almost no rules, so anyone can use it. What if we made some easy to copy page frame or section that is a mini Wiki, for the purpose of adding use test results to footprints? It should be compact and not open a whole other page, but expand in the right column next to one of the footprints only when asked for. It could contain cells for kinds of tests, dates and signatures of some sort. John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: footprint bugs
Mark Rages wrote: I trust only footprints I made myself and triple checked It seems wasteful for all gEDA users to be doing this. Yes, if there are errors, there should be a bug filed in the tracker at pcb.sf.net. That's what I did when I encountered footprint bugs, and they were fixed quickly. I'd like an effort reducing hard system to help this. m4 footprints are still cluttered and I can't even figure how to remove them from my library window easily. Suggestions for dealing with them have been like, delete m4 dir before compiling' That loses the ged- set of footprints, which are good... John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: newlib footprints ==manageable list of dirs in the library window.
Dan McMahill wrote: My comment about it being strange that people trusted newlib footprints more than m4 generated footprints was based on A big thing about newlib footprints is you can delete them, move them around, and organize the dirs that show up in the library window. For the m4's this is a lot of compile changes, so I have never done it I like the idea of runing m4 at compile and then having only newlib footprints, which you could delete whole dirs of, and have a manageable list of dirs in the library window. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
On Feb 13, 2007, at 12:10 AM, DJ Delorie wrote: And there's an intro offer at www.pcbnet.com for 4 layer 60 sq in, $50 with no minimum. But it is an intro offer... And... company name required So make up a company name. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
RE: gEDA-user: Re: LED 100 != 5mm LED ?
On Sun, 11 Feb 2007 22:47:30 -0500, Dan McMahill wrote: and for some bizarre reason people seem to trust newlib footprints more apparently just because they don't use m4 at runtime. I trust only footprints I made myself and triple checked for consistency with the specs. Is this bizarre? Agreed. I also trust only my footprints and triple check for consistency with the specs. Additionally, I have chosen the newlib format for making my footprints which is believe is a good choice since gEDA is moving towards newlib files. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: tested library of popular footprints.
What if we made some easy to copy page frame or section that is a mini Wiki, for the purpose of adding use test results to footprints? It should be compact and not open a whole other page, but expand in the right column next to one of the footprints only when asked for. It could contain cells for kinds of tests, dates and signatures of some sort. If we can get the rules figured out, I could probably implement this. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
RE: gEDA-user: Re: LED 100 != 5mm LED ?
-Original Message- From: [EMAIL PROTECTED] [mailto:geda-user- [EMAIL PROTECTED] On Behalf Of Mark Rages Sent: Monday, February 12, 2007 5:29 PM To: gEDA user mailing list Subject: Re: gEDA-user: Re: LED 100 != 5mm LED ? On 2/12/07, Kai-Martin Knaak [EMAIL PROTECTED] wrote: I trust only footprints I made myself and triple checked for consistency with the specs. Is this bizarre? It seems wasteful for all gEDA users to be doing this. Wouldn't you find this bizarre: I print only with fonts I made myself and triple checked for consistency. If I said that, you might consider me a control freak with too much time on my hands. For similar reasons, I think a board design application should come with a tested library of popular footprints. Now, having been burned a couple times by broken footprints in pcb, I now check closely before sending the board off. I think we can agree that this is an undesirable situation. (I also realize that footprint library maintenance is hard work, and I'm not volunteering.) Assuming you created a perfect footprint for your PCB application with zero errors, does not equate to that same footprint being exactly perfect for my application. Depending on board population techniques, there could be a wide variance into what an acceptable pad excess should be. If I am soldering at home without a microscope, I may want 50-80 mils of excess pad to help facilitate soldering. If I have access to my company's scopes, then 10-40 mills might be needed depending on the pitch of the part. Pick and place and I may want no excess to help pack parts. Bottom line, its tough to come up with a one size fits all footprint IMHO. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
Andy Peters wrote: And... company name required So make up a company name. I do business with a local county dba name as a sole prop. and have no trouble with importing from Taiwan, or getting chip co. samples... or work done by 4pcb.com. Just get a .com email address to go with the bus.name you use. John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
On Feb 13, 2007, at 8:37 AM, DJ Delorie wrote: Oh absolutely. It's just a matter of whether the capabilities, the open nature and the low, low price are enough to overcome the bugs and the, uh, quirks of the user interface. I'm not likely to use 53 layers and a 40 acre board, but I would like the ratsnesting to work in a sane fashion and I'd like auto DRC to let me actually draw traces to pads in the same net... Please be specific about which version and what bugs, as we're doing a lot of work on it these days and bugs are getting fixed all the time. The problems you see may already be fixed in the CVS version, or perhaps we need to work on documenting how some of our features work. One bug/annoyance I can think of is when moving a footprint, with rats-nest enabled, the rats-nest lines don't move smoothly with the footprint. After you drop the part in the new location, you have to zoom in or out to clean up the rats-nest. I'm on PCB version 20060822 (the latest in fink) on OS X 10.4.8 on Intel. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
[EMAIL PROTECTED] writes: Just get a .com email address to go with the bus.name you use. Like, delorie.com? And I've been paying taxes through delorie software for years. It's not the get a company name that's the problem (I've got one), it's the companies that aren't geared towards individuals that are. It's a minor point, though. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
RE: gEDA-user: www.66each.com
Check the prices from Advanced Circuits, it isn't a little more the last time I checked, it's a lot more, like 2-3 times the price of everyone else in that space. The original quote for 5 pieces of a 4 layer board was like $550 from Advanced Circuits, I can get the same deal from pcbfabexpress for $180(and this was for the same turn). Which makes me wonder where they are getting their business from. If they are at the high end of the quality space then that explains it. Otherwise if they are a me too outfit then I am scratching my head. I threw out the LLC idea with the thought that perhaps you do some work for yourself(consulting or otherwise). An LLC is a nice little thing to protect you. I didn't propose it as a one off deal to help you get a cheaper board price. In any case you may try to float it anyway with a fictitious company name. When I did the first time deal with Advanced Circuits there really didn't appear to be any checking of the company even though I had a valid LLC. The worst that can happen is they say no, best case is they accept the order. Don't forget the tax write off of owning your own business ;) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
RE: gEDA-user: www.66each.com
-Original Message- From: [EMAIL PROTECTED] [mailto:geda-user- [EMAIL PROTECTED] On Behalf Of DJ Delorie Sent: Tuesday, February 13, 2007 9:26 AM To: geda-user@moria.seul.org Subject: Re: gEDA-user: www.66each.com What is copper thieving? They add small copper squares to otherwise bare areas to even out the electroplating. Why is this bad for your applications? Can you not just give them DRC for the squares and have them covered with soldermask? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: www.66each.com
Why is this bad for your applications? Can you not just give them DRC for the squares and have them covered with soldermask? It would be bad if they put them in the isolation gap between the high voltage side and the low voltage side. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
RE: gEDA-user: www.66each.com
-Original Message- From: [EMAIL PROTECTED] [mailto:geda-user- [EMAIL PROTECTED] On Behalf Of DJ Delorie Sent: Tuesday, February 13, 2007 10:30 AM To: geda-user@moria.seul.org Subject: Re: gEDA-user: www.66each.com And... company name required So make up a company name. My complaint was more philosophical than technical. I'm interested if you are sharing. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: minor PCB annoyance
Hi, When selecting a component from the Select Component dialog box, you must first use the TAB key or mouse click to bring focus to the Filter: edit line in order for the search to work properly. If you simply start typing in the Filter box without first manually bringing focus to the edit line, the text is accepted but nothing happens. I suspect this is one of those tricky focus problems that plague all GUI packages. Anyone else see this. By the way, thanks for all of the advice with the ground plane discussion; I did get the fill to work properly after changing a few options as suggested. Thanks, Ryan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC/rat quirks
On Tue, Feb 13, 2007 at 11:28:16AM -0700, Andy Peters wrote: On Feb 13, 2007, at 8:37 AM, DJ Delorie wrote: Ben Jackson wrote: but I would like the ratsnesting to work in a sane fashion and I'd like auto DRC to let me actually draw traces to pads in the same net... Please be specific about which version and what bugs One bug/annoyance I can think of is when moving a footprint, with rats-nest enabled, the rats-nest lines don't move smoothly with the footprint. After you drop the part in the new location, you have to zoom in or out to clean up the rats-nest. That's one. Another is that the rats for a net don't go away unless you can get your line to end exactly the right place, which doesn't work for me even with snap to pad. Also, the rat wire should give visual feedback as you route a net -- rats to routed pads should disappear as you place tracks that complete segments. As for the DRC, I've played with a few boards. Each time I end up with at least one rat wire going between two pads which I can't route because the auto-DRC won't let me onto the second pad. This might be related to the fact that my wire didn't start at the right place, despite it starting on the snap point that caused the new line to exactly cover the rat... There's another thread going on where someone is concerned about trusting a new feature in PCB when fabbing a board. Well, it's all new to me, and I don't know if I trust it yet. Maybe it has fabulous internals and a quirky interface, or maybe the internals are just as quirky... I'm on PCB version 20060822 (the latest in fink) on OS X 10.4.8 on Intel. I'm on PCB version 20060822 (latest freebsd ports) on FreeBSD 4.9 on Intel, displaying to X.org. -- Ben Jackson AD7GD [EMAIL PROTECTED] http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: minor PCB annoyance
When selecting a component from the Select Component dialog box, That would be in gschem, not pcb? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC/rat quirks
That's one. Another is that the rats for a net don't go away unless you can get your line to end exactly the right place, which doesn't work for me even with snap to pad. I'd like to see a test case for this. Also, the rat wire should give visual feedback as you route a net -- rats to routed pads should disappear as you place tracks that complete segments. With the lesstif HID, you could call the rats-optimize action on each mouse button release ;-) As for the DRC, I've played with a few boards. Each time I end up with at least one rat wire going between two pads which I can't route because the auto-DRC won't let me onto the second pad. It's also sensitive to which side you started on. Start on the pad that's already wired in, and connect to the one that isn't. Also check your netlist. Still, a test case would help. Me, I don't use auto-drc. I use the 'o' key to tell me when I screwed up, plus the 'f' key to highlight what I'm *supposed* to be routing to. There's another thread going on where someone is concerned about trusting a new feature in PCB when fabbing a board. Because the postscript and pdf prints, on screen, have faint lines between slices, and I didn't know if the DRCbots were going to complain about them. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: minor PCB annoyance
DJ Delorie wrote: When selecting a component from the "Select Component" dialog box, That would be in gschem, not pcb? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user Yes, you are right; it is gschem. Ryan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: footprint bugs
On 2/13/07, [EMAIL PROTECTED] [EMAIL PROTECTED] wrote: Mark Rages wrote: I trust only footprints I made myself and triple checked It seems wasteful for all gEDA users to be doing this. Yes, if there are errors, there should be a bug filed in the tracker at pcb.sf.net. That's what I did when I encountered footprint bugs, and they were fixed quickly. I'd like an effort reducing hard system to help this. m4 footprints are still cluttered and I can't even figure how to remove them from my library window easily. Suggestions for dealing with them have been like, delete m4 dir before compiling' That loses the ged- set of footprints, which are good... John G Don't the geda footprints refer to the other ones? Regards, Mark [EMAIL PROTECTED] -- You think that it is a secret, but it never has been one. - fortune cookie ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: wasteful for all gEDA users to be doing footprint libraries separately
On 2/13/07, [EMAIL PROTECTED] [EMAIL PROTECTED] wrote: Mark Rages wrote: It seems wasteful for all gEDA users to be doing this. (I also realize that footprint library maintenance is hard work, and I'm not volunteering.) We've talked of ways to set up some hard system that helps raise the trustworthiness of footprints. Would you please review the past archives on it and suggest some new ideas? Most of the ideas are about checklists that people sign when they do a test like send a board to fab and assemble it successfully. Another step to verifying a footprint is comparing against the datasheet package drawing somehow. It gets tricky with surface mount parts where hot air reflow might work differently and best use a different pad shape than IR reflow assembly. Make a specific suggestion. It won't go ignored here. John G My suggestion was in the other message: Yes, if there are errors, there should be a bug filed in the tracker at pcb.sf.net. That's what I did when I encountered footprint bugs, and they were fixed quickly. So maybe rather than a heroic effort to proofread all the footprints, we should encourage users to file bugs on them if they find a problem. Then the offending footprints can be fixed or removed. I have more ideas. I'll post again when they are more fully formed. Regards, Mark [EMAIL PROTECTED] -- You think that it is a secret, but it never has been one. - fortune cookie ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: changes to 0603 footprint?
At some point the 0603 footprint in the CVS version of PCB lost the silkscreen rectangle around it. Is there any reason it went away? Was this intentional? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC/rat quirks
Ben Jackson wrote: There's another thread going on where someone is concerned about trusting a new feature in PCB when fabbing a board. Well, it's all new to me, and I don't know if I trust it yet. Maybe it has fabulous internals and a quirky interface, or maybe the internals are just as quirky... The output from PCB is very predictable. I've always gotten accurate results from either my laser printer or the fab house. Never a problem. If you feel like the interface is odd, it is. It is raw. Because of this maybe there's a case for trusting it _more_? Phil Taylor ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: LED 100 != 5mm LED ?
Andy Peters wrote: On Feb 12, 2007, at 10:07 PM, Dan McMahill wrote: Andy Peters wrote: However, when an install of pcb comes with a warning that there are errors in the m4 libraries, yet doesn't say what footprints have errors (not to mention: why haven't these errors been fixed?), leads one to simply not trust the provided libraries at all. Could you point me to where that warning is? It needs to be updated. It's in the wiki: http://geda.seul.org/wiki/ geda:pcb_tips#how_do_pcb_s_footprints_work and I know I've seen it elsewhere. So this is funny. The 0805 footprint it talks about in the 'newlib' section has been deleted since it has a non-standard name and has not been verified against any real standard. The m4 library on the other hand has 3 tiered IPC conforming in name and footprint footprints for most of the 2 pin surface mount footprints like 0805's I doubt that whoever wrote that section actually looked at the libraries. In fact, I just took a look at the newlib footprint talked about there and I wouldn't use it. The pads have a larger gap and are narrower than any of the least/nominal/most material recommendations from IPC. Perhaps this proves my point that there seems to be a misguided trust of newlib and mistrust of pcblib footprints. Anyway, I've updated that section of the wiki to more accurately reflect the current state of affairs. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: changes to 0603 footprint?
Matt Ettus wrote: At some point the 0603 footprint in the CVS version of PCB lost the silkscreen rectangle around it. Is there any reason it went away? Was this intentional? yes. It was brought more inline with IPC footprints instead of the homegrown one that was there. With an 0603, there really isn't much room for silk. You'll see that silk is there on the larger ones, I think starting with maybe 1008 or 1206. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: changes to 0603 footprint?
Matt Ettus wrote: At some point the 0603 footprint in the CVS version of PCB lost the silkscreen rectangle around it. Is there any reason it went away? Was this intentional? yes. It was brought more inline with IPC footprints instead of the homegrown one that was there. With an 0603, there really isn't much room for silk. You'll see that silk is there on the larger ones, I think starting with maybe 1008 or 1206. FWIW, if you want a silk outline, you can always generate footprints using my little script called smtgen.pl, available from my website: http://www.brorson.com/gEDA/ It's a command line utility which outputs PCB footprints for SMT passives after you specify the various dimensions as command flags. It draws a silk outline. Also, John Luciani has SMT passives on his website with silkscreen outlines, here: http://www.luciani.org/geda/pcb/pcb-footprint-list.html#misc I'll betcha that there are some SMT passives with silk outlines on gedasymbols.org too. I just haven't looked. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb-20070208 snapshot
--- Dan McMahill [EMAIL PROTECTED] wrote: Hello, I have uploaded a new pcb snapshot to sourceforge. The change list fails to mention one of the new features is a change of cursor shape to visually indicate when the arrow tool will grab the end-point of a line before you grab it. Any questions? Get answers on any topic at www.Answers.yahoo.com. Try it now. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: changes to 0603 footprint?
I'll betcha that there are some SMT passives with silk outlines on gedasymbols.org too. I just haven't looked. http://www.gedasymbols.org/user/dj_delorie/tools/2pad.html ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Rotations, rotations, rotations.
--- Lares Moreau [EMAIL PROTECTED] wrote: No! it's not implemented yet. This is what I have started to implement. Let me know what you think. I think before putting much effort in to this, the patch contributed to sourceforge should be evaluated. From my looking at the patch itself I think the author covered almost everything that matters. Running it through Dan's test cases would be an important first step. I think that the autorouter will be unable to route to rotated pads unless the rotation is very small. It would be foolish to reinvent the wheel if it's mostly working. We won't tell. Get more on shows you hate to love (and love to hate): Yahoo! TV's Guilty Pleasures list. http://tv.yahoo.com/collections/265 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC/rat quirks
- That's one. Another is that the rats for a net don't go away unless you can get your line to end exactly the right place, which doesn't work for me even with snap to pad. That's pretty hard to believe. The connectivity is checked by a rigurous intersection test, no particular points are required, any touching will do. Implied in your statment is that after making a connection and optimizing the rats nest (o key), a rat line suggests the connection you just made is not making connection. I'd really like to see a test case because I've never seen this behavior ever. Also, the rat wire should give visual feedback as you route a net -- rats to routed pads should disappear as you place tracks that complete segments. Originally it took a fair amount of compute resources to trace the connectivity - it still can with very large boards so updating the whole rats nest automatically was never really considered. I think that most computers are fast enough now that its a viable idea to add an optional setting to optimize the rats nest after every move, track addition, track deletion etc. That would make the rat disappear as soon as the connection was made. As for the DRC, I've played with a few boards. Each time I end up with at least one rat wire going between two pads which I can't route because the auto-DRC won't let me onto the second pad. This might be related to the fact that my wire didn't start at the right place, despite it starting on the snap point that caused the new line to exactly cover the rat... This sounds like a bug. Send me a test case and I will solve it. Do the source and target turn green when you start the trace? Come to think of it this coupled with your rats nest failure above strongly suggests your layers aren't assigned the way you think they are. There was a release where some default layer names (which are nothing more than names and could well be foo and bar) were something like component and solder while they were actually grouped to the opposite side. Check your layer groupings. There's another thread going on where someone is concerned about trusting a new feature in PCB when fabbing a board. Well, it's all new to me, and I don't know if I trust it yet. Maybe it has fabulous internals and a quirky interface, or maybe the internals are just as quirky... pcb has a long history. For many years it was very stable and very reliable. This past year we have made so many sweeping changes including completely replacing all of the user interfaces and major changes to much of the code internals too. Some level of skeptisism is warranted because of this. With that said I think the latest snapshot release should be pretty stable. Any questions? Get answers on any topic at www.Answers.yahoo.com. Try it now. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC/rat quirks
Because the postscript and pdf prints, on screen, have faint lines between slices, and I didn't know if the DRCbots were going to complain about them. Strange. I'm sure the postscript is drawing those faint lines but they shouldn't be visible since they are on top of or beneath a solid fill. (The slices share a common edge where the line appears.) Does your printed postscript show those lines (or worse gaps)? Don't pick lemons. See all the new 2007 cars at Yahoo! Autos. http://autos.yahoo.com/new_cars.html ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC/rat quirks
Strange. I'm sure the postscript is drawing those faint lines but they shouldn't be visible since they are on top of or beneath a solid fill. (The slices share a common edge where the line appears.) Does your printed postscript show those lines (or worse gaps)? The prints appear OK. Both ghostview and acroread have faint white lines between the slices, and not always - it depends on the zoom factor. I suspect it's due to the antialiasing since it only happens when antialiasing is on, but it makes me wonder if these edges shouldn't be overlapped by a bit (1/100 thou?) or not. I also don't know what the fab's DRC/DFM would do with the thin slices or just-touching edges. gerbv seems to draw it OK too. I wouldn't have been too concerned about it except that these are internal layers on my board, so I can't visually inspect the results from the fab. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: footprint bugs
On Tue, 13 Feb 2007 13:47:42 -0500, Dan McMahill wrote: remind me again what it matters if they are removed or not removed from the pcb library window? If you don't bother to use them, they are a minor waste of screen real estate. Anyway, me thinks, the more important issue is how to make gsch2pcb ignore m4 libs. ---(kaimartin)--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC/rat quirks
For instance, you must turn it off if you are placing a via to connect traces to finish off a rats nest, even if the rats are displayed properly. Ok, I can reproduce this. PCB expects you to do something else. What it wants is for you to draw the line off the first pin, change layers, and continue drawing lines. It puts in the vias for you whenever you change layers. You should be able to connect to vias that are already connected to the net through other lines, though. It's just totally unconnected vias it's blocking. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: footprint bugs
Anyway, me thinks, the more important issue is how to make gsch2pcb ignore m4 libs. Dan added an option to ignore them, and enabled it by default. I immediately complained because my furnace controller broke - it uses many of the JEDEC standard footprints (0603, tssop16, etc), which are in the m4 library. I'm sure he'll chime in with what the new option and default will be :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: pcb-20070208 snapshot
On Tue, 13 Feb 2007 15:36:35 -0800, Harry Eaton wrote: The change list fails to mention one of the new features is a change of cursor shape to visually indicate when the arrow tool will grab the end-point of a line before you grab it. ... which is a major step ahead in terms of usability. I just finished manual routing of my laser driver and more than once had a hard time to find the end point. ---(kaiamrtin)--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: footprint bugs
On 2/13/07, DJ Delorie [EMAIL PROTECTED] wrote: Anyway, me thinks, the more important issue is how to make gsch2pcb ignore m4 libs. Dan added an option to ignore them, and enabled it by default. I immediately complained because my furnace controller broke - Disabling an option in PCB breaks your furnace??? What kind of a crazy heating system are you designing ;-) (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: footprint bugs
Kai-Martin Knaak wrote: On Tue, 13 Feb 2007 13:47:42 -0500, Dan McMahill wrote: remind me again what it matters if they are removed or not removed from the pcb library window? If you don't bother to use them, they are a minor waste of screen real estate. Anyway, me thinks, the more important issue is how to make gsch2pcb ignore m4 libs. There has always been the '--use-files' command line option or the use-files project file option. That still runs m4 but then replaces those footprints with newlib ones _if_ it can find any. There is a new option, '--skip-m4' for the command line and 'skip-m4' for the project file that never runs m4 at all. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: footprint bugs
Disabling an option in PCB breaks your furnace??? Dan reacted the same way, I've got to learn to describe it better. The new default broke the scripts that process my furnace board files, since it could no longer find the footprints it needed. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: footprint bugs
DJ Delorie wrote: Anyway, me thinks, the more important issue is how to make gsch2pcb ignore m4 libs. Dan added an option to ignore them, and enabled it by default. I immediately complained because my furnace controller broke - it uses many of the JEDEC standard footprints (0603, tssop16, etc), which are in the m4 library. I'm sure he'll chime in with what the new option and default will be :-) yep. After DJ pointed out that obvious principle of least suprise I dropped use-m4 which was the option to enable the old behaviour in favor of skip-m4 which is now the option to behave differently by never running m4. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: pcb-20070208 snapshot
Kai-Martin Knaak wrote: On Tue, 13 Feb 2007 15:36:35 -0800, Harry Eaton wrote: The change list fails to mention one of the new features is a change of cursor shape to visually indicate when the arrow tool will grab the end-point of a line before you grab it. ... which is a major step ahead in terms of usability. I just finished manual routing of my laser driver and more than once had a hard time to find the end point. Sorry about leaving that out. I create those notes by reading through the ChangeLog and trying to summarize it in about a page. This time around the ChangeLog was so long (nearly 2000 lines covering over 300 commits since the last snapshot) I had a bit of a hard time picking out which things were new and which things were improving performance or fixing bugs in things which were new. This one slipped through the cracks. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: footprint bugs
On 2/13/07, DJ Delorie [EMAIL PROTECTED] wrote: Disabling an option in PCB breaks your furnace??? Dan reacted the same way, I've got to learn to describe it better. The new default broke the scripts that process my furnace board files, since it could no longer find the footprints it needed. No self-respecting gEDA-gadfly, or Freedog-gadflea, could resist! (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: footprint bugs
On Tue, 13 Feb 2007 20:30:18 -0500, Dan McMahill wrote: There is a new option, '--skip-m4' for the command line and 'skip-m4' for the project file that never runs m4 at all. Thanks :^) ---(kaimartin)--- -- Kai-Martin Knaak http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: new footprints added at gedasymbols.org
I made some nice visual representations of mounting screws of the kind we usually hold a PCB to an enclosure with -- a philips head screw. http://www.gedasymbols.org/user/john_griessen/footprints/ They're not metric. I made no. 6,8, and 10 versions with the silkscreen sized for a loose tolerance in the PCB hole, but that hole size is actually up to you when you make the drill drawing, since the pin used in these is sized small to be a guide for a hand aimed drill press drilling job. These are intended for prototyping and small volume use -- not a finished accurate hole size as is. The philips head drawing is made with a 5 mils grid setting. It would be easy to copy the style, and maybe some of the content to make inch/metric versions and production versions with no small via to guide drills, but a via the size of the finished hole for NC drilling at a hired fab. John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gEDA code sprint and donations
Hi All, The fourth worldwide gEDA code sprint was held last Saturday (2007/02/10). It was quite successful (probably the best one yet) with many changes being checked in (I know I got lots done) and with 14 different people hanging out in irc (with probably all the core developers being online at one point or another) from around the world. We will certainly have another one, probably sometime in the month of April 2007. All details to be hashed out as we get closer to April. For those of you curious what happened and what was discussed be sure to check out the irc log that can be found at: http://geda.seul.org/sprints/irclog_sprint_20070210.txt Also, for those curious about the donation mechanism for the gEDA project discussed a while ago, I have finally turned on the SourceForge donation mechanism. The start page of this donation mechanism can be found at: http://sourceforge.net/project/project_donations.php?group_id=161080 Enjoy, -Ales ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
