gEDA-user: Re: Free ECB_AT91 actually isn't free
On 3/19/07, Karel Kulhavy <[EMAIL PROTECTED]> wrote: http://wiki.emqbit.com/free-ecb-at91 Hi Karel (you forgot to say hello). The licence is GPL and you are stating that the design is free, but it actually isn't. If anyone takes these files and distributes them further, he is violating the GPL, because GPL says that he has to give sources with them. But he can't even have them because the sources don't seem to be actually published. AFAIK from GPL point of view, source must be in a format that is the optimum one for editing. I think that saying that the board is not free, is a bold claim. We know of people who are trying to assemble the board. Now if we _did_ choose the GPL, we should have put the "true holy sources online", and you have a point here. We just released the sources of the version 1.6. We replaced the PHY, that was discontinued. We checked the design and we will try it really soon (PCBs are on their way). http://svn.arhuaco.org/svn/src/emqbit/free-ecb-at91/ In this case it's definitely not the Gerber. The actual sources is probably a file for Eagle or Orcad (neither of them being free software), judging by the graphical appearance of the schematics. We used Orcad. We would welcome any porting effort to a free tool. I wonder why you didn't design it in gEDA. I am using gEDA for Ronja design and Darrel Harmon (did you actually copy anything from his design?) designed also in gEDA. Carlos used the Reference Design from Atmel. And the Darrel design was a great source of inspiration and even support. Also, on the software side, now that you talk about the GPL, we'd like you to know that we did show the board to Richard Stallman when he came to Bogotá last year and he was concerned whether it had a free BIOS or not. Fortunately, we have an slightly improved version of the Darrell's loader online. http://svn.arhuaco.org/svn/src/emqbit/ECB_AT91_V2/darrell-loader/Changelog We don't have much free time in our hands. Carlos worked for free in this project and he is more productive with Orcad. Last year I thought Buildroot was better than OpenEmbedded, and Stefano, an Italian Engineer did show us otherwise by porting OE to the board. In the same spirit, If someone had the time to port the design to gEDA, we would love to publish it in our site and even use it for future projects. I think it's important to have a free tool for edition but are working on a lot of things now so we cannot do it ourselves this time. But talking about correctness, I think we fully honor the GPL now. I also wonder what you are trying to achieve with publishing only the gerbers and not the sources. If someone wants to manufacture the design in quantities, sell cheaper and decrease your sales, then it's easy for him as he has the gerbers. If someone wants to actually be creative and change the design, he cannot. You're right here. I hope the design if useful for someone. I'd love to see it ported to gEDA. We are working a lot to improve the documentaton in our site, and any help is more than welcome. I am not a hardware guy, so I work on the software side. The last thing we did is get 2.6.20 to work in the board. Now we need to send a lot of patches uptstream. Regards, Nelson.- BTW: We like the gEDA project. I was already in this mailing list. -- http://arhuaco.org http://emQbit.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
Dan McMahill wrote: how should PCB behave with a hierarchical schematic? by default for each cell to be an entity that you can grab and move around. The ability to visually toggle all hierarchical instances between the contents and a box is fairly useful. [jg]As in Cadence. To save on redraw time for big designs. If you want to edit the contents, you have to descend into the block to edit it. [jg] Some have hinted they want to create unnamed versions on the fly by doing this, but I like to keep the main reuse-identical-cells value at front and have the editing affect all placements of that same named cell. If I want to make a separate version of a layout instance, I have to save as some-new-name to get it. You almost certainly want a mode where when you descend you only see that block in its zero rotation as well as an edit in place mode where you edit the block while all the rest of the board is visible. I'm saying this based on having done quite a bit of hierarchical layout in the ic world. Haven't done it in the board world although I've wished for it a few times. [jg]And I think when organic printable semiconductors become more real, we will be wanting the IC layout style more and more. Our IC's will just be organic and naked-eye-visible is all... I'll add the visual toggle concept to the wiki, along with zero-rotation-as-in-the-orginal on edit by default. http://geda.seul.org/wiki/geda:design_flow_and_hierarchy_roadmap The other ideas Igor and DJ already asked for. And I second all those motions. John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
al davis wrote: * Finally, how should PCB behave with a hierarchical schematic? Right click on a symbol, select "go inside", and another drawing opens up showing what's inside. gschem also should act this way. I think what you want is by default for each cell to be an entity that you can grab and move around. The ability to visually toggle all hierarchical instances between the contents and a box is fairly useful. If you want to edit the contents, you have to descend into the block to edit it. You almost certainly want a mode where when you descend you only see that block in its zero rotation as well as an edit in place mode where you edit the block while all the rest of the board is visible. I'm saying this based on having done quite a bit of hierarchical layout in the ic world. Haven't done it in the board world although I've wished for it a few times. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: File corrupted after segmentation fault in pcb
Mikael W. Bertelsen wrote: Hi all! I tried out the gEDA package and I am very impressed! My thanks to all who contributed to this project! I created a layout in pcb and just needed the last finish before the board was done. Unfortunately I marked two rats nets together with my component which I wanted to delete. When I hit the delete button pcb gave me a segmentation fault, and now the layout file is corrupted. I know the layout file is ASCII, but as a first time user it is not trivial to repair the file. Therefore, I will ask any of you to help me repair the file. I have no auto-backup since this apparently does not work quite yet in pcb. auto-backup should be working in 20070208. Do you have a "msp430-eval.pcb-" file? Note the "-"? If not, how about /tmp/PCB.something? -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog with Xilinx simprims...
CSB wrote: If your design is purely combinatorial, then of course you will have glitches, and remember that a post-fit timing simulation will show you these glitches for the particular routing the tools just used, which may change for each place-and-route run as you tweak the design. Hmm. My design is a bit wacky... it's mostly clock-based, but also has a combinatorial part. I'll test what I have with a real CPLD, see if it'll work (or not). Good thing they're erasable, I feel it's not the last time I'm going to re-write it ! When they said warnings and "your on your own" that means when you make something "just barely function" and have no safety margin logically coming form the spec sheet of the parts you used, you do not know when it will or won't work, at which temperature, or on which individual part from the factory. John G ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: gEDA problems
People, Please ignore my last posting. It seems I had some kind of line-wrap problem in my project file for the "gsch2pcb" command. Once I got that corrected, the netlist appears to be correct and things look OK now. Sorry about the confusion, and I thank you people for a very usable product (perhaps I should say many usable products). Harold Skank ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA problems
Do your refdes's end in lower case letters? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gEDA problems
People, Seems like I've been here before, but I can't seem to remember the issues. As briefly as possible, the problem is that I have a large schematic, some 10 pages that include 8 large connectors, and 2 Xilinx, 1100 pin fpga's. Currently, the only net that I have connected is "GND." When I do "gsch2pcb" the scheme runs, but I'm missing the last page of connections. In addition, there seems to be a subset of connections missing from one of the fpga's (which should be identical to the first one). The last page (most of the missing connections) is a 4-slot memory connector. Originally, I thought that I must have an error in its construction, but treating that page separately, it seems to assemble properly under "gsch2pcb" so at this point it looks OK. Because of the size of this project, I'm concerned about the possibility of memory restrictions. Currently I am running with about 1 gigabyte of memory. Does anyone there have a feeling for what I might be facing here? Concerned gEDA user. Harold Skank ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog with Xilinx simprims...
> If you're doing an asynchronous design, then you're on your own! > Current CPLD and FPGA methodologies don't lend themselves well to > async design. > Certainly the fitted design will have glitches, as delays through > various paths will be different. The point of synchronous design is > that you can ignore those glitches; all you care about is if the > inputs to all of your registers are settled by the setup time before > the clock edge. And for each clock, that is what the static timing > analyzer tells you -- the length of all paths through all registers. > As long as the prop delay from register A through logic to the D > input of register B is less than the clock period, you win. The > timing analyzer accounts for register clock-to-out delay and register > input setup and hold. > If your design is purely combinatorial, then of course you will have > glitches, and remember that a post-fit timing simulation will show > you these glitches for the particular routing the tools just used, > which may change for each place-and-route run as you tweak the > design. Hmm. My design is a bit wacky... it's mostly clock-based, but also has a combinatorial part. I'll test what I have with a real CPLD, see if it'll work (or not). Good thing they're erasable, I feel it's not the last time I'm going to re-write it ! > http://iverilog.wikia.com/wiki/Graffiti#SDF_support Quite interesting, thank you for the link. Thanks to all for the information, Christian -- CSB [EMAIL PROTECTED] -- http://www.fastmail.fm - A fast, anti-spam email service. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: installation
Stuart Brorson wrote: My experience has been that if you are missing some system dependencies, the first expect session will always fail, whether running as root or not. This may be unique to the openSuSe distributions, but I don't think so. It is more likely just an issue exposed by the fact that the openSuSe installations have less of the system dependencies installed out of the box. Maybe the SuSe distributions are the best way to test the installer :)? In general I do test on SuSE 9.3, 10.0 and 10.1, and the installer does work on those platforms. As for the dependency installation failing: I have seen failures due to several causes: * Users running as root. The expect session wants to see "assword:" when it tries to log in as root. If the user is already root, then the computer doesn't ask for a password. Therefore, the expect session just hangs, waiting for the "Password:" which never comes. Solution: Don't install as root. * Non-english users. This one was interesting. A German user had the expect session hang immediately after he started the dependency install. The reason was that his box asked for his password as "Passwort:", the German word. The expect session was waiting for "Password:". Therefore, it hung, waiting forever. I haven't done anything to fix this yet. The fix will be for the install wizard to set the local environment to English only upon startup. I haven't implemented this yet because I am not sure what kinds of problems that might cause (what happens if no English translations are installed?) Yikes! Thankfully I can only speak English (and that's on a good day). * The WTF catagory. In this catagory are some occasional, intermittant failures I see in my testing. I don't know exactly what causes them, but I suspect timing issues withing the call/response process of the expect session. With the last CD I upgraded the expect package, so I'm hoping this problem will just go away. But I haven't thoroughly verified that yet, either by verifying the design, or by rigorous testing. I'm just about to install on SuSe 10.2. I'll let you know what happens. Joe T Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: installation
My experience has been that if you are missing some system dependencies, the first expect session will always fail, whether running as root or not. This may be unique to the openSuSe distributions, but I don't think so. It is more likely just an issue exposed by the fact that the openSuSe installations have less of the system dependencies installed out of the box. Maybe the SuSe distributions are the best way to test the installer :)? In general I do test on SuSE 9.3, 10.0 and 10.1, and the installer does work on those platforms. As for the dependency installation failing: I have seen failures due to several causes: * Users running as root. The expect session wants to see "assword:" when it tries to log in as root. If the user is already root, then the computer doesn't ask for a password. Therefore, the expect session just hangs, waiting for the "Password:" which never comes. Solution: Don't install as root. * Non-english users. This one was interesting. A German user had the expect session hang immediately after he started the dependency install. The reason was that his box asked for his password as "Passwort:", the German word. The expect session was waiting for "Password:". Therefore, it hung, waiting forever. I haven't done anything to fix this yet. The fix will be for the install wizard to set the local environment to English only upon startup. I haven't implemented this yet because I am not sure what kinds of problems that might cause (what happens if no English translations are installed?) * The WTF catagory. In this catagory are some occasional, intermittant failures I see in my testing. I don't know exactly what causes them, but I suspect timing issues withing the call/response process of the expect session. With the last CD I upgraded the expect package, so I'm hoping this problem will just go away. But I haven't thoroughly verified that yet, either by verifying the design, or by rigorous testing. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
Igor2 wrote: On Sun, 18 Mar 2007, al davis wrote: * Finally, how should PCB behave with a hierarchical schematic? Right click on a symbol, select "go inside", and another drawing opens up showing what's inside. gschem also should act this way. I like this idea very much. In case of PCB it also would make sense to add a way to display in place what's inside. With an "expand all" functionality this would allow one to see the whole pcb with all inner structures at once, without needing to export to ps. The ability to "look inside" or "expand all" is a feature that is standard for IC layout editors. Years ago I used a PC board editor that evolved from an IC layout tool and it had this behavior. In particular, you could create sub-blocks of circuitry that might represent individual "devices" (or elements in PCB parlance) or more complex blocks that you might want to repeat. You could add these to your layout (with up to 256 levels of nesting). You could turn on/off the visibility or "editability" of any device at a lower or higher level of nesting than the one you were currently working in. When "editing down" to a lower level device it would leave all the surrounding features (the "context") visible so you see what you were doing. Other copies of the current block could be immediately displayed with the changes you just made. Needless to say, this implementation of heirarchy allowed for some very complex designs and much easier re-use than we have now. Joe T ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
> Couldn't resource file be used with the plugin mode of programming
> to extend function? Since it is LISP-ish it seems closest to a
> common file format language with gschem, which uses guile. Are
> there rumors of planning to stop using guile?
The resource file is purely data. Its primary benefits are that its
syntax is independent of its content, and the values are all strings.
Hence, you can put pretty much any data in it, and pcb can parse it.
Here's a copy of pcb-menu.res:
# -*- c -*-
# Note - pcb-menu.res is used to build pcb-menu.h
# Note - parameters are sensitive to extra spaces around the commas
Mouse =
{
Left = {
Mode(Notify)
up = Mode(Release)
}
Right = {
{ Mode(Save) Mode(Rotate) Mode(Notify) Mode(Release) Mode(Restore) }
}
Middle = {
Pan(1)
up = Pan(0)
ctrl = Pan(thumb,1)
ctrl-up = Pan(thumb,0)
}
Up = Zoom(0.8)
Down = Zoom(1.25)
# If you want zoom to center, do this instead.
#Up = { {Zoom(0.8) Center()} }
#Down = { {Zoom(1.25) Center()} }
}
MainMenu =
{
{File
{"About..." About()}
{"Save layout" Save(Layout)}
{"Save layout as..." Save(LayoutAs)}
{"Revert" Load(Revert,none)}
{"Load layout" Load(Layout)}
{"Load element data to paste-buffer" PasteBuffer(Clear)
Load(ElementTobuffer)}
{"Load layout data to paste-buffer" PasteBuffer(Clear) Load(LayoutTobuffer)}
{"Load netlist file" Load(Netlist)}
{"Load vendor resource file" LoadVendor()}
{"Print layout..." Print()}
{"Export layout..." Export()}
{"Calibrate Printer..." PrintCalibrate()}
-
{"Save connection data of..." foreground=grey50 sensitive=false}
{" a single element" GetXY(press a button at the element location)
Save(ElementConnections)}
{" all elements" Save(AllConnections)}
{" unused pins" Save(AllUnusedPins)}
-
{"Start new layout" New()}
-
{"Quit Program" Quit() m=Q a={"Ctrl-Q" "Ctrlq"}}
}
{View
{"Flip up/down" checked=flip_y SwapSides(V) a={"Tab" "Tab"}}
{"Flip left/right" checked=flip_x SwapSides(H) a={"Shift-Tab"
"ShiftTab"}}
{"Spin 180°" SwapSides(R) a={"Ctrl-Tab" "CtrlTab"}}
{"Swap Sides" SwapSides() a={"Ctrl-Shift-Tab" "Ctrl ShiftTab"}}
{"Center cursor" Center() a={"C" "c"}}
{"Show soldermask" checked=showmask Display(ToggleMask)}
-
{"Displayed element-name..." foreground=grey50 sensitive=false}
{"Description" Display(Description) checked=elementname,1}
{"Reference Designator" Display(NameOnPCB) checked=elementname,2}
{"Value" Display(Value) checked=elementname,3}
{"Lock Names" checked=locknames Display(ToggleLockNames)}
{"Only Names" checked=onlynames Display(ToggleOnlyNames)}
-
{"Pinout shows number" checked=shownumber Display(ToggleName)}
{"Open pinout menu" Display(Pinout) a={"Shift-D" "Shiftd"}}
-
{Zoom
{"Zoom In 2X" Zoom(-2)}
{"Zoom In 20%" Zoom(-1.2) m=Z a={"Z" "z"}}
{"Zoom Out 20%" Zoom(+1.2) m=O a={"Shift-Z" "Shiftz"}}
# If you want zoom to center, do this instead.
#{"Zoom In 20%" Zoom(-1.2) Center() m=Z a={"Z" "z"}}
#{"Zoom Out 20%" Zoom(+1.2) Center() m=O a={"Shift-Z" "Shiftz"}}
{"Zoom Out 2X" Zoom(+2)}
{"Zoom Max" Zoom() m=M a={"V" "v"}}
-
{"Zoom to 0.1mil/px" Zoom(=10)}
{"Zoom to 0.01mm/px" Zoom(=39.37)}
{"Zoom to 1mil/px" Zoom(=100)}
{"Zoom to 0.05mm/px" Zoom(=196.8504)}
{"Zoom to 2.5mil/px" Zoom(=250)}
{"Zoom to 0.1mm/px" Zoom(=393.7)}
{"Zoom to 10mil/px" Zoom(=1000)}
}
{Grid
{"mils" checked=grid_units_mm,0 SetUnits(mil)}
{"mms" checked=grid_units_mm,1 SetUnits(mm)}
{"Display grid" checked=drawgrid Display(Grid)}
{"Realign grid" GetXY(Press a button at a grid point) Display(ToggleGrid)}
{"No Grid" checked=gridsize,1 SetValue(Grid,1)}
-
{ "0.1 mil" checked=gridsize,10 SetUnits(mil) SetValue(Grid,10)}
{ "1 mil" checked=gridsize,100 SetUnits(mil) SetValue(Grid,100)}
{ "5 mil" checked=gridsize,500 SetUnits(mil) SetValue(Grid,500)}
{ "10 mil" checked=gridsize,1000 SetUnits(mil) SetValue(Grid,1000)}
{ "25 mil" checked=gridsize,2500 SetUnits(mil) SetValue(Grid,2500)}
{"100 mil" checked=gridsize,1 SetUnits(mil) SetValue(Grid,1)}
-
{"0.01 mm" checked=gridsize,39 SetUnits(mm) SetValue(Grid,39.37007874)}
{"0.05 mm" checked=gridsize,197 SetUnits(mm) SetValue(Grid,196.85039370)}
{"0.1 mm" checked=gridsize,394 SetUnits(mm) SetValue(Grid,393.70078740)}
{"0.25 mm" checked=gridsize,984 SetUnits(mm) SetValue(Grid,984.25197)}
{"0.5 mm" checked=gridsize,1969 SetUnits(mm) SetValue(Grid,1968.503937)}
{"1 mm"checked=gridsize,3937 SetUnits(mm) SetValue(Grid,3937.00787400)}
-
{"Grid -5mil" SetValue(Grid,-5,mil) a={"Shift-G" "Shiftg"}}
{"Grid +5mil" SetValue(Grid,+5,mil) a={"G" "g"}}
{"Grid -0.05mm" SetValue(Grid,-0.05,mm) a={"Shift-Ctrl-G" "Shift
Ctrlg"}}
{"Grid +0.05mm" SetValue(Grid,+0.05,mm) a={"Ctrl-G" "Ctrlg"}}
}
-
{"Shown Layers"
@layerview
-
Re: gEDA-user: Design Flow Roadmap starting point
DJ Delorie wrote: [Al Davis]>> Design the file format first, then the data structures. The file format should be designed as a language for expressing what you want to express. PCB has a second format it uses called a "resource file". It's a semi-lisp-ish format that allows for arbitrarily nested data, without the complexities of XML (the whole parser is about a page of code). It could be used to hold pretty much anything, but it isn't "designed for the data". Couldn't resource file be used with the plugin mode of programming to extend function? Since it is LISP-ish it seems closest to a common file format language with gschem, which uses guile. Are there rumors of planning to stop using guile? John G PS more condensing and grouping of these ideas done at the wiki. http://geda.seul.org/wiki/geda:design_flow_and_hierarchy_roadmap ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: installation
Stuart Brorson wrote: On Sun, 18 Mar 2007, Jason Elder wrote: Hi, I'm having trouble with the installation, but I don't know if this should be posted hereI just downloaded the new version 20070221 of gEDA and I was wondering how I can install it as root. Do not install as root. If you install as root, and you need to install system-wide dependencies, the installer becomes confused when it tries to fire up an expect session as root. My experience has been that if you are missing some system dependencies, the first expect session will always fail, whether running as root or not. This may be unique to the openSuSe distributions, but I don't think so. It is more likely just an issue exposed by the fact that the openSuSe installations have less of the system dependencies installed out of the box. Maybe the SuSe distributions are the best way to test the installer :)? Joe T. Old versions of the installer didn't check to see if the user was root. Then, users running as root would find that the installer failed when it tried to install system dependencies. Therefore, I implemented a check to verify that the user was *not* running as root. This change went in to the 20077221 installer (IIRC). In general, using your Linux box in root all the time is dangerous, and is considered bad form. You can make a mistake and harm your system running as root all the time. Run as a regular user. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: installation
C P Tarun wrote: Do not install as root. If you install as root, and you need to install system-wide dependencies, the installer becomes confused when it tries to fire up an expect session as root. Now I'm confused. In all these years of working on Unix, I've always thought packages need to be installed as root. How else will you keep the binaries in a place like /opt or /usr/local where all users of your system can access them? In all my (almost 30) years of working on Unix systems this is what I always thought as well. Especially on systems used by more than one user (which is/was usually the case). I don't see how installing system dependencies as other than the root user will work in general, especially if any of those dependencies are expected to be available to other programs sometime in the future. Joe T -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
I corrected the documentation and added the TO220 pads example to the Examples section. Great. Thanks. :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Icarus Verilog with Xilinx simprims...
Stephen Williams wrote: I've changed your section to be one heading level down, assuming that is your desire. Thanks for contributing. Looks good - Thanks Evan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: installation
Thank you for the post and thank you for this clarification. I do usually run my home computer as root, but creating a user and installing this under that user won't be a big deal. I guess I just needed the clarification for peace of mind that I was doing the best thing for the installation. I just couldn't find an explanation of this anywhere in the docs. Stuart Brorson <[EMAIL PROTECTED]> wrote: On Sun, 18 Mar 2007, Jason Elder wrote: > Hi, I'm having trouble with the installation, but I don't know if >this should be posted hereI just downloaded the new version >20070221 of gEDA and I was wondering how I can install it as root. Do not install as root. If you install as root, and you need to install system-wide dependencies, the installer becomes confused when it tries to fire up an expect session as root. Old versions of the installer didn't check to see if the user was root. Then, users running as root would find that the installer failed when it tried to install system dependencies. Therefore, I implemented a check to verify that the user was *not* running as root. This change went in to the 20077221 installer (IIRC). In general, using your Linux box in root all the time is dangerous, and is considered bad form. You can make a mistake and harm your system running as root all the time. Run as a regular user. Stuart - Expecting? Get great news right away with email Auto-Check. Try the Yahoo! Mail Beta. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Icarus Verilog with Xilinx simprims...
Evan Lavelle wrote: > Günter Dannoritzer wrote: >> Andy Peters wrote: >>> Does iverilog support SDF backannotation? The SDF has the delay >>> information. >> >> Here are some information about that and a link to a previous discussion: >> >> http://iverilog.wikia.com/wiki/Graffiti#SDF_support > > I added a section to your entry covering the reasons for doing timing > simulations (same URL). > > Haven't quite got the hang of this wiki yet. I tried to add it as a > second-level heading under 'SDF support', but it's gone in as a main > heading... I've changed your section to be one heading level down, assuming that is your desire. Thanks for contributing. -- Steve Williams"The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog with Xilinx simprims...
Evan Lavelle wrote: > Günter Dannoritzer wrote: [...] >> >> Here are some information about that and a link to a previous discussion: >> >> http://iverilog.wikia.com/wiki/Graffiti#SDF_support > > I added a section to your entry covering the reasons for doing timing > simulations (same URL). > > Haven't quite got the hang of this wiki yet. I tried to add it as a > second-level heading under 'SDF support', but it's gone in as a main > heading... Thanks Evan, Those are great information. I think the 'SDF support' headline was already a second-level == headline ==. To get it underneath you would need to make it a third-level === headline ===. Cheers, Guenter ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
On 3/19/07, C P Tarun <[EMAIL PROTECTED]> wrote: > A script to place TO220 pads can be pretty simple (see below). The > poorly named routine element_add_pin_oval overlays a pin, a rounded pad > on the component side and a rounded pad on the solder side. I have been reading your (excellently-formatted reference-class) documentation on your library. The documentation does not mention that add_pin_oval adds two pads on two layers... it seems to say that this is a "hybrid object consisting of a pad and a pin with the same centre point." Is the document out of sync with the library? I corrected the documentation and added the TO220 pads example to the Examples section. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog with Xilinx simprims...
Günter Dannoritzer wrote: Andy Peters wrote: Does iverilog support SDF backannotation? The SDF has the delay information. Here are some information about that and a link to a previous discussion: http://iverilog.wikia.com/wiki/Graffiti#SDF_support I added a section to your entry covering the reasons for doing timing simulations (same URL). Haven't quite got the hang of this wiki yet. I tried to add it as a second-level heading under 'SDF support', but it's gone in as a main heading... Evan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tool to calculate Nyquist-plot or impedance?
Try KJWaves (on sourceforge). The graphing routine allows you to select the Real or Imaginary part of any signal to place on any axis of a graph. It should do what you want. You just have to get your sim. ready to run on ngspice. Kurt Wen wrote: > Hi list, > I am going to do Equivalent circuit fitting for a university project with impedance spectroscopy. > > I am looking for a tool that first allows to define (via a graphic interface would be best) an electric circuit made of resistors, conductors, inductors and maybe constant phase and warburg elements. > What i need is a Nyquist-plot of that circuit-> a plot that shows the imaginary (vert. axis) and the real (horiz. axis) part of the impedance of the defined circuit for a wide range of frequencies. > > So I am either looking for an application that outputs that Nyquist-plot directly or that calculates the impedance analytically with the frequency as a parameter, so that I can use it for a matlab/octave-script. > > Is there a geda-tool thats able to do one of those two things? I did not see something like that in the tutorial-part nor find it in the gschem-interface? > If not, does somebody know other applications that are able to handle this? > > Thanks in advance, > Wen gnucap. gnucap is a circuit simulator and it is very easy to describe your circuit and do an ac analysis of it to directly measure the impedance. You can take that data and feed it back to matlab or octave. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
On 3/19/07, C P Tarun <[EMAIL PROTECTED]> wrote: > A script to place TO220 pads can be pretty simple (see below). The > poorly named routine element_add_pin_oval overlays a pin, a rounded pad > on the component side and a rounded pad on the solder side. I have been reading your (excellently-formatted reference-class) documentation on your library. The documentation does not mention that add_pin_oval adds two pads on two layers... it seems to say that this is a "hybrid object consisting of a pad and a pin with the same centre point." Is the document out of sync with the library? It is out of sync. I corrected the mistake in the procedure and forgot to update the documentation. Thanks for the report. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
