gEDA-user: gattrib text size
In gschem I have my default text size set as 8. If I add attributes via gattrib then the text is added as size 10. Obviously these are two separate programmes and gattrib is not dependant on the settings in my gschemrc, so this behaviour is kind of expected. Is there any way to set the default size of the text that is added when using gattrib? I tried to add a gattribrc file to my .gEDA directory with (text-size 8) in it, but that did not work. -- Turn ideas into products - http://www.engineersimplicity.com The Art of Engineering - http://blog.engineersimplicity.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gattrib text size
In gschem I have my default text size set as 8. If I add attributes via gattrib then the text is added as size 10. Obviously these are two separate programmes and gattrib is not dependant on the settings in my gschemrc, so this behaviour is kind of expected. Is there any way to set the default size of the text that is added when using gattrib? I tried to add a gattribrc file to my .gEDA directory with (text-size 8) in it, but that did not work. I forget the exact behavior of gattrib, but I can say that gattrib *does* read the gafrc file. Therefore, try putting a text-size declaration in your gafrc file. (To remind people, the idea of gafrc was to avoid the proliferation of RC files for each different member of gEDA/gaf by creating a single RC file which would contain settings read by all programs. In principle, you only need a gafrc. The gschemrc was kept because gschem has all kinds of GUI settings which no other program needs to read.) Cheers, Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Free Dog gathering on Thursday Nov 6th in Reading, MA!
-- Free Dog Gathering Announcement The Free EDA Users Group will meet Thursday, November 6th. It's been many months since we last gathered. Let's get back into the swing of things with a fall gathering at the Bear Rock Cafe in Reading, MA! The meeting will be an open and informal working session. Bring your laptop *and* wireless card! Some items on the agenda are: * gEDA/gaf release 1.6.X * Google Summer of Code: lessons learned in 2008 * Gerbv-2.1.X: What's next for gerbv? * Symbol and footprint libraries: What's next? * Rationalization of hotkeys between gschem and PCB? * What have you been up to? *** Feature! *** For those not able to be present physically, we will have at least one participant on IRC, so if you Europeans feel like staying up late, please join us on IRC channel #geda! Free Dog is an association of like-minded hackers and engineers interested in free and open EDA tools. We hold monthly meetings around the Boston area featuring informal networking, speakers, and camaraderie. Our goals are to learn more about CAD, engineering and scientific software, share ideas about our current projects, and -- most importantly -- have fun with like-minded people. We welcome new members and participants of all ages. Students are particularly welcome! Date: Thursday, November 6th, 2008. (*** Note day ***) Time: 7:00pm, Eastern US Time. Location: Bear Rock Cafe, 26 Walkers Brook Drive, Reading, Mass. (*** Note location ***) == The Bear Rock Cafe is located in the same mall as the gigantic Jordan's Furniture IMax cinema right off Rt 128 exit 39. IRC: #geda For more details, please contact me privately at sdb (* AT *) cloud9 (* DOT *) net. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gattrib text size
I forget the exact behavior of gattrib, but I can say that gattrib *does* read the gafrc file. Therefore, try putting a text-size declaration in your gafrc file. I tried putting (text-size 8) into the gafrc file and removed it from the gschemrc file. Text added in gschem is then back to the default 10pt, and text added via gattrib is also still 10pt. *Harumph* Then it's possible that 10 is hard-coded into gattrib. I don't know why gschemrc ignores the text-size setting in gafrc. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gattrib text size
On Mon, 2008-10-27 at 07:35 -0400, Stuart Brorson wrote: I forget the exact behavior of gattrib, but I can say that gattrib *does* read the gafrc file. Therefore, try putting a text-size declaration in your gafrc file. I tried putting (text-size 8) into the gafrc file and removed it from the gschemrc file. Text added in gschem is then back to the default 10pt, and text added via gattrib is also still 10pt. *Harumph* Then it's possible that 10 is hard-coded into gattrib. Yep... grep DEFAULT_TEXT_SIZE *.c s_object.c:#define DEFAULT_TEXT_SIZE 10 This previously did look at the variables defined in gschemrc, but those got moved into GSCHEM_TOPLEVEL with this commit of mine: http://git.gpleda.org/?p=gaf.git;a=commitdiff;h=823d692b70510986db607c8592b788ca68dbb979 Since gattrib never parsed the gschemrc, there wasn't any change in behaviour by _not_ looking in those data-structures though. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb, howto partition power planes?
Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb, polygon dead copper removal question
I do not fully understand what is going on when a polygon is divided by a trace (with clearance). Is there somewhere an explanation how it (should) work? Is there a way to deactivate the removal of copper? It is my impression that always the smaller part of a rectangle/polygon is removed, even when the two sub-parts are connected by a trace? I think this is not always desired. Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I typically deal with this by separating the planes at the schematic level using a bead-core inductor. The two planes are then on different nets at the PCB level. This not only makes it easier to do the routing but they also serve an electrical purpose of isolating the two planes from a high frequency viewpoint, whilst connecting them at DC. On Mon, 2008-10-27 at 16:39 +0100, Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Am Montag, den 27.10.2008, 11:59 -0400 schrieb Neil Webster: I typically deal with this by separating the planes at the schematic level using a bead-core inductor. The two planes are then on different nets at the PCB level. This not only makes it easier to do the routing but they also serve an electrical purpose of isolating the two planes from a high frequency viewpoint, whilst connecting them at DC. Yes, I also have GND and AGND in my schematics. My question is more in this direction: How do I best divide a copper area (physically) into subsections with complicated shape/outline. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is there a directory of footprints for PCB?
I do not want to start a flame war, since I am relatively new here but I have to comment ... On Sun, 2008-10-26 at 20:47 +0100, Stefan Salewski wrote: Am Sonntag, den 26.10.2008, 14:25 -0500 schrieb Kipton Moravec: There are huge differences in the size of these footprints! Please note, some are metric, see http://archives.seul.org/geda/user/Sep-2008/msg00312.html Why in gods name would some one call a footprint 0603 when it is really an 0201. Nobody uses a metric name for resistors or capacitors. You folks are asking for trouble. First of all why so many? When would you use one versus another? We may need more than one -- hand, wave, reflow soldering... If you do some search in Internet you will find many different size recommendations. I do not buy that. Everything I build is designed for machine placement and solder, and so a human can perform touch-up if necessary, but my assembly shop decides how they will build it. If it is a small order they may hand build it. If it is more then they will use the pick-and-place machine. Everyone should design for the machine. Same is true for through hole. You build your footprints so a machine can stuff it. If there is not enough volume to use a machine, it cam be hand placed. But if you design your footprints for only hand placement, then a machine can never place it. Bad idea. Also assume it will be wave soldered for the same reason. I worked at an assembly shop for awhile, so I would better understand the assembly process, and I could design for manufacturability. I was amazed at how bad some boards were layed out and how difficult they were to inspect, and they were doing production in the thousands! The biggest problem nowadays is that the designers do not follow the board through production in most places. They need to know the whole process from design to placing in the customers hands. You have one guy design the schematic, another person lay it out, another person purchase the parts, another person assemble the board and another person inspect the board, and another person test it. And they do not talk to each other. I design boards so they can be built. I design boards so they can be inspected. I design boards so they can be tested. I design boards with parts that are in stock or do not have long lead times ( 4 weeks). My customers want me to design a board, and provide them finished product at a certain rate per month. If I make it easy for the assembly house to build, they can assemble it cheaper, with less errors, and we all make more money. You design it one time, but build it many many times. Make it easy to build, even if it takes a little longer in the design. Kip -- Kipton Moravec AE5IB Always do right; this will gratify some people and astonish the rest. --Mark Twain ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is there a directory of footprints for PCB?
Why in gods name would some one call a footprint 0603 when it is really an 0201. Nobody uses a metric name for resistors or capacitors. You folks are asking for trouble. It's not us, it's the international standards. We're microscopic fish in a galaxy-sized pond. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is there a directory of footprints for PCB?
Ahh, haha. In the USA, electronic design engineers have been using inches (with 0603 meaning 0.06 by 0.03 inches) to describe surface mount resistors and capacitors. Folks in other countries have probably always been using metric. But I've noticed that recently digikey.com (a popular supplier of low-volume electronic parts in the USA) is listing the metric sizes in parenthesis after the inch sizes for their standard 0201/0402/0603/0805 sizes. [1]http://search.digikey.com/scripts/DkSearch/dksus.dll?Cat=65769;stoc k=1;rohs=1;pbfree=1 0201 (0603 metric) 0402 (1005 metric) 0603 (1608 metric) and so on is how digikey does it. (Digikey does still list these parts by their inch as the primary name, but provides the metric as a secondary.) So what the primary standard is depends on whether you're in the USA. I'm in the USA but most gEDA developers probably are not. DJ Delorie wrote: Why in gods name would some one call a footprint 0603 when it is really an 0201. Nobody uses a metric name for resistors or capacitors. You folks are asking for trouble. It's not us, it's the international standards. We're microscopic fish in a galaxy-sized pond. ___ geda-user mailing list [EMAIL PROTECTED] [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Nikola Engineering Inc. 224 W. Washington St. Suite 104 Sequim, WA 98382-3371 Tel (360)582-1051 Fax (360)582-1104 References 1. http://search.digikey.com/scripts/DkSearch/dksus.dll?Cat=65769;stock=1;rohs=1;pbfree=1 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is there a directory of footprints for PCB?
On Mon, Oct 27, 2008 at 11:21:50AM -0600, John Doty wrote: Nobody uses a metric name for resistors or capacitors. I see it all the time. For example, here's a blurb that gives both with priority to metric: http://www.rohm.com/ad/mcr004/index.html Another example is Altium, which comes with IPC-standard footprint libraries, which only state the metric name. I'm sure other CAD packages are similar. -- http://petertodd.org 'peter'[:[EMAIL PROTECTED] signature.asc Description: Digital signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I typically deal with this by separating the planes at the schematic level using a bead-core inductor. Yes, I also have GND and AGND in my schematics. Don't put inductors between ground planes, connect them at a star point. If you are going to use inductors then have them on the power side, not between grounds. How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? It would be relatively easy if planes could be handled as negatives, i.e. everything you see is NOT there. Then it is just a matter of moving a line. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Am Montag, den 27.10.2008, 19:47 +0200 schrieb Duncan Drennan: Yes, I also have GND and AGND in my schematics. Don't put inductors between ground planes, connect them at a star point. If you are going to use inductors then have them on the power side, not between grounds. I think so too -- but it may depend on what we build. Indeed I have seen recommendations to employ inductors in newsgroup sci.electronics.design. I use an analog ground where my OpAmps reside, and a digital ground for FPGA, uC. Situation is more complicated for DC/DC-converters or ADC, there are detailed shapes for ground and power planes in some datasheets. But my question currently is not how it should look, but how I build it best with pcb. How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? This is my question. It would be relatively easy if planes could be handled as negatives, i.e. everything you see is NOT there. Then it is just a matter of moving a line. I would be also interested in how this is handled in other pcb programs. Best regards, Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Mon, 27 Oct 2008 19:47:32 +0200, Duncan Drennan wrote: How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? If you want to partially divide a polygon: * Draw lines on copper with zero thickness but finite clearance. If you want to completely dissect a polygon: * Divide the polygon with thin tracks. Parts will render invisible. * Let the mouse hover over the visible part of the polygon. Use the command MorphPolygon(Object) to make each snippet a polygon on its own. Alternatively you can select the polygon and apply the variant MorphPolygon(Selected) ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Am Montag, den 27.10.2008, 18:17 + schrieb Kai-Martin Knaak: On Mon, 27 Oct 2008 19:47:32 +0200, Duncan Drennan wrote: How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? If you want to partially divide a polygon: * Draw lines on copper with zero thickness but finite clearance. Does this really result in legal Gerber files -- would be not so nice if a few manufacturers can not handle it. If you want to completely dissect a polygon: * Divide the polygon with thin tracks. Parts will render invisible. * Let the mouse hover over the visible part of the polygon. Use the command MorphPolygon(Object) to make each snippet a polygon on its own. Alternatively you can select the polygon and apply the variant MorphPolygon(Selected) Thanks -- this was what I was missing. I think I read about MorphPolygon() on this list, but I did not know how to use it correctly. Best regards, Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, polygon dead copper removal question
On Mon, 2008-10-27 at 16:47 +0100, Stefan Salewski wrote: I do not fully understand what is going on when a polygon is divided by a trace (with clearance). Is there somewhere an explanation how it (should) work? Is there a way to deactivate the removal of copper? It is my impression that always the smaller part of a rectangle/polygon is removed, even when the two sub-parts are connected by a trace? I think this is not always desired. I have some scratch code to do a proper pour, keeping all pieces which aren't connected to something better, such as a line, via, etc.. That seems to work vaguely nicely for me, but the code isn't ready yet. I still need to figure out how to make it backwards compatible with the old polygon method, lots of things to finish off, corner cases to fix for triggering island detection. Also, I need to work out if I can make island detection work fast enough to update on the fly without annoying the user, or whether that process (perhaps pouring its-self) needs to be a manually invoked operation. Best regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is there a directory of footprints for PCB?
Kipton Moravec wrote: I do not want to start a flame war, . . . Everyone should design for the machine. You might get one. But probably not... gEDA users are about as individual as they come, and often do things their way, so you won't be able to convince them to all design any one way. The biggest problem nowadays is that the designers do not follow the board through production in most places. Many gEDA users do. They are also the individualistic ones that make their own footprints and symbols slightly differently from others. I worked at an assembly shop for awhile, so I would better understand the assembly process, and I could design for manufacturability. Then you can help a lot with organizing gschem and pcb libraries, such as are published at gedasymbols.org. The problem of publishing well tested, dependable footprints is not easy -- it takes effort to test things. We've talked here about ideas like a website full of vetted footprints, but no agreement on how to proceed. John Griessen -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I agree with Niel, I separate my ground planes with a symbol for a power inductor. I do this at the schematic level and then I read the layout suggestions typically provided by the A/D data sheet on where to connect the planes. For the fab I put in the power inductor foot print. You can then use the power inductor or not. You can leave it open or you can short it. I also do similar activities for power supplies separating the board power from board sections. Makes it very easy to debug the board from one section to the next. Steve Meier On Mon, 2008-10-27 at 19:47 +0200, Duncan Drennan wrote: I typically deal with this by separating the planes at the schematic level using a bead-core inductor. Yes, I also have GND and AGND in my schematics. Don't put inductors between ground planes, connect them at a star point. If you are going to use inductors then have them on the power side, not between grounds. How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? It would be relatively easy if planes could be handled as negatives, i.e. everything you see is NOT there. Then it is just a matter of moving a line. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On the issue of powering boards I have been playing with some really neat programmable power supply controllers (surface mount chip) that support power supply modules. Prices of the modules seem to be comparable to the prices of the individual components one would need to build various forms of switching power supplies. The controllers set the duty cycle, phase and frequency of the switching power supplies. This makes it possible to insure that two switchers are switching out of phase with each other. Other parameters which are controlled are delays from power up and rate of power up. So one other trick I use is to isolate each power supply from the rest of the board with a jumper (large diameter holes to support a fat wire). Then when we first turn on the board, we program the power supplies check out their voltages, ringing etc and then we connect them via the jumper to the rest of the board. Steve Meier On Mon, 2008-10-27 at 14:43 -0700, Steve Meier wrote: I agree with Niel, I separate my ground planes with a symbol for a power inductor. I do this at the schematic level and then I read the layout suggestions typically provided by the A/D data sheet on where to connect the planes. For the fab I put in the power inductor foot print. You can then use the power inductor or not. You can leave it open or you can short it. I also do similar activities for power supplies separating the board power from board sections. Makes it very easy to debug the board from one section to the next. Steve Meier On Mon, 2008-10-27 at 19:47 +0200, Duncan Drennan wrote: I typically deal with this by separating the planes at the schematic level using a bead-core inductor. Yes, I also have GND and AGND in my schematics. Don't put inductors between ground planes, connect them at a star point. If you are going to use inductors then have them on the power side, not between grounds. How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? It would be relatively easy if planes could be handled as negatives, i.e. everything you see is NOT there. Then it is just a matter of moving a line. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Mon, 27 Oct 2008 19:47:52 +0100, Stefan Salewski wrote: * Draw lines on copper with zero thickness but finite clearance. Does this really result in legal Gerber files -- would be not so nice if a few manufacturers can not handle it. I didn't check the Gerber specs. My favorite fab (Basista) did not complain when I started to (miss) use this feature. They just rendered it like pcb and gerbv showed on the screen. If you want to completely dissect a polygon: * Divide the polygon with thin tracks. Parts will render invisible. * Let the mouse hover over the visible part of the polygon. Use the command MorphPolygon(Object) to make each snippet a polygon on its own. Alternatively you can select the polygon and apply the variant MorphPolygon(Selected) Note to Peter Clifton: There is a quirk in the Cairo enabled version. It does the morphing action and removes the old polygon. But it fails to automatically draw the newly produced polygons. I had to resort to the save-and-revert trick to get the new polygons on the screen. ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
