gEDA-user: autoconf and pcb
I've grabbed the pcb head branch from git and am trying to build it. I ran autoconf then ./configure and I get the following error: ./configure: line 1899: `AM_INIT_AUTOMAKE(1.9)' Does anyone have any suggestions? I haven't dug into configure documentation to see why. I'm doing this on mac osx. Pete ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autoconf and pcb
It appears as though I had to run autogen.sh instead of autoconf and was able to get configure to run. Pete On Feb 16, 2009, at 7:13 AM, Peter Wiley-Cordone wrote: I've grabbed the pcb head branch from git and am trying to build it. I ran autoconf then ./configure and I get the following error: ./configure: line 1899: `AM_INIT_AUTOMAKE(1.9)' Does anyone have any suggestions? I haven't dug into configure documentation to see why. I'm doing this on mac osx. Pete ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user Peter Wiley-Cordone pcord...@ieee.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autoconf and pcb
Autogen.sh is supposed to run automake, autoconf, autoheader, etc. They're supposed to be run in a particular order, which is why they've been conveniently grouped together into autogen.sh. If you just run autoconf alone, then you won't necessarily have set up all the other stuff needed for normal compilation. You might get a configure file, but it many not have all the macros in it fully expanded. Chances are good that compilation will fail during configure or somewhere later on From your error, it looks like you don't have automake version 1.9. You probably have an earlier one. You need to upgrade. The autotools are very finnicky about versioning. They are also a something of a PITA. However, they're easier to use than hand-writing a configure script for a big, cross-platform application. Also, since they're supposed to be used only by developers, it's allegedly OK that they are not user friendly. Here are some tutorials about autotool basics which I Googled up: http://markuskimius.wikidot.com/programming:tut:autotools http://www.lrde.epita.fr/~adl/autotools.html HTH, Stuart On Mon, 16 Feb 2009, Peter Wiley-Cordone wrote: It appears as though I had to run autogen.sh instead of autoconf and was able to get configure to run. Pete On Feb 16, 2009, at 7:13 AM, Peter Wiley-Cordone wrote: I've grabbed the pcb head branch from git and am trying to build it. I ran autoconf then ./configure and I get the following error: ./configure: line 1899: `AM_INIT_AUTOMAKE(1.9)' Does anyone have any suggestions? I haven't dug into configure documentation to see why. I'm doing this on mac osx. Pete ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user Peter Wiley-Cordone pcord...@ieee.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: GL pcb bugs and a question re the log/library window, gerber outline output
Hello there! I found a few bugs in pcb, some of them are stopping me from sending the layout to the manufacturer :( The bugs are there in pcb 20081128 and in the GL + pcb branch. I've filed tickets for them with minimal working examples and screenshots. First there's a problem with polygon clearance. It is rather buggy for large polygons with many holes in them and produces awkward results. Screenshot attached for your convenience. Second, there is a bug in the polygon code causing pcb to crash when zooming. I couldn't obtain a core dump file (it always has a size of zero bytes), but I've pasted a backtrace into the bug description. Last but not least there's a usability bug where the mouse cursor does not change into that little rectangle when the cursor is over a line end so it becomes hard sometimes to pull a line end around. The questions I have are rather simple: How do I stop the log window and the library from opening every time I start pcb? I don't need them 90% of the time and they start to annoy me ... Then, the gerber files contain text describing holes. I'm not sure how the pcb pool manufacturer will cope with that, so is there an option to turn that off? many thanks and greetings Denis ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tutorial changes
On Sat, 24 Jan 2009 14:51:54 +0530, Shakthi Kannan wrote: http://geda.seul.org/wiki/geda:gsch2pcb_tutorial * There is no Analog library under Components. Under Basic devices, we have resistor-1.sym. I accommodated the tutorial to reflect the names displayed in the library chooser. By the way: How can I set similar names that deviate from the path for my local libs? * There is no slot definition in dual-opamp-1.sym. The symbol contains the slot definition. However, the slot attribute is not visible. So it is not copied to the instance in the schematics. You can add it manually: 1) Select the instantiated symbol in the schematic. 2) Type ee to bring up the attribute editor 3) Choose slot from the drop down list of attribute names. 4) Type 1 in the value field 5) press the add button. The instance of the symbol immediately updates accordingly -- No need to close the attribute editor dialog. Following the principle of least surprise, the slot attribute should be effective automatically, when working with the default library. However, the slot attribute is invisible in all the slotted symbols of the default library I checked. I'd volunteer to change the slot attribute of all these symbols to visible. How would this enter the distribution? My local source was downloaded via git. How would I go ahead and communicate the necessary changes? ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: vendor resource file and fab houses
On Wed, 04 Feb 2009 14:31:40 -0800, Saritha Kalyanam wrote: From experience, which fab house is recommended? How about a section on fab experience in the wiki? This may seem sensitive because it might interfere with commercial aspects. If this prevents inclusion on the official website, I might set up such a section on my private web space. ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tutorial changes
On Feb 16, 2009, at 9:57 AM, Kai-Martin Knaak wrote: On Sat, 24 Jan 2009 14:51:54 +0530, Shakthi Kannan wrote: http://geda.seul.org/wiki/geda:gsch2pcb_tutorial * There is no Analog library under Components. Under Basic devices, we have resistor-1.sym. I accommodated the tutorial to reflect the names displayed in the library chooser. By the way: How can I set similar names that deviate from the path for my local libs? * There is no slot definition in dual-opamp-1.sym. The symbol contains the slot definition. However, the slot attribute is not visible. So it is not copied to the instance in the schematics. You can add it manually: 1) Select the instantiated symbol in the schematic. 2) Type ee to bring up the attribute editor 3) Choose slot from the drop down list of attribute names. 4) Type 1 in the value field 5) press the add button. The instance of the symbol immediately updates accordingly -- No need to close the attribute editor dialog. Much easier is to use eS or EditSlot... That adds the required attribute. Following the principle of least surprise, the slot attribute should be effective automatically, when working with the default library. However, the slot attribute is invisible in all the slotted symbols of the default library I checked. I'd volunteer to change the slot attribute of all these symbols to visible. Yuck. Please no. This is actually an attribute that it makes sense to always promote in just about every flow, even if invisible. But the list in system- gafrc (always-promote-attributes footprint device value model-name) is not sensible in my flows. Of course this is easy to customize... How would this enter the distribution? My local source was downloaded via git. How would I go ahead and communicate the necessary changes? ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni- hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak +kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Interesting board defect
Am Montag, den 16.02.2009, 09:50 + schrieb Dylan Smith: On Sat, 14 Feb 2009, Dave N6NZ wrote: On Chinese fabs... So... it's hard to beat BatchPCB's price for one-offs, but I've decided to dial back a bit on how hard I push their technology. I've never gotten a straight answer from them anyway on design rule questions. I've used PCB Cart for a few boards (dealt with them directly). They probably are a bit more expensive for one-offs, but the boards I got back for a project using 0.4mm pitch LQFP (a 4 layer board) with minimum DRC trace/clearance of 6/6 came back from them perfect. They seem very flexible and don't have any odd design rules. They do free electrical testing for boards that are 4 layers or more. Interesting. I consider using PCB Cart myself -- price is good, and I heard that quality and support is fine too. I have a 4 layer board too. Have you send gerbers from PCB program? Is there something special to watch for? I think they have no information for impedance control on their page (we need to know layer separation to calculate impedance). Have you manage to get defined impedances for your traces? Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tutorial changes
Am Montag, den 16.02.2009, 14:57 + schrieb Kai-Martin Knaak: * There is no slot definition in dual-opamp-1.sym. The symbol contains the slot definition. However, the slot attribute is not visible. So it is not copied to the instance in the schematics. You can add it manually: 1) Select the instantiated symbol in the schematic. I think there is Slot... entry in recent gschem Edit menu -- this is a faster may to select slots. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Interesting board defect
On Mon, 16 Feb 2009 17:36:02 +0100, Stefan Salewski wrote: I consider using PCB Cart myself -- price is good, Just checked it. Some remarks: * 4 Layers will take 12 working days minimum, plus what ever it takes for fedex to ship from china. If you don't register for open account payment needs to be confirmed before production time begins. * Shipping and customs and EUSt have to be added on top of the quoted price. * There is a maximum number of holes. (300 for my 100x100mm test case) * Design rules are modestly aggressive: minimum drill = 0.4 mm minimum track width, minimum spacing = 0.2 mm minimum annular ring = 0.25 mm My preferred fab offers about 0.75 times these values as standard. * Poor english on the webpage. E.g: For small quantity, if by air the extra cost will make it not save (no full stop). I think they have no information for impedance control on their page There is an item impedance control in their quote. I'd guess, this could be set this to some other value on request. ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autoconf and pcb
The autotools are very finnicky about versioning. They are also a something of a PITA. However, they're easier to use than hand-writing a configure script for a big, cross-platform application. Also, since they're supposed to be used only by developers, it's allegedly OK that they are not user friendly. Another project I am interested in (Csound) uses Scons as a build tool - has that ever been considered for gEDA/gaf or PCB? I don't know too much about it so I can't advocate on its behalf but I've heard it praised Gareth ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Interesting board defect
Am Montag, den 16.02.2009, 18:53 + schrieb Kai-Martin Knaak: Some remarks: * 4 Layers will take 12 working days minimum, plus what ever it takes for fedex to ship from china. If you don't register for open account payment needs to be confirmed before production time begins. Yes, boards from china will take some time. * Shipping and customs and EUSt have to be added on top of the quoted price. Yes, but total costs are still not bad. If I remember correctly: Four boards, 4 layer, each 26cm * 32cm will give total something about 1000 Dollar. The only company which I aware of here in Germany which is not much more expensive is http://www.microcirtec.de Large quantities are really cheap at pcbcart, so I think it is a good idea to try them. * There is a maximum number of holes. (300 for my 100x100mm test case) I think this is no problem, most people use at least some SMD. * Design rules are modestly aggressive: minimum drill = 0.4 mm minimum track width, minimum spacing = 0.2 mm minimum annular ring = 0.25 mm My preferred fab offers about 0.75 times these values as standard. * Poor english on the webpage. E.g: For small quantity, if by air the extra cost will make it not save (no full stop). My english is poor also -- perfect fit :-) I think their parameters are not too bad, and I think they can do better, for more money. (And I think drill is 0.3mm without additional costs, think I have seen it...) I think they have no information for impedance control on their page There is an item impedance control in their quote. I'd guess, this could be set this to some other value on request. I have seen this, but do not understand it. I have asked by email some months ago, and got only a very short reply: Hi Mr. Salewski, Thanks for your suggestion, we are considering improving our homepage. Regarding to your question, please see follows: Trace width: 8.5mil, 1oz copper, 0.12/1.13/0.12 for 50ohm impedance. Best regards Not much. I guess that I will get 50 Ohm impedance for traces on outer layers of 4 layer board if trace width is 8.5 mil. Hope that I really will get this. Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL pcb bugs and a question re the log/library window, gerber outline output
On Mon, Feb 16, 2009 at 02:56:44PM +0100, Denis Grelich wrote: First there's a problem with polygon clearance. I think that might be a GL display bug. There was a thread about that recently. Try exporting your layout to PostScript and view that (you can convert with ps2pdf and use acroread if you want). If the planes look fine there, they will look fine in the gerbers. core dump file (it always has a size of zero bytes), but I've pasted a backtrace into the bug description. Make sure your coredump size isn't limited (check ulimit). Where are you submitting these bugs? Are we still using sourceforge's tracker? (the latter isn't really a question for Denis...) -- Ben Jackson AD7GD b...@ben.com http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL pcb bugs and a question re the log/library window, gerber outline output
Where are you submitting these bugs? Are we still using sourceforge's tracker? I believe that hasn't changed, we're still using sf for bug tracking. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Was there a major change to how power nets are handled in netlists?
In many of my schematics, I would have multiple power symbols, and when I wanted them to be the same, I just connected them. However, that no longer works! The netlister is making them separate nets. Was this intentional? Matt ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Interesting board defect
On Feb 16, 2009, at 12:11 PM, Stefan Salewski wrote: Am Montag, den 16.02.2009, 18:53 + schrieb Kai-Martin Knaak: Some remarks: * 4 Layers will take 12 working days minimum, plus what ever it takes for fedex to ship from china. If you don't register for open account payment needs to be confirmed before production time begins. Yes, boards from china will take some time. * Shipping and customs and EUSt have to be added on top of the quoted price. Yes, but total costs are still not bad. If I remember correctly: Four boards, 4 layer, each 26cm * 32cm will give total something about 1000 Dollar. The only company which I aware of here in Germany which is not much more expensive is http://www.microcirtec.de Large quantities are really cheap at pcbcart, so I think it is a good idea to try them. * There is a maximum number of holes. (300 for my 100x100mm test case) I think this is no problem, most people use at least some SMD. * Design rules are modestly aggressive: minimum drill = 0.4 mm minimum track width, minimum spacing = 0.2 mm minimum annular ring = 0.25 mm My preferred fab offers about 0.75 times these values as standard. * Poor english on the webpage. E.g: For small quantity, if by air the extra cost will make it not save (no full stop). My english is poor also -- perfect fit :-) I think their parameters are not too bad, and I think they can do better, for more money. (And I think drill is 0.3mm without additional costs, think I have seen it...) I think they have no information for impedance control on their page There is an item impedance control in their quote. I'd guess, this could be set this to some other value on request. I have seen this, but do not understand it. I have asked by email some months ago, and got only a very short reply: Hi Mr. Salewski, Thanks for your suggestion, we are considering improving our homepage. Regarding to your question, please see follows: Trace width: 8.5mil, 1oz copper, 0.12/1.13/0.12 for 50ohm impedance. Best regards Not much. I guess that I will get 50 Ohm impedance for traces on outer layers of 4 layer board if trace width is 8.5 mil. Hope that I really will get this. send then a demo board. with your stack up and your trace, that you expect to be 50 Ohms. and ask them to verify that their process will make that 50 Ohms. We send spec boards to our vendors with test lines for our controlled impedances. and they then verify that our assumptions about their process were right. Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: Problems creating a ground plane and adding thermals
Hardkrash, Thanks for that - Is this documented anywhere (because I missed it if it is and I obviously need to go back and read the section again!). Also, any comments (from anyone) about the second part of my question: using the ground plane as the GND netlist? Susan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: Problems creating a ground plane and adding thermals
On Tue, Feb 17, 2009 at 09:18:51AM +1100, Susan Mackay wrote: Also, any comments (from anyone) about the second part of my question: using the ground plane as the GND netlist? You just connect the plane to a net in PCB. It will then know that plane goes with that net. -- Ben Jackson AD7GD b...@ben.com http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB - How To Find A Component?
Hi all,
On Fri, 2009-02-13 at 05:53 -0500, gene wrote:
*Scrolling* to the selected part would be easier, and could be done as
a plugin. Compare with my findrat plugin:
http://www.delorie.com/pcb/findrat.c
I don't even know where to begin :( How do the plugins get compiled and
executed? Is there some docs somewhere?
gene
I tried to get a plug-in together using findrat.c (by DJ) as a template.
I does compile with some warnings and then segfaults when run.
gdb says the culprit lives in line 71, near the strcmp () call.
Maybe I'm overlooking something very obvious and better should restart
tomorrow morning after some coffee.
Anyway I think I would like my attempt sofar.
Kind regards,
Bert Timmerman.
/*!
* \file findelement.c
* \author Copyright (C) 2009 by Bert Timmerman bert.timmer...@xs4all.nl
* \brief Plug-in for PCB to find the specified element.
*
* Function to look up the specified PCB element on the screen.\n
* \n
* Compile like this:\n
* \n
* gcc -Ipath/to/pcb/src -Ipath/to/pcb -O2 -shared findelement.c -o findelement.so
* \n\n
* The resulting findelement.so file should go in $HOME/.pcb/plugins/\n
* \n
* \warning Be very strict in compiling this plug-in against the exact pcb
* sources you compiled/installed the pcb executable (i.e. src/pcb) with.\n
*
* Usage: FindElement(Refdes)\n
* \n
* If no argument is passed, no action is carried out.\n
*
* hr
* This program is free software; you can redistribute it and/or modify\n
* it under the terms of the GNU General Public License as published by\n
* the Free Software Foundation; either version 2 of the License, or\n
* (at your option) any later version.\n
* \n
* This program is distributed in the hope that it will be useful,\n
* but WITHOUT ANY WARRANTY; without even the implied warranty of\n
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.\n
* \n
* You should have received a copy of the GNU General Public License\n
* along with this program; if not, write to:\n
* the Free Software Foundation, Inc.,\n
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.\n
*/
#include stdio.h
#include math.h
#include global.h
#include data.h
#include hid.h
#include misc.h
#include create.h
#include rtree.h
#include undo.h
#include set.h
/*!
* \brief Find the specified element.
*
* Usage: FindElement(Refdes)\n
* If no argument is passed, no action is carried out.
*/
static int
find_element (int argc, char **argv)
{
if (argc 0 strcasecmp (argv[0], ) == 0)
{
Message (WARNING: in FindElement the argument should be a non-empty string value.\n);
return 0;
}
else
{
SET_FLAG (NAMEONPCBFLAG, PCB);
ELEMENT_LOOP(PCB-Data);
{
if (strcmp (argv[0], NAMEONPCB_NAME(element)) == 0)
{
gui-set_crosshair
(
element-MarkX,
element-MarkY,
HID_SC_PAN_VIEWPORT
);
}
}
END_LOOP;
gui-invalidate_all ();
IncrementUndoSerialNumber ();
return 0;
};
}
static HID_Action findelement_action_list[] =
{
{FindElement, NULL, find_element, Find the specified element, NULL},
{FE, NULL, find_element, Find the specified element, NULL}
};
REGISTER_ACTIONS (findelement_action_list)
void
pcb_plugin_init()
{
register_findelement_action_list();
}
/* EOF */
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gEDA-user: pstoedit patch for the pcb driver
Someone mentioned that the output produced by the pstoedit pcb driver
had the board size set to a size which was too big and also I noticed
that the silk is sometimes off the board anyway. Attached is a diff
against pstoedit-3.41 that sizes the board based on the postscript
bounding box and it also offsets the silk so the silk starts at 0,0 and
fills the board.
Mark, if you're listening and agree with this, would you care to submit
it back to the pstoedit maintainer?
-Dan
--- drvpcb2.cpp.orig2009-02-16 17:44:37.0 -0500
+++ drvpcb2.cpp 2009-02-16 18:11:10.0 -0500
@@ -30,4 +30,6 @@
+#define PCB_SILK_W 1000
+const float SCALE = (10.0f/72.0f);
drvPCB2::derivedConstructor(drvPCB2):
@@ -36,7 +38,4 @@
{
// driver specific initializations
- outf PCB[\\ 60 50]\n\n;
- outf Grid[2000. 0 0 0]\n\n;
- outf Layer(10 \silk\)\n(\n;
}
@@ -55,6 +54,21 @@
{
// outf #Neue Seite\n;
+ BBox mybox;
+ long int width_p01_mil, height_p01_mil;
+
+ mybox = getCurrentBBox();
+
+ x_offset = -mybox.ll.x_ + 0.5*PCB_SILK_W/SCALE ;
+ y_offset = mybox.ur.y_ + 0.5*PCB_SILK_W/SCALE;
+
+ width_p01_mil = (long int) ((mybox.ur.x_ - mybox.ll.x_) * SCALE +
PCB_SILK_W);
+ height_p01_mil = (long int) ((mybox.ur.y_ - mybox.ll.y_) * SCALE +
PCB_SILK_W);
+
+
+ outf PCB[\\ width_p01_mil height_p01_mil ]\n\n;
+ outf Grid[2000. 0 0 0]\n\n;
+ outf Layer(10 \silk\)\n(\n;
+
}
-const float SCALE = (10.0f/72.0f);
void drvPCB2::show_path()
@@ -67,8 +81,9 @@
const Point p = pathElement(n).getPoint(0);
outf Line[;
- outf (int)(p1.x_*SCALE)
- (int)(50-p1.y_*SCALE)
- (int)(p.x_*SCALE)
- (int)(50-p.y_*SCALE) 1000 2000 0x0020]\n;
+ outf (int)( (x_offset + p1.x_)*SCALE + 0.5)
+ (int)((y_offset - p1.y_)*SCALE + 0.5)
+ (int)((x_offset + p.x_)*SCALE + 0.5)
+ (int)((y_offset - p.y_)*SCALE + 0.5)
+ PCB_SILK_W 2000 0x0020]\n;
}
}
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Re: gEDA-user: PCB - How To Find A Component?
Maybe I'm overlooking something very obvious and better should restart
tomorrow morning after some coffee.
Close! Elements don't always have names. You also didn't check for
missing arguments. Try this bit of code:
if (argc == 0 || strcasecmp (argv[0], ) == 0)
{
Message (WARNING: in FindElement the argument should be a
non-empty string value.\n);
return 0;
}
else
{
SET_FLAG (NAMEONPCBFLAG, PCB);
ELEMENT_LOOP(PCB-Data);
{
if (NAMEONPCB_NAME(element)
strcmp (argv[0], NAMEONPCB_NAME(element)) == 0)
{
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Re: gEDA-user: Was there a major change to how power nets are handled in netlists?
Hi Matt,
In many of my schematics, I would have multiple power symbols, and
when I wanted them to be the same, I just connected them. However,
that no longer works! The netlister is making them separate nets.
I cannot seem to reproduce this in a simple schematic. Could
you do me a favor and take a look at the below schematic, netlist it with
your gnetlist (on your machine), and let me know if:
1) it matches what you are doing in your large schematic
2) it netlists correctly or incorrectly for you.
I might not have interpreted your schematics correctly and maybe I am
missing something subtle.
Was this intentional?
I hope not.
-Ales
v 20081231 1
C 46000 47600 1 0 0 resistor-1.sym
{
T 46100 47900 5 10 1 1 0 0 1
refdes=R1
}
N 46000 47700 45200 47700 4
N 45200 47700 45200 48700 4
C 45000 48700 1 0 0 generic-power.sym
{
T 45200 48950 5 10 1 1 0 3 1
net=one:1
}
C 44300 48300 1 0 0 generic-power.sym
{
T 44500 48550 5 10 1 1 0 3 1
net=two:1
}
N 44500 48300 44500 48100 4
N 44500 48100 45200 48100 4
C 45400 45800 1 0 0 resistor-1.sym
{
T 45500 46100 5 10 1 1 0 0 1
refdes=R2
}
N 45400 45900 44600 45900 4
N 44600 45900 44600 46900 4
C 44400 46900 1 0 0 generic-power.sym
{
T 44600 47150 5 10 1 1 0 3 1
net=two:1
}
C 43700 46500 1 0 0 generic-power.sym
{
T 43900 46750 5 10 1 1 0 3 1
net=one:1
}
N 43900 46500 43900 46300 4
N 43900 46300 44600 46300 4
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Re: gEDA-user: autoconf and pcb
On Feb 16, 2009, at 2:52 PM, gdedwa...@blueyonder.co.uk wrote: The autotools are very finnicky about versioning. They are also a something of a PITA. However, they're easier to use than hand- writing a configure script for a big, cross-platform application. Also, since they're supposed to be used only by developers, it's allegedly OK that they are not user friendly. Another project I am interested in (Csound) uses Scons as a build tool - has that ever been considered for gEDA/gaf or PCB? I don't know too much about it so I can't advocate on its behalf but I've heard it praised Wow, Csound is still around? (assuming it's the same one) I messed with that more than a decade ago. Wow. -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Was there a major change to how power nets are handled in netlists?
On Mon, Feb 16, 2009 at 6:05 PM, Ales Hvezda ahve...@moria.seul.org wrote: Hi Matt, In many of my schematics, I would have multiple power symbols, and when I wanted them to be the same, I just connected them. However, that no longer works! The netlister is making them separate nets. I cannot seem to reproduce this in a simple schematic. Could you do me a favor and take a look at the below schematic, netlist it with your gnetlist (on your machine), and let me know if: 1) it matches what you are doing in your large schematic Only partially. I am using multiple sheets, and have many different power connectors. I have tried to reproduce it with a smaller schematic and was unsuccessful. 2) it netlists correctly or incorrectly for you. Your example netlists correctly. I might not have interpreted your schematics correctly and maybe I am missing something subtle. Did you see the same problem? The netlist I sent in the tarball shows the problem. If you rerun the netlister, do you get the same output as the netlist I sent you? If so, you have reproduced the problem :) I will try making a smaller test case again, but haven't had luck so far. I would feel better if I knew that you saw the problem in the netlist I sent. Thanks, Matt ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Google SoC : Potential Candidate seeking Info
On Monday 16 February 2009, Stephen Williams wrote: Icarus Verilog provides an API for writing code generators. This API is described by the ivl_target.h header file. There are example code generators specifically intended to demonstrate the API use: the tgt-null/ directory has a null code generator, and the tgt-stub/ directory has a stub code generator. The null code generator simply connects to the API and does noting. The stub code generator scans the entire design, displaying what it finds in human-readable form. There's also a VHDL generator, done as a SoC project last year, and an old generator that makes flat Verilog. That might be closer. A lot of work is done, just change the syntax. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Google SoC : Potential Candidate seeking Info
On Saturday 14 February 2009, Aanjhan R wrote: Thank you all for the feedbacks. I looked a bit deeper into the projects and my interests and figured that , I am not into GUI stuff but would love to get my hands more dirty with things even down. People spend lots of time trying to make a GUI, when there are problems underneath. I am not opposed to GUI's, but it is important to make what is behind it work well first, and to keep the user interface separate from the action. On Thu, Feb 12, 2009 at 9:56 AM, al davis ad...@freeelectron.net wrote: 3. Porting of missing analysis, (noise, pz, disto, hb, etc.) from other free simulators (under gnucap) All good projects .. There is someone now working on noise and hb. pz and disto would be good summer projects. pz is fairly easy, if it is based on AC analysis, because the whole model interface is already working. disto is harder because of the model interface. You will learn a lot. Looks interesting now for me. I will look at the current codebase. Is this noise and hb implementation that someone is doing already available in the VCS for me to have a look at and check the pattern of implementation? No .. and I am not sure how it will develop. You can look at the AC, DC, tran, and Fourier analysis to see how it fits. Everything is plugins, so it is easy to experiment with it. pz (spice method) is to ac as fourier is to tran. Another possibility is to make a pz that looks at saved data, as a postprocessor, and add the ability to do go anywhere on the S plane to AC, as opposed to the usual of traversing the j-omega axis. Another interesting type of analysis that Spice doesn't have is a semi-symbolic analysis, where the result is a transfer function, in S, that has some values carried through as symbols. I would have to help you a lot, but it would be a real accomplishment, and I think I know of a few places where you could get a paper out of it. .. at least a conference paper, maybe two, maybe even a journal paper. It may sound intimidating, but there are some features of C++ that make it a lot easier than in other languages. Any further discussion of it will be over the head of most people here, so ask about it on the gnucap-devel list, where it is absolutely on topic, if you want to know more. That is the place to ask more about things like the pz analysis too. Again, it is over the head of most people here, but a good match there. On Wednesday 11 February 2009, Stephen Williams wrote: Given the apparent bent towards analog in your selection of candidate projects, might I suggest you take a look at the gnucap Code Generator on the Icarus Verilog projects page? This is something that Al has been wanting, and also puts to use some of the nascent analog support in Icarus Verilog proper. I like this one too. It is an enabler that will make other enhancements easier, and something that is desperately needed as a model compiler. There are lots of people who want it and some real experts who can help. This sounds exciting too. But I am highly unsure about the things that I need to learn before taking this project up. The Icarus Project page says this project remains clear of the Iverilog core. It states that one might require knowledge of how to compile models for gnucap. Can some more light be thrown here please? Any nice starting pointers? I can then catch on and start rolling. Unsure???... you say you are doing a masters .. The projects we are talking about are beyond what I would expect an undergrad to do, but it should be ok for someone doing a masters, especially if you are considering a research oriented career. You will need to learn a lot, but that's the way it is supposed to be. It may be too late to do this, but if you can, I recommend a course in compilers. In this case, the parser is done. What is needed is a code generator, and that is similar to others that are done. So, you have a good starting point. The interface is well defined. A lot of the code generation is just copying with a different syntax. You can do a lot of that just by text substitution. Then the hard part is generating code for all of the partial derivatives. This means analyzing an expression, figuring out what partial derivatives to generate, and generating them. Usually, they are based on the chain rule. If you are interested in this one, again you can ask some of the harder questions on the gnucap-devel list, and also the Icarus Verilog developer list. You should probably subscribe to both. As to getting papers out of it, I think you could get a conference paper, but not a journal paper, from this one. Any of these are good projects. They are all challenging, and will really keep you busy all summer. Some of them could also be used for a master's thesis. It is possible that you could use it as a start for a Ph.D.
Re: gEDA-user: autoconf and pcb
Wow, Csound is still around? (assuming it's the same one) I messed with that more than a decade ago. Wow. Still around and better than ever! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
