Re: gEDA-user: translation standards (was: fritzing )
I don't think the standard is open. However I think it can be reversed engineered. I have done a lot of it already. There are at least a couple of third party translation programs that have already done it for the commercial programs. www.unisoft-cim.com/importers.htm https://wiki.altium.com/display/ADOH/Moving+to+Altium+Designer+from+Pads +Logic+and+PADS+Layout The actual file format specification is included with the PADS distribution in a pdf format. On Wed, 2009-05-13 at 23:14 +, Kai-Martin Knaak wrote: > On Wed, 13 May 2009 14:12:52 -0700, Steve Meier wrote: > > > I believe the electronics industry has already centered on the PADs > > ASCII file format which has the netlist, components, foor print's, > > layers, lines, vias etc. > > Is this standard open in any way? > That is, can it be read without signing a NDA statement? > > ---<(kaimartin)>--- > > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
Brendan Howell wrote: > Hi gEDAns, We looked at easily a dozen different GUI frameworks before > chosing Qt. > We don't really see Fritzing as competing with the other open > source/free EDA tools. Our target audience is largely hobbyists, > students, designers and artists: essentially, non-engineers. > Our long-term goal is to support file interchange with other EDAs, > especially gEDA and KiCAD so that as users reach the limits of what is > possible with Fritzing, they can move their project over to more > professional tools. > With that in mind, it would be great to collaborate. Thanks, I'll sign up on your list/forum. Although we don't use gEDA as a backend, I've learned an > awful lot by reading your code, docs and discussions. We might though if the GUI coding is as easy as you say. But, if using GTK along with Qt is trouble, we might just copy some of your UI design as settable in beginner mode geda_manager, a glue code for projects that is only half baked as yet. John Griessen -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: translation standards
Kai-Martin Knaak wrote: > On Wed, 13 May 2009 14:12:52 -0700, Steve Meier wrote: > >> I believe the electronics industry has already centered on the PADs >> ASCII file format which has the netlist, components, foor print's, >> layers, lines, vias etc. > > Is this standard open in any way? > That is, can it be read without signing a NDA statement? > Not sure if this could help: http://www.ashevillecommunity.org/hawker/pcb/pads/bmp2asc.html It's been a long time since I sat in front of a PADS system. AFAIR the file format was described in great detail in the help files and it might still be that way. On older systems probably in the shape of a book instead of a help file. Almost looked like the detailed documentation that came with the very first IBM XT PCs. -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: translation standards (was: fritzing )
On Wed, 13 May 2009 14:12:52 -0700, Steve Meier wrote: > I believe the electronics industry has already centered on the PADs > ASCII file format which has the netlist, components, foor print's, > layers, lines, vias etc. Is this standard open in any way? That is, can it be read without signing a NDA statement? ---<(kaimartin)>--- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cypress PSoC MiniProg under Linux
> > I use WebPack for Linux, it works just fine. Although, I don't use > > any of their programming cables. > > Don't touch their drivers with a barge pole.. use these: I said *cables* so of course none of the standard drivers would work for me anyway. I write my own. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cypress PSoC MiniProg under Linux
On Wed, 2009-05-13 at 15:41 -0400, DJ Delorie wrote: > > I have not already used their WebPack for Linux, but I am sure it > > works. > > I use WebPack for Linux, it works just fine. Although, I don't use > any of their programming cables. Don't touch their drivers with a barge pole.. use these: http://rmdir.de/~michael/xilinx/ I've successfully used a "Prog2" clone cable (parallel port - slow), Platform cable USB, and Platform cable USB II. (The latter two USB programmers are much much faster, but rather expensive!) Since ISE version 10.1, their software supports a libusb based driver natively. For 10.1, you need to set the environment variable: XIL_IMPACT_USE_LIBUSB=1 For 11.1, the libusb based driver is the default. In either case, if you want to use the parallel port programming cables without the evil kernel drivers, use the LD_PRELOAD library at the above link. Oh.. my first impressions of 11.1 is that is a pile of cra*. Segfaults all the time, and with the newer Qt / theme their using, the GUI seems more cluttered, less compact. Schematic format is now XML based. I can't think it is related, but the tools are _very_ slow doing even simple tasks like opening and saving schematics. I only upgraded to 11.1 because of a nasty programming bug (segfault) in 10.1 programming an SPI flash via IMPACT. 11.1 introduces new bugs in other aspects of the process though! -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: translation standards
John Doty wrote: > On May 13, 2009, at 3:01 PM, John Griessen wrote: >> al davis wrote: >> pad/pin centers >> that are defined as center of main part of a pad and center of hole >> circles, and also >> pad numbers? > > Remember that Al's vision includes schematic translation. > I have not read his starting point document yet...Ooops. Al said he wants no drawing points or line definitions as part of it, which suggests a diagram description language that leaves the exact placement of lines or pixels up to the translator. Translated schematics or footprints would look similar in ordering pf pins around packages maybe, but all proportions might be stretched or shrunk in translation since that info is not in the transfer standard. Hmmmsounds hard to automate. John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: translation standards (was: fritzing )
I believe the electronics industry has already centered on the PADs ASCII file format which has the netlist, components, foor print's, layers, lines, vias etc. I have bumped into pcb and assembly shop requests for this a few times where they use the information for programming their pick and place equipment as well as their flying probe testers. Plus if you wan't to translate projects back and forth between commercial cad programs this seems to be the most commonly supported format. Steve Meier On Wed, 2009-05-13 at 16:01 -0500, John Griessen wrote: > al davis wrote: > > > My proposal does consider placement, which should be enough. > > > > It is essentially a netlist format. That's the idea. > > How about having a netlist format that holds footprint center, plus pad/pin > centers > that are defined as center of main part of a pad and center of hole circles, > and also > pad numbers? > > That would make a netlist skeleton version of a footprint. > > I think Brendan of the fritzing project wants the descriptive artwork lines > too, though. > > Those could be defined by a generic standard as vector line segments relative > to a center zero > easily enough. For centroid based drawings like pcb and RS274-X use, a line > width number would be > part of it too. > > But then when you get to square pads that are based on a zero length line > segment what do you do? > > Most 3D models used now are edge and surface based, or if 2D like postscript, > edge and outline based. > > Square pads suggest using outline based graphics and round suggests centroid > based, so a standard would need both. > Defining outline based graphics in output to the standard format would mean > any other importing to centroid based > would need to convert, and them you get into questions of "can you do it > losslessly?" > > John Griessen > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: translation standards (was: fritzing )
On May 13, 2009, at 3:01 PM, John Griessen wrote: > al davis wrote: > >> My proposal does consider placement, which should be enough. >> >> It is essentially a netlist format. That's the idea. > > How about having a netlist format that holds footprint center, plus > pad/pin centers > that are defined as center of main part of a pad and center of hole > circles, and also > pad numbers? Remember that Al's vision includes schematic translation. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cypress PSoC MiniProg under Linux
Chris Smith wrote: > Eric Brombaugh wrote: >> I also use Xilinx ISE (both full-blown and Webpack) under Linux with no >> difficulties. > > I've used that too, and it's a great source of irritation and amazement > to me that they manage to produce a 1.4GB install file to program a > device the size of a postage stamp! :( Yes, and that 1.4GB download balloons out to > 4GB after it's decompressed into the final hierarchy. I did manage to strip a whole lot of junk out of it and fit it onto a 2GB SD card for use with an eeePC901 under Ubuntu though. >> or I copy bitstreams to an SD card which is loaded into the FPGA at >> boot time via an on-board MCU. > > Would you mind elaborating a little on this 'bitstream' copying and > loading technique? I've got a home-made board with an NXP LPC2148 ARM processor driving a Xilinx XC3S250E FPGA via one of the SPI ports. At boot time the ARM reads the bitstream out of an SD card via a FAT filesystem, strips off the header and feeds it to the FPGA in slave-serial mode. After the FPGA is configured, the configuration clk/data inputs become a SPI port and that's how the ARM talks to the new FPGA design. More info (and source code) here: http://members.cox.net/ebrombaugh1/synth/armfpga/index.html Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: naming and creation of 54-pin TSOP II (400 mil) footprint, request for help
Hi Jelle, On Wed, 2009-05-13 at 14:45 +0200, Jelle de Jong wrote: > Hello everybody, > > I am trying to create a footprint with a correct name using the IPC-7351 > Naming Convention for Standard SMT Land Patterns. > > But I am having some issues, i am using the below document to learn about > the naming convention: > https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/footprint-name-spec.pdf > > The footprint I want to make is a 54-pin TSOP II (400 mil), see: > https://secure.powercraft.nl/svn/openarm/trunk/doc/SDRAM/MT48LC16M16A2P-7E/256MSDRAM.pdf > # page 75, 54-Pin Plastic TSOP > > I tried to figure it out but I don't know what the lead span 1(L1) is? > > footprint: > TSSOP-65P-640L1-54N > 54-pin TSOP II (400 mil) > TSSOP pin spacing, lead span 1, pin count > P pin spacingdimension > L1 lead span 1dimension > N pin count count > > I also learned to create footprints with the following document: > https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/land_patterns_20070818.pdf > I had my ups and downs learning this and had some help trough IRC. > > However the creation of a 54-pin TSOP II seems to be able to automate > using a script. > > I looked at the following, but it uses a license I disagree with and I > can't figure out how it works, I prefer OSI and GPL compatible licenses. > http://www.luciani.org/geda/pcb/pcb-perl-library.html > > Would somebody be able to help me out, what should the name of the > footprint become and what scripts can I use to make the footprint and how > can I do this? > I would go for a name like: "TSSOP80P1176X120-54N.fp" as in the IPC standard IPC-7351 0.80 mm pitch, 11.76 mm lead span, X 1.20 mm height - 54 leads with Nominal pad conditions (as one of the following: Least, Nominal, Most). Maybe it is a wise thing to avoid "-" characters in footprint file names or to have a "use-files" line in your gsch2pcb config file and pass a --skip-m4 flag to disable m4 macro generated footprints to goof up your pcb stuff. Maybe include a vendor and part name too, while footprint artwork recommendations may vary across vendors and specific parts. Kind regards, Bert Timmerman. > Could somebody help me out by making an example for the 54-pin TSOP II > footprint? > > I got a lot more footprints to make, and I can use all the help, since > time is getting really sparse. > > OpenARM Single Board Computer Project: > https://secure.powercraft.nl/websvn/openarm/ > > Thanks in advance, > > Jelle de Jong > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: translation standards (was: fritzing )
al davis wrote: > My proposal does consider placement, which should be enough. > > It is essentially a netlist format. That's the idea. How about having a netlist format that holds footprint center, plus pad/pin centers that are defined as center of main part of a pad and center of hole circles, and also pad numbers? That would make a netlist skeleton version of a footprint. I think Brendan of the fritzing project wants the descriptive artwork lines too, though. Those could be defined by a generic standard as vector line segments relative to a center zero easily enough. For centroid based drawings like pcb and RS274-X use, a line width number would be part of it too. But then when you get to square pads that are based on a zero length line segment what do you do? Most 3D models used now are edge and surface based, or if 2D like postscript, edge and outline based. Square pads suggest using outline based graphics and round suggests centroid based, so a standard would need both. Defining outline based graphics in output to the standard format would mean any other importing to centroid based would need to convert, and them you get into questions of "can you do it losslessly?" John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cypress PSoC MiniProg under Linux
Eric Brombaugh wrote: > > I also use Xilinx ISE (both full-blown and Webpack) under Linux with no > difficulties. I've used that too, and it's a great source of irritation and amazement to me that they manage to produce a 1.4GB install file to program a device the size of a postage stamp! :( > or I copy bitstreams to an SD card which is loaded into the FPGA at > boot time via an on-board MCU. Would you mind elaborating a little on this 'bitstream' copying and loading technique? Chris -- Chris Smith signature.asc Description: OpenPGP digital signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cypress PSoC MiniProg under Linux
DJ Delorie wrote: >> I have not already used their WebPack for Linux, but I am sure it >> works. > > I use WebPack for Linux, it works just fine. Although, I don't use > any of their programming cables. > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > > I also use WebPACK including the internal downloader (impact) with the opensource libusb-driver which emulates Jungo Windrvr for my Spartan-3AN developer board. It has a CY7C68013 USB<->JTAG interface (closed hardware and firmware (even the wires are deleted from the PCB and schematic documentation). It works good. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: geda cygwin package (Re: geda-user Digest, Vol 36, Issue 35)
Subject: Re: gEDA-user: geda cygwin package From: "David C. Kerber" [1] Date: Wed, 13 May 2009 13:08:07 -0400 To: gEDA user mailing list [2] To: gEDA user mailing list [3] I could offer up space on my personal web site as well. Only 2Mbps ougoing BW, but there's no monthly limit so if only one or two people are hitting it at a time, it would probably suffice. Dave Hey, why not setup a torrent tracker (or use a public one) ? References 1. mailto:dker...@warrenrogersassociates.com 2. mailto:geda-user@moria.seul.org 3. mailto:geda-user@moria.seul.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cypress PSoC MiniProg under Linux
Stefan Salewski wrote: > On Wed, 2009-05-13 at 12:03 -0700, Eric Brombaugh wrote: >> Since their development >> IDE is Win-only I didn't see much point in pursuing it further. > > Maybe my understanding of your comment is wrong, but to make it clear: > Xilinx FPGA development tools called WebPack are available free of costs > for Windows and Linux. Downloading code to the FPGA may be a problem, I > guess the parport cable for the old Spartan-3 boards works. I have not > already used their WebPack for Linux, but I am sure it works. This was > the reason why I decided using Spartan-3E for my DSO board, not Altera > chips. Altera has tools for Linux too, but you have to buy it (It may > work with Wine under Linux?). The OP wasn't talking about Xilinx tools. He was asking about the Cypress PSoC processor that's also on the Avnet S3A board, and that's what my comments were directed towards. I also use Xilinx ISE (both full-blown and Webpack) under Linux with no difficulties. I don't do Xilinx downloads via JTAG under Linux though - I either use a Xilinx USB/JTAG pod under WinXP, or I copy bitstreams to an SD card which is loaded into the FPGA at boot time via an on-board MCU. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gschem: ERROR: Wrong type (expecting string): #f
hello, just build the development release (gschem 1.5.2.20090328) and fired it up. First time it worked. After closing it and try to restart it I get this error, ERROR: Wrong type (expecting string): #f . What does it mean? regards Felix ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gschem: ERROR: Wrong type (expecting string): #f
hello, just build the development release (gschem 1.5.2.20090328) and fired it up. First time it worked. After closing it and try to reopen it I get this error, ERROR: Wrong type (expecting string): #f . What does it mean? regards Felix ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cypress PSoC MiniProg under Linux
> I have not already used their WebPack for Linux, but I am sure it > works. I use WebPack for Linux, it works just fine. Although, I don't use any of their programming cables. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cypress PSoC MiniProg under Linux
On Wed, 2009-05-13 at 12:03 -0700, Eric Brombaugh wrote: > Since their development > IDE is Win-only I didn't see much point in pursuing it further. Maybe my understanding of your comment is wrong, but to make it clear: Xilinx FPGA development tools called WebPack are available free of costs for Windows and Linux. Downloading code to the FPGA may be a problem, I guess the parport cable for the old Spartan-3 boards works. I have not already used their WebPack for Linux, but I am sure it works. This was the reason why I decided using Spartan-3E for my DSO board, not Altera chips. Altera has tools for Linux too, but you have to buy it (It may work with Wine under Linux?). Related, but only in german language: http://www.mikrocontroller.net/topic/136915#new ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
On May 13, 2009, at 12:42 PM, al davis wrote: > On Wednesday 13 May 2009, John Doty wrote: >> The graphics problem is 1000x harder, but gets almost no >> mention in your proposal. > > The intent is not to translate the symbols themselves, any more > than moving between text markup formats translates fonts. The difference is that a schematic is profoundly graphical, in a way that text isn't. > > My proposal does consider placement, which should be enough. I think few would consider this enough. Without graphics, placement is of little use. And for graphic-free translation, the pins2gsch approach is pretty trivial, at least for simple netlist formats (Verilog is somewhat harder to parse). John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cypress PSoC MiniProg under Linux
Tamas Szabo wrote: > > I just recieved an Avnet Spartan-3A Evaluation Kit. It has the above > mentioned interface for downloading configuration. I only found Win > based software for it. > > Has anyone any experience with it under Linux? I did some work with PSoC a few years ago and wasn't able to find any Linux drivers for their USB programming dongle. Since their development IDE is Win-only I didn't see much point in pursuing it further. I believe that their MCU is based on an 8-bit Renesas architecture so there may be a GCC-based toolchain available, but you'll have a tough time finding any open-source software for setting up the analog and digital arrays. Plus, you'd be giving up all the firmware interface routines that their IDE automatically links in when you use the Cypress tools & libraries. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Cypress PSoC MiniProg under Linux
Hi, Maybe off-topic a bit... I just recieved an Avnet Spartan-3A Evaluation Kit. It has the above mentioned interface for downloading configuration. I only found Win based software for it. Has anyone any experience with it under Linux? Thanks, /sza2 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
On Wednesday 13 May 2009, John Doty wrote: > The graphics problem is 1000x harder, but gets almost no > mention in your proposal. The intent is not to translate the symbols themselves, any more than moving between text markup formats translates fonts. My proposal does consider placement, which should be enough. It is essentially a netlist format. That's the idea. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
On May 13, 2009, at 10:27 AM, al davis wrote: > > A while back I made a proposal for a file interchange system > that is neutral in the sense that it is not tied to any > particular target. It's based on the structural subset of > Verilog. But that's essentially a netlist format. It's already easy to translate from sch to just about any netlist format you want, and (as I've shown: http://archives.seul.org/geda/dev/Nov-2008/msg00069.html) it's even easier to back translate as long as you don't care about carrying across the graphics and creating a human-readable result. The graphics problem is 1000x harder, but gets almost no mention in your proposal. Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Signal Source Setup for Electric Guitar?
Michael B Allen wrote: > On Tue, May 12, 2009 at 6:43 PM, Joerg wrote: >> Michael B Allen wrote: >>> Anyway it looks like their AC generator is using 2mV. So the 20mV >>> value I used to get a good output SIN looks closer to reality which >>> means my model is probably ok. >>> >>> I wish I had a real oscilloscope to find out what my guitar is really >>> putting out but xoscope doesn't seem to produce voltages (but I'm not >>> surprised since the sound card is probably oblivious to such things). >>> Maybe I'll have to get one of those PC oscilloscopes. >>> >> I don't know much about E-guitars, other than having enjoyed a live >> rockband here this weekend. But AFAIK the magnetic pickups are high >> impedance, above 100kohms. Much higher if piezo. Sound cards in contrast >> are in the kiloohm range so most likely the signal from your guitar >> collapsed the instant you plugged it into the sound card. Also, keep in >> mind that sound card inputs often carry a little DC voltage to feed >> electret microphones. You can measure it with a voltmeter. That can >> cause a DC current through the pickup coil and saturate the core. >> >> If you want to display the waveforms or an FFT spectrum on the PC >> cheaply you could use an emitter follower as a buffer so the voltage >> gets transferred 1:1. Then a high input impedance is provided to the >> guitar even if you connect a sound card. > > I think I would rather buy a PC oscilloscope only because building the > buffer circuit requires time and knowledge that I don't really have. > Again, this is not work - it's just a hobby. I'm still trying to wrap > my head around the concept of impedance in general and especially it's > relation to frequency and how capacitors work and so on. So I think it > would be better to get something that I know is going to just work. > > Has anyone tried the "Parallax USB Oscilloscope"? It's only $139. It > can certainly handle audio and I assume it will tell me voltages, do > FFT etc. The only problem I can see is that only has 8 bits of > resolution. > No idea. All the PC-scopes I've looked at so far only produced yawning. The Picoscopes seem pretty good but expensive. >> Probably the input impedance must be set to a certain value (by means of >> an extra resistors) so the guitar "likes it" and "sounds alright". > > This is very interesting. I had no idea the difference between the > impedance of the sound card and a guitar amp was so significant. > > I built the circuit last night (although I haven't tried it yet). So > now I have to wonder about it's impedance wrt to the sound card. > If you connect it smack to the collector of a transistor (via a capacitor, of course) then the impedance will be loading it down. The gain of a single transistor stage like yours is roughly equal the combined resistance hanging on the collector node divided by the emitter resistor. So your gain would drop. > Another thing I was thinking about doing was using siggen to feed the > preamp circuit a SIN and then feed the result back into the sound > card. So what is the impedance of the sound card output jack? Now I > need a high impedance SIN generator. > That depends on the card you have. Some can drive small speakers directly and are in the 10-20ohm range. Others only offer line level output and that would be in the kiloohm region. > I get the feeling the whole sound card solution is not going to be ok. > I either need a high impedance buffer circuit or an oscilloscope. > Read up on them. I have used the sound card of laptops at clients and found noise problem that >$10k audio spectrum analyzers were unable to see. Sometimes to the utter amazement of engineers witnessing this. Seen some jaws drop ... > This is a lot harder than I thought. I think I have a lot of reading to do ... > Yep. And the good news is that thanks to the Internet such information is essentially free of charge. Or to stay with the tune of this group, open source :-) -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: geda cygwin package
On Wed, 13 May 2009 17:32:37 +0100, Peter Baxendale wrote: > I routinely package up cygwin with built gEDA cygwin executables once a > year for our Windows users here. Because it's once a year it gets a bit > out of date, but I'd be happy to make it available to anyone interested. > It has a readme to tell you how to install it all and includes swcad and > the windows installer for gerbv. Unfortunately the zip is too big (133M) > for the measly quota I get on our externally accessible servers here. > It's tested on students, which is usually a pretty tough test to pass... If you send the zip via mail to kn...@iqo.uni-hannover.de I'd make it available on my slightly inofficial server here at hannover university. Admin is me, so no crippling quotas involved. It would be accessible to the rest of the internet since I arranged for an open port 80 in the firewall. This is the slightly inofficial bit... If you are not happy with such a publically available download link, I can arrange for internal use in hannover only. ---<(kaimartin)>--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmk&op=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: geda cygwin package
On Wednesday 13 May 2009, Peter Baxendale wrote: > I routinely package up cygwin with built gEDA cygwin > executables once a year for our Windows users here. Because > it's once a year it gets a bit out of date, but I'd be happy > to make it available to anyone interested. It has a readme to > tell you how to install it all and includes swcad and the > windows installer for gerbv. Unfortunately the zip is too big > (133M) for the measly quota I get on our externally > accessible servers here. It's tested on students, which is > usually a pretty tough test to pass... I have space on gnucap.org, but you will need to take out swcad. gEDA also has space, but again you will need to take out swcad. Gnucap has always worked on windows. It works with gEDA, with gnetlist generating a spice file, as well as any simulator does. How about using Gnucap? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
On Tue, May 12, 2009 at 6:31 PM, Kai-Martin Knaak wrote: > On Mon, 11 May 2009 19:14:26 -0400, DJ Delorie wrote: > >>> PS: I use gEDA on cygwin. I have a cygwin mirror at work, and I made a >>> cygwin package for gEDA, as well as making a modified cygwin installer >>> so that coworkers can run the installer to automatically install all >>> the packages I think they need from our local mirror, including my gEDA >>> package. It was a PITA to set up, and I doubt many people at companies >>> even an order of magnitude bigger than where I work will devote the >>> resources to do something like that. >> >> If you've done all this work, why not upload it to gpleda.org or some >> other public place so that others can benefit from it? That would >> pretty much end the argument if it's done. > > +1 > I'd love to point my coworkers to a place where they can get everything > they need to install gschem/pcb in a windows context. If web space is an > issue, I may dedicate bandwidth either on my private website or at the > university of Hannover. > I've assembled all the libraries and such so I can type "make burncd" in my project directory and it will burn a CD of with the design files and copies of Windows builds of pcb and gerbv and the necessary DLLs. It also makes two batch files in the root of the CD: "open_gerbers.bat" and "open_pcb.bat". These run gerbv.exe and pcb.exe respectively off the CD, loading design files off the CD as well. I figure this is an easy way to give clients a copy of my work, and also is a gentle introduction to gEDA. It's not very GPL-compliant, as I just grabbed binaries off the web (building software for Windows is not something I enjoy). But I could maybe fix it up into something releasable if anyone's interested. Regards, Mark markra...@gmail -- Mark Rages, Engineer Midwest Telecine LLC markra...@midwesttelecine.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Deafult gap between copper pin/pad and resist
On Wed, 13 May 2009 17:41:54 +0200, Kovács Levente wrote: >>> You can change the mask size after you convert the >>> footprint, of course. > > With the GUI? How? 1) activate tht display of the mask 2) let the mouse float above the pin 3) type [k] several times to increase mask clearance 3a) type [SHIFT-k] to decrease mask clearance ---<(kaimartin)>--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmk&op=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: geda cygwin package
I could offer up space on my personal web site as well. Only 2Mbps ougoing BW, but there's no monthly limit so if only one or two people are hitting it at a time, it would probably suffice. Dave > -Original Message- > From: geda-user-boun...@moria.seul.org > [mailto:geda-user-boun...@moria.seul.org] On Behalf Of Peter Baxendale > Sent: Wednesday, May 13, 2009 12:33 PM > To: gEDA user mailing list > Subject: gEDA-user: geda cygwin package > > On Tue, 2009-05-12 at 23:31 +, Kai-Martin Knaak wrote: > > > I'd love to point my coworkers to a place where they can get > > everything they need to install gschem/pcb in a windows context. If > > web space is an issue, I may dedicate bandwidth either on > my private > > website or at the university of Hannover. > > I routinely package up cygwin with built gEDA cygwin > executables once a year for our Windows users here. Because > it's once a year it gets a bit out of date, but I'd be happy > to make it available to anyone interested. > It has a readme to tell you how to install it all and > includes swcad and the windows installer for gerbv. > Unfortunately the zip is too big (133M) for the measly quota > I get on our externally accessible servers here. > It's tested on students, which is usually a pretty tough test > to pass... > > -- > -- > -- > Peter Baxendale University of Durham > peter.baxend...@durham.ac.uk School of Engineering > tel +44 191 33 42492 South Road > fax +44 191 33 42408 Durham DH1 3LE > England > -- > -- > > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A not too serious PCB question
On Wed, May 13, 2009 at 04:16:26PM +0200, Stefan Salewski wrote: > Someone asked how one can build PCB boards like this: > > http://www.mikrocontroller.net/topic/137821#new > > (Click on the picture too enlarge) > > This layout may have advantages if PCB is made mechanical, i.e. by > milling machines. > > So I asked myself is current PCB can do it -- I guess not, but I may be > wrong. Sure, you just route the board as usual, and in a post-processing step you retain the same net topology but you achieve it by cutting up a plane. PCB would need a new exporter, and you wouldn't have direct control over the output (you'd probably end up drawing some spurious traces to steer it), but it could be done. -- Ben Jackson AD7GD http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: geda cygwin package
On Tue, 2009-05-12 at 23:31 +, Kai-Martin Knaak wrote: > I'd love to point my coworkers to a place where they can get everything > they need to install gschem/pcb in a windows context. If web space is an > issue, I may dedicate bandwidth either on my private website or at the > university of Hannover. I routinely package up cygwin with built gEDA cygwin executables once a year for our Windows users here. Because it's once a year it gets a bit out of date, but I'd be happy to make it available to anyone interested. It has a readme to tell you how to install it all and includes swcad and the windows installer for gerbv. Unfortunately the zip is too big (133M) for the measly quota I get on our externally accessible servers here. It's tested on students, which is usually a pretty tough test to pass... -- Peter Baxendale University of Durham peter.baxend...@durham.ac.uk School of Engineering tel +44 191 33 42492 South Road fax +44 191 33 42408 Durham DH1 3LE England ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Signal Source Setup for Electric Guitar?
On Tue, May 12, 2009 at 6:43 PM, Joerg wrote: > Michael B Allen wrote: >> Anyway it looks like their AC generator is using 2mV. So the 20mV >> value I used to get a good output SIN looks closer to reality which >> means my model is probably ok. >> >> I wish I had a real oscilloscope to find out what my guitar is really >> putting out but xoscope doesn't seem to produce voltages (but I'm not >> surprised since the sound card is probably oblivious to such things). >> Maybe I'll have to get one of those PC oscilloscopes. >> > > I don't know much about E-guitars, other than having enjoyed a live > rockband here this weekend. But AFAIK the magnetic pickups are high > impedance, above 100kohms. Much higher if piezo. Sound cards in contrast > are in the kiloohm range so most likely the signal from your guitar > collapsed the instant you plugged it into the sound card. Also, keep in > mind that sound card inputs often carry a little DC voltage to feed > electret microphones. You can measure it with a voltmeter. That can > cause a DC current through the pickup coil and saturate the core. > > If you want to display the waveforms or an FFT spectrum on the PC > cheaply you could use an emitter follower as a buffer so the voltage > gets transferred 1:1. Then a high input impedance is provided to the > guitar even if you connect a sound card. I think I would rather buy a PC oscilloscope only because building the buffer circuit requires time and knowledge that I don't really have. Again, this is not work - it's just a hobby. I'm still trying to wrap my head around the concept of impedance in general and especially it's relation to frequency and how capacitors work and so on. So I think it would be better to get something that I know is going to just work. Has anyone tried the "Parallax USB Oscilloscope"? It's only $139. It can certainly handle audio and I assume it will tell me voltages, do FFT etc. The only problem I can see is that only has 8 bits of resolution. > Probably the input impedance must be set to a certain value (by means of > an extra resistors) so the guitar "likes it" and "sounds alright". This is very interesting. I had no idea the difference between the impedance of the sound card and a guitar amp was so significant. I built the circuit last night (although I haven't tried it yet). So now I have to wonder about it's impedance wrt to the sound card. Another thing I was thinking about doing was using siggen to feed the preamp circuit a SIN and then feed the result back into the sound card. So what is the impedance of the sound card output jack? Now I need a high impedance SIN generator. I get the feeling the whole sound card solution is not going to be ok. I either need a high impedance buffer circuit or an oscilloscope. This is a lot harder than I thought. I think I have a lot of reading to do ... Mike -- Michael B Allen Java Active Directory Integration http://www.ioplex.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
On Wednesday 13 May 2009, Brendan Howell wrote: > for expediency we hacked up a quick output to Eagle. I saw that, opened mouth too soon. > While the demo was cool, it quickly turned into an unpleasant > experience for coders as we reached the limitations of the > GUI framework (not to mention the problems of being dependent > on proprietary CAD tools). So, last summer we threw all the > old code out and started over from scratch. Then saw that, thank you. On Wednesday 13 May 2009, Brendan Howell wrote: > Our long-term goal is to support file interchange with > other EDAs, especially gEDA and KiCAD so that as users reach > the limits of what is possible with Fritzing, they can move > their project over to more professional tools. > With that in mind, it would be great to collaborate. I'm > currently working on a gEDA/PCB footprint importer to take > advantage of the great library that you guys have. I also > have "export to gEDA" on my list as it would be really great > to be able to export a netlist that gnetlist can understand. A while back I made a proposal for a file interchange system that is neutral in the sense that it is not tied to any particular target. It's based on the structural subset of Verilog. I think Fritzing, Kicad, and gEDA should all benefit from doing it. Also, if there is a standard interchange format, new tools can be developed to interface to the standard, rather than to any particular toolset. Here's a start: http://geda.seul.org/wiki/geda:format_translation I have some starter code, which may need to be replaced, as part of Gnucap. Regarding the "footprint importer" .. This needs to be the same. There needs to be a format for describing footprints and symbols that does not belong to any application in particular, with an easy conversion to any format. None of the tools should have the burden of converting to and from each other. All of them should support a standard. By supporting the standard, you automatically support all other tools that support that standard. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A not too serious PCB question
Kovács Levente wrote: > Joerg írta: >> Bill Gatliff wrote: >>> Andy Fierman wrote: Could open a whole new topological discussion on auto routers though :) >>> I don't know how you could automate the boundary descriptions, but once >>> you had that then it looks like a basic flood-fill... >>> >> Typically this isn't done fully automated. One method is to autoroute or >> do a regular hand layout with default trace width, fatten up or fill >> every other trace by hand section by section, then do an auto-fill for >> the remaining traces. > > It would be easyer with PCB, if polygons had net attribute. I mean if > you place a polygon on the layout, it is just a graphical object. You > have to control the gaps, etc. manually. > I don't know the PCB sofware of gEDA much but can't you set a default clearance that would make sure the gaps are all the same after auto-fill? [...] -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Deafult gap between copper pin/pad and resist
Kai-Martin Knaak írta: > On Mon, 11 May 2009 17:52:04 -0400, DJ Delorie wrote: > Note that you can change PCB's internal default by changing MASKFRAME in the top-level globalconst.h. >>> Setting must be done at compile time, is it ? >> That default, yes. > > Would it be difficult to add this to the list of parameters read from the > preferences/settings file? ...and make it editable by the "routing style". That would be fantastic! :-) That implys file format change. :-( >> You can change the mask size after you convert the >> footprint, of course. With the GUI? How? > What about via tenting? Is there a compile time switch to get rid of this > default? Open vias are convenient places for all kinds dirty tricks to > fix errors in the layout. At my former dayjob we deliberately set via > hole size to a value that fits the diameter of patch wires. > > ---<(kaimartin)>--- > > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A not too serious PCB question
Joerg írta: > Bill Gatliff wrote: >> Andy Fierman wrote: >>> Could open a whole new topological discussion on auto routers though :) >>> >> I don't know how you could automate the boundary descriptions, but once >> you had that then it looks like a basic flood-fill... >> > > Typically this isn't done fully automated. One method is to autoroute or > do a regular hand layout with default trace width, fatten up or fill > every other trace by hand section by section, then do an auto-fill for > the remaining traces. It would be easyer with PCB, if polygons had net attribute. I mean if you place a polygon on the layout, it is just a graphical object. You have to control the gaps, etc. manually. > It would theoretically be possible to automate by having the SW perform > ratiometric trace width adaptation but it would require that it also > handles off-center situations where the density increases. I have never > heard of a layout program that can do all of this by itself, but who knows. > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A not too serious PCB question
On Wed, May 13, 2009 at 10:16 AM, Stefan Salewski <[1]m...@ssalewski.de> wrote: Someone asked how one can build PCB boards like this: [2]http://www.mikrocontroller.net/topic/137821#new (Click on the picture too enlarge) This layout may have advantages if PCB is made mechanical, i.e. by milling machines. Was the PCB layout done to maximize the copper or did a pre-processing program generate the machine instructions to minimize milling time? (* jcl *) -- You can't create open hardware with closed EDA tools. [3]http://www.luciani.org References 1. mailto:m...@ssalewski.de 2. http://www.mikrocontroller.net/topic/137821#new 3. http://www.luciani.org/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fritzing
Hi gEDAns, I'm one of the developers of Fritzing. I know I'm coming to this thread rather late but I have a few comments and clarifications... First, I think some of the initial debate and criticism was based on looking at our old (archive.fritzing.org) web site that had a bunch of early stuff that is completely obsolete. This first "proof-of-concept" version of Fritzing was written using Java on top of multiple Eclipse frameworks and for expediency we hacked up a quick output to Eagle. While the demo was cool, it quickly turned into an unpleasant experience for coders as we reached the limitations of the GUI framework (not to mention the problems of being dependent on proprietary CAD tools). So, last summer we threw all the old code out and started over from scratch. We decided to go with Qt for aesthetic as well as technical reasons. For us, it makes coding C++ almost as easy as working in a higher level language, while still giving us every increment of speed that we want. It has support for 90% of what we need without external libs. Docs are great. It's very portable; we release on 4 platforms with just a few ifdefs. We looked at easily a dozen different GUI frameworks before chosing Qt. We don't really see Fritzing as competing with the other open source/free EDA tools. Our target audience is largely hobbyists, students, designers and artists: essentially, non-engineers. Our long-term goal is to support file interchange with other EDAs, especially gEDA and KiCAD so that as users reach the limits of what is possible with Fritzing, they can move their project over to more professional tools. With that in mind, it would be great to collaborate. I'm currently working on a gEDA/PCB footprint importer to take advantage of the great library that you guys have. I also have "export to gEDA" on my list as it would be really great to be able to export a netlist that gnetlist can understand. Please feel free drop in on our forums to give us comments, critique and code. Although we don't use gEDA as a backend, I've learned an awful lot by reading your code, docs and discussions. It's great stuff! Brendan Howell http://fritzing.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A not too serious PCB question
Bill Gatliff wrote: > Andy Fierman wrote: >> Could open a whole new topological discussion on auto routers though :) >> > > I don't know how you could automate the boundary descriptions, but once > you had that then it looks like a basic flood-fill... > Typically this isn't done fully automated. One method is to autoroute or do a regular hand layout with default trace width, fatten up or fill every other trace by hand section by section, then do an auto-fill for the remaining traces. It would theoretically be possible to automate by having the SW perform ratiometric trace width adaptation but it would require that it also handles off-center situations where the density increases. I have never heard of a layout program that can do all of this by itself, but who knows. -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A not too serious PCB question
Andy Fierman wrote: > Could open a whole new topological discussion on auto routers though :) > I don't know how you could automate the boundary descriptions, but once you had that then it looks like a basic flood-fill... b.g. -- Bill Gatliff b...@billgatliff.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A not too serious PCB question
Andy Fierman wrote: > Interesting idea. > > Looks like it's a single (maybe double) sided through hole PCB. > Probably only a low frequency board. > > I can see this may have some advantages for high current and therefore > maybe switch mode PSU's but it may only have limited use for the > following reasons: > > i) All tracks have the same gap between them. This may have adverse > implications for crosstalk. > ii) Track dimensions are very irregular. This makes it almost > impossible to provide a controlled impedance. Therefore limited to > only low frequency / slow edge applications. > > Could open a whole new topological discussion on auto routers though :) > > 2009/5/13 Stefan Salewski : >> Someone asked how one can build PCB boards like this: >> >> http://www.mikrocontroller.net/topic/137821#new >> >> (Click on the picture too enlarge) >> >> This layout may have advantages if PCB is made mechanical, i.e. by >> milling machines. >> >> So I asked myself is current PCB can do it -- I guess not, but I may be >> wrong. >> If it supports copper pour well enough (I don't know PCB designer much but would be surprised if such a fine program didn't) then it should be able to do that. This is often done to reduce the amount of chemicals needed in PCB fab. Especially in areas of the world where on-site recycling isn't really happening yet. With the advent of SMT power packages such as DPAK this art enjoys a bit of a renaissance. -- Regards, Joerg http://www.analogconsultants.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A not too serious PCB question
Stefan Salewski wrote: > http://www.mikrocontroller.net/attachment/50837/Beispiel.jpg > This layout may have advantages if PCB is made mechanical, i.e. by > milling machines. That kind of layout has etchant cost minimization as advantage also. John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A not too serious PCB question
Interesting idea. Looks like it's a single (maybe double) sided through hole PCB. Probably only a low frequency board. I can see this may have some advantages for high current and therefore maybe switch mode PSU's but it may only have limited use for the following reasons: i) All tracks have the same gap between them. This may have adverse implications for crosstalk. ii) Track dimensions are very irregular. This makes it almost impossible to provide a controlled impedance. Therefore limited to only low frequency / slow edge applications. Could open a whole new topological discussion on auto routers though :) 2009/5/13 Stefan Salewski : > Someone asked how one can build PCB boards like this: > > http://www.mikrocontroller.net/topic/137821#new > > (Click on the picture too enlarge) > > This layout may have advantages if PCB is made mechanical, i.e. by > milling machines. > > So I asked myself is current PCB can do it -- I guess not, but I may be > wrong. > > > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > -- Cheers, Andy. Signality Solutions tel: +44 (0) 5601 720 580 skype: andyfierman www.signality.co.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Signal Source Setup for Electric Guitar?
Gareth Edwards wrote: >>> I wish I had a real oscilloscope to find out what my guitar is really >>> putting out An old Tek oscilloscope ($100) and a FET input probe ($50) would show you a lot. join teksco...@yahoogroups.com to find out more. > > Unless you are building a pickup, don't get too hung up on modelling > it - it's a complex and changing impedance across frequency (stray and > interwinding capacitance, leakage inductance, DC resistance etc) and > the unit-to-unit variation in impedance and output voltage is large. > You've already spotted that cable capacitance plays a part - the tone > and volume controls loading the pickup are probably just as important. That's where all those Hendrix effects of bending the guitar neck get "picked up". The whole guitar is a sensor. JG -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: A not too serious PCB question
Someone asked how one can build PCB boards like this: http://www.mikrocontroller.net/topic/137821#new (Click on the picture too enlarge) This layout may have advantages if PCB is made mechanical, i.e. by milling machines. So I asked myself is current PCB can do it -- I guess not, but I may be wrong. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: naming and creation of 54-pin TSOP II (400 mil) footprint, request for help
Jelle de Jong wrote: > Hello everybody, > > I am trying to create a footprint with a correct name using the IPC-7351 > Naming Convention for Standard SMT Land Patterns. > > But I am having some issues, i am using the below document to learn about > the naming convention: > https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/footprint-name-spec.pdf > > The footprint I want to make is a 54-pin TSOP II (400 mil), see: > https://secure.powercraft.nl/svn/openarm/trunk/doc/SDRAM/MT48LC16M16A2P-7E/256MSDRAM.pdf > # page 75, 54-Pin Plastic TSOP > > I tried to figure it out but I don't know what the lead span 1(L1) is? > > footprint: > TSSOP-65P-640L1-54N > 54-pin TSOP II (400 mil) > TSSOP pin spacing, lead span 1, pin count > P pin spacingdimension > L1 lead span 1dimension > N pin count count > > I also learned to create footprints with the following document: > https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/land_patterns_20070818.pdf > I had my ups and downs learning this and had some help trough IRC. > > However the creation of a 54-pin TSOP II seems to be able to automate > using a script. > > I looked at the following, but it uses a license I disagree with and I > can't figure out how it works, I prefer OSI and GPL compatible licenses. > http://www.luciani.org/geda/pcb/pcb-perl-library.html > > Would somebody be able to help me out, what should the name of the > footprint become and what scripts can I use to make the footprint and how > can I do this? > > Could somebody help me out by making an example for the 54-pin TSOP II > footprint? > > I got a lot more footprints to make, and I can use all the help, since > time is getting really sparse. > > OpenARM Single Board Computer Project: > https://secure.powercraft.nl/websvn/openarm/ > > Thanks in advance, > > Jelle de Jong The secure links are using a CAcert.org authority this is true open security. However not all web browsers have this authority in there lists. So you may have to add them. If you added the authority the secure pages should not show an security exception. Certificate Authority: http://www.cacert.org/index.php?id=3 OpenARM Single-board Computer: http://www.tuxcrafter.net/pages/projects.html#openarm-single-board-computer Cheers, Jelle de Jong ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: naming and creation of 54-pin TSOP II (400 mil) footprint, request for help
On Wed, 2009-05-13 at 14:45 +0200, Jelle de Jong wrote: > > Could somebody help me out by making an example for the 54-pin TSOP II > footprint? > I can not open your linked PDF documents, I get security warnings like this: >secure.powercraft.nl uses an invalid security certificate. >The certificate is not trusted because the issuer certificate is >unknown. >(Error code: sec_error_unknown_issuer) So I do not know how your desired footprint looks exactly, but my guess is that my SFG generator can do it -- it is licensed GPL. Of course finding the correct name is difficult, for me often this is more work than making the layout. But the name is indeed important to identify the footprint later. If you can not make the footprints yourself (maybe with my SFG) I can try to help you, if you send me the dimensions and the names of the footprint. Best reagrds Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: naming and creation of 54-pin TSOP II (400 mil) footprint, request for help
Hello everybody, I am trying to create a footprint with a correct name using the IPC-7351 Naming Convention for Standard SMT Land Patterns. But I am having some issues, i am using the below document to learn about the naming convention: https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/footprint-name-spec.pdf The footprint I want to make is a 54-pin TSOP II (400 mil), see: https://secure.powercraft.nl/svn/openarm/trunk/doc/SDRAM/MT48LC16M16A2P-7E/256MSDRAM.pdf # page 75, 54-Pin Plastic TSOP I tried to figure it out but I don't know what the lead span 1(L1) is? footprint: TSSOP-65P-640L1-54N 54-pin TSOP II (400 mil) TSSOP pin spacing, lead span 1, pin count P pin spacingdimension L1 lead span 1dimension N pin count count I also learned to create footprints with the following document: https://secure.powercraft.nl/svn/openarm/trunk/working/pcb/documents/land_patterns_20070818.pdf I had my ups and downs learning this and had some help trough IRC. However the creation of a 54-pin TSOP II seems to be able to automate using a script. I looked at the following, but it uses a license I disagree with and I can't figure out how it works, I prefer OSI and GPL compatible licenses. http://www.luciani.org/geda/pcb/pcb-perl-library.html Would somebody be able to help me out, what should the name of the footprint become and what scripts can I use to make the footprint and how can I do this? Could somebody help me out by making an example for the 54-pin TSOP II footprint? I got a lot more footprints to make, and I can use all the help, since time is getting really sparse. OpenARM Single Board Computer Project: https://secure.powercraft.nl/websvn/openarm/ Thanks in advance, Jelle de Jong ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Signal Source Setup for Electric Guitar?
Quick tip on your schematic: it's a good idea to offset 4 wire junctions (C1, R1, R2 & Q1b) so that they appear as two pairs of 3 wire junctions. That way even if the junction dot disappears in a .png or .pdf or whatever, it is obvious that the 4 wires are all joined and it's not just 2 wires crossing. The reason you're seeing such distortion with your first attempt is that the R1, R2 base bias potential divider feeds current into Q1b so this node sits at between about 0.55V and 0.7V above ground (let's say it's 0.6V and call this Q1vbe). Your 1V ac source (V2) is driving 1V pk, i.e. 2V pk - pk directly into C1. It is a pure (zero R) voltage source so R5 has no effect at all. The signal swing at Q1b is then offset by Q1vbe so whenever V2 drops below -0.6V, Q1 is cut off. If you look closely at what happens to Voutput when V2 swings through -0.6V, you'll also see that Voutput is increasingly distorted. This is a long way of saying that you are right: you need to use a much smaller input voltage swing. And yes, you can probably get away with using some sort of high impedance buffer in front of a sound card or even your on board sound but for it to be of much use, the buffer has to be very linear, have a suitably wide input voltage and frequency range and you'll need some sort of reasonably calibrated signal source with which to calibrate what you can see on any waveform display. If you don't have those things then you can't relate what you see on the display with what is actually happening at the point you are trying to measure. By the time you've sorted all that out you may find it easier and cheaper to get a reasonable quality PC scope card or even a 2nd hand scope. Don't forget that you need to allow for the effect of the connection you make into your circuit at the point you are trying to measure it too. Connecting a 1Meg // 50pF scope input across a 10Meg buffer input is not very helpful! Even x10 probes (notionally 10Meg//5pF) are not that much use. (You can reconcile the scope and simulator displays if you model the effect of the scope probe in the schematic too but that is getting a bit esoteric.) Whatever, Spice is a good tool for learning about electronics. With gEDA/gaf the tools and all the components are free and you can't even blow anything up! That said you do need to sanity check simulations for things like silly voltages or currents and power dissipations that would have destroyed real devices. : ) 2009/5/13 Gareth Edwards : > 2009/5/12 Joerg >> >> For guitar pickup modelling, you might like to do a bit of Googling on >> >> "spice model guitar pickup" or similar. >> > >> > Yes, that is a very interesting page. This is precisely the kind of >> > thing I'm interested in. I had no idea the capacitance of the cable >> > was so significant. >> > >> > Anyway it looks like their AC generator is using 2mV. So the 20mV >> > value I used to get a good output SIN looks closer to reality which >> > means my model is probably ok. >> > >> > I wish I had a real oscilloscope to find out what my guitar is really >> > putting out but xoscope doesn't seem to produce voltages (but I'm not >> > surprised since the sound card is probably oblivious to such things). >> > Maybe I'll have to get one of those PC oscilloscopes. >> > > > Unless you are building a pickup, don't get too hung up on modelling > it - it's a complex and changing impedance across frequency (stray and > interwinding capacitance, leakage inductance, DC resistance etc) and > the unit-to-unit variation in impedance and output voltage is large. > You've already spotted that cable capacitance plays a part - the tone > and volume controls loading the pickup are probably just as important. > > The trick is to use a high impedance amp front end that isolates the > pickup from the rest of the circuit (JFET or, my personal > preference/prejudice, a valve triode stage); then you can simplify the > pickup model to a simple generator without worrying too much. In my > amp work, I use a 100mV pk nominal signal - this is recommended by > Kevin O'Conner in his excellent Ultimate Tone series of books: > > http://www.londonpower.com/catalog/index.php?cPath=3 > > However, modelling can only get you in the ballpark of gain staging > and frequency response - eventually you have to evaluate with your > ears, not with SPICE! > >> >> If you want to display the waveforms or an FFT spectrum on the PC >> cheaply you could use an emitter follower as a buffer so the voltage >> gets transferred 1:1. Then a high input impedance is provided to the >> guitar even if you connect a sound card. > > Agreed, guitar into soundcard is sonic disappointment but JFET source > follower would be much better. Here's a good one (not mine, but > derived from a Win Hill circuit he posted on Usenet): > > http://www.ciphersbyritter.com/RADELECT/PREJFET/JFETPRE.HTM > > Cheers > Gareth > > > ___ > geda-user mailing list > geda-user@moria.seu
Re: gEDA-user: Signal Source Setup for Electric Guitar?
2009/5/12 Joerg > >> For guitar pickup modelling, you might like to do a bit of Googling on > >> "spice model guitar pickup" or similar. > > > > Yes, that is a very interesting page. This is precisely the kind of > > thing I'm interested in. I had no idea the capacitance of the cable > > was so significant. > > > > Anyway it looks like their AC generator is using 2mV. So the 20mV > > value I used to get a good output SIN looks closer to reality which > > means my model is probably ok. > > > > I wish I had a real oscilloscope to find out what my guitar is really > > putting out but xoscope doesn't seem to produce voltages (but I'm not > > surprised since the sound card is probably oblivious to such things). > > Maybe I'll have to get one of those PC oscilloscopes. > > Unless you are building a pickup, don't get too hung up on modelling it - it's a complex and changing impedance across frequency (stray and interwinding capacitance, leakage inductance, DC resistance etc) and the unit-to-unit variation in impedance and output voltage is large. You've already spotted that cable capacitance plays a part - the tone and volume controls loading the pickup are probably just as important. The trick is to use a high impedance amp front end that isolates the pickup from the rest of the circuit (JFET or, my personal preference/prejudice, a valve triode stage); then you can simplify the pickup model to a simple generator without worrying too much. In my amp work, I use a 100mV pk nominal signal - this is recommended by Kevin O'Conner in his excellent Ultimate Tone series of books: http://www.londonpower.com/catalog/index.php?cPath=3 However, modelling can only get you in the ballpark of gain staging and frequency response - eventually you have to evaluate with your ears, not with SPICE! > > If you want to display the waveforms or an FFT spectrum on the PC > cheaply you could use an emitter follower as a buffer so the voltage > gets transferred 1:1. Then a high input impedance is provided to the > guitar even if you connect a sound card. Agreed, guitar into soundcard is sonic disappointment but JFET source follower would be much better. Here's a good one (not mine, but derived from a Win Hill circuit he posted on Usenet): http://www.ciphersbyritter.com/RADELECT/PREJFET/JFETPRE.HTM Cheers Gareth ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
