gEDA-user: Multicomp Footprint SD/MMC slot

2010-03-17 Thread Michael Theurl
Hello List,

I'm new to pcb and looking for an footprint for Multicomp SD/MMC
Cardslot. First question is this the right place to ask for this ?

This is the exact part type: Multicomp SDAMB-01215BT00
Details link: http://octopart.com/sdamb-01215bt00-multicomp-5438442

hopefully someone out there had a nice footprint :)

thanxs a lot

michael





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Re: gEDA-user: Multicomp Footprint SD/MMC slot

2010-03-17 Thread Kai-Martin Knaak
On Wed, 17 Mar 2010 10:53:33 +0100, Michael Theurl wrote:

 Hello List,
 
 I'm new to pcb and looking for an footprint for Multicomp SD/MMC
 Cardslot. First question is this the right place to ask for this ?

Yes.


 This is the exact part type: Multicomp SDAMB-01215BT00 Details link:
 http://octopart.com/sdamb-01215bt00-multicomp-5438442
 
 hopefully someone out there had a nice footprint :)

http://gedasymbols.org is a place to search pcb footprints. 
Unfortunately, there is no connector named sdamp, yet. The data sheet 
does not give explicit recommendations on the land pattern. Good luck 
with rolling your own footprint! Please consider a contribution to 
gedasymbols when successful. 

---(kaimartin)---
-- 
Kai-Martin Knaak  tel: +49-511-762-2895
Universität Hannover, Inst. für Quantenoptik  fax: +49-511-762-2211 
Welfengarten 1, 30167 Hannover   http://www.iqo.uni-hannover.de
GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get



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Re: gEDA-user: On integrating simulator in gschem

2010-03-17 Thread John Griessen

Ivan Stankovic wrote:

On Mon, Mar 15, 2010 at 04:47:05PM -0500, John Griessen wrote:

Al wants more info than you get with SPICE netlist formats.  So Verilog-ams
level of function is possible.


While we're at it, was there a consensus on using verilog-ams as the format
of choice for Al's translation system?


Consensus?  Not yet.  Al does ask for two way translatable formats,
so including enough info to recreate a schematic is implied, but not
how exactly appearance matching it will be.  I'm thinking of graphic
elements as only the generic rectangular boxes at first, then by
way of text attributes, add more later.  the detailed info to
recreate schematic appearance is not needed for effective translation
purposes, just connectivity.  A reasonable goal is to capture
data that assists in putting back a schematic as it was, but not
doing the layout part of a schematic.  A big assist would be to
keep any unique identifiers from schematic symbols until a symbol
is changed for simulation purposes.  Then one could relate the
simulation netlist points to the original schematic points for cross
probing, even when the sim netlist is a subset or different in part
from the original.   Then you could do a process of back annotating,
deleting schematic symbols not found in the sim netlist, and saving
the modified schematic as an aid to simulation displaying.  With a small
amount of symbol layout time, your new schematic for cross-probing purpose
would be a one-to-one match with the simulation.

Al asked for a format for electric/electronic
netlists that can include any simulator's or schematic/netlist capture
program's circuit information.

John
--
Ecosensory   Austin TX


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Re: gEDA-user: if you people want to do it then put up the *cash*

2010-03-17 Thread Stephen Ecob
On Tue, Mar 16, 2010 at 6:34 AM, gene glick carzr...@optonline.net wrote:
 So now the question is Who else will pledge money?.

Sure, happy to contribute.

Stephen


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Re: gEDA-user: Toporouter update?

2010-03-17 Thread Anthony Blake
Hi,

On Wed, Mar 17, 2010 at 4:48 AM, Kai-Martin Knaak k...@familieknaak.de wrote:
 On Wed, 24 Feb 2010 09:10:29 -0500, Ethan Swint wrote:

 On 02/23/2010 06:46 PM, Anthony Blake wrote:
 Ok, then. Can you compile a list of tasks that need to be accomplished
 before the topo router is ready for general use? The smaler the
 individual tasks, the more likely they can be tackled by low time
 hackers like me...
 For sure. It would require some careful consideration though.. I'll get
 back to you within a week.
 Keep me in the loop, too.

 bump the topic up...

Since this thread started, I've discussed continuing work on the
toporouter with my Uni supervisors. They are OK with me taking time
off from my PhD if the GSoC thing goes ahead. I would prefer to do
most of the core work myself, rather than try and get others to
implement my 'half baked' and untested ideas.. The idea of getting
someone to implement something that I'm not even sure of myself
doesn't seem right..

As for smaller individual tasks.. I was thinking that an abstraction
layer for the autorouters might be a good idea. We now have 1.5
autorouters (very soon to be 2x complete autorouters), and an
abstraction layer would help future work built on top of the
autorouters, such as the auto-plow feature Harry Eaton mentioned,
seamlessly switch between the underlying autorouters.. An abstraction
layer would also be a good first step towards untangling the
toporouter from PCB, and making it more of a general open source
autorouter.

Another small task, which would *really* help me, would be an
automated testing framework for the autorouters. I would like to have
some tool which I could throw a directory of unrouted boards at, and
for each board it comes back with images of the output from the
toporouter  the autorouter, as well as performance results (wiring
length, runtime etc).

Someone also suggested switching out the absolute wiring length metric
with sum of each nets wiring length to MST length ratio.. That would
be a good small task to familiarize oneself with the toporouter 
autorouter code.. and the results would be very interesting if that
metric is also used as the cost function in the net ordering.

btw, if there are other little projects or features you would like to
add.. I'm happy to help in anyway I can, including being available on
IM/IRC to answer questions..

Also, can anyone think of a new name for the toporouter? There is
already a commercial tool called the 'toporouter', which I don't want
us to be confused with.

Regards,
Anthony


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Re: gEDA-user: Toporouter update?

2010-03-17 Thread Windell H. Oskay
 Also, can anyone think of a new name for the toporouter? There is
 already a commercial tool called the 'toporouter', which I don't want
 us to be confused with.


How about Awesomerouter?  :D



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Re: gEDA-user: Toporouter update?

2010-03-17 Thread Anthony Blake
On Thu, Mar 18, 2010 at 12:56 PM, Windell H. Oskay wind...@oskay.net wrote:
 Also, can anyone think of a new name for the toporouter? There is
 already a commercial tool called the 'toporouter', which I don't want
 us to be confused with.


 How about Awesomerouter?  :D

Haha nice..  I used to route boards by hand, but then I became
awesome instead. True story.


-- 
Anthony Blake


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Re: gEDA-user: Toporouter update?

2010-03-17 Thread Dave McGuire

On Mar 17, 2010, at 8:17 PM, Anthony Blake wrote:

Also, can anyone think of a new name for the toporouter? There is
already a commercial tool called the 'toporouter', which I don't  
want

us to be confused with.



How about Awesomerouter?  :D


Haha nice..  I used to route boards by hand, but then I became
awesome instead. True story.


  tea - keyboard

--
Dave McGuire
Port Charlotte, FL



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Re: gEDA-user: Toporouter update?

2010-03-17 Thread kai-martin knaak
Anthony Blake wrote:

 btw, if there are other little projects or features you would like to
 add..

Last time I checked, there were some real show-stoppers. E.g, the topo 
router would choke on preexisting tracks. I'd rather see these major issues 
resolved than divert energy toward added features. 

That said, I can surely come up with loads of feature requests. All kinds of 
suggestions to the router, layers exclusively for specific signals, 
customizable preferred directions, design rules that depend on the net, ... 
;-)

---(kaimartin)---
-- 
Kai-Martin Knaak
Öffentlicher PGP-Schlüssel:
http://pgp.mit.edu:11371/pks/lookup?op=getsearch=0x6C0B9F53



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Re: gEDA-user: Toporouter update?

2010-03-17 Thread Anthony Blake
On Thu, Mar 18, 2010 at 1:24 PM, kai-martin knaak k...@familieknaak.de wrote:
 Anthony Blake wrote:

 btw, if there are other little projects or features you would like to
 add..

 Last time I checked, there were some real show-stoppers. E.g, the topo
 router would choke on preexisting tracks. I'd rather see these major issues
 resolved than divert energy toward added features.

Absolutely agree with you about fixing those show-stoppers first.. the
problem is none of those issues (e.g., vias, existing geometry etc)
are small tasks suitable for people new to the toporouter to take on.
I would prefer to deal with those issues myself as part of the GSoC
this year.

 That said, I can surely come up with loads of feature requests. All kinds of
 suggestions to the router, layers exclusively for specific signals,
 customizable preferred directions, design rules that depend on the net, ...
 ;-)

Yup, those are the features I really want to get other people
implementing, so I can spend my time working on core features like
vias and existing traces..

Cheers,
-- 
Anthony Blake


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Re: gEDA-user: Toporouter update?

2010-03-17 Thread Ethan Swint

On 03/17/2010 08:24 PM, kai-martin knaak wrote:

Anthony Blake wrote:

   

btw, if there are other little projects or features you would like to
add..

  design rules that depend on the net, ...
   

+1, for my work.

-Ethan


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Re: gEDA-user: Toporouter update?

2010-03-17 Thread Windell H. Oskay

 Haha nice..  I used to route boards by hand, but then I became
 awesome instead. True story.

tea - keyboard

I suggest it because (1) it's awesome and (2) it's suggestive of
'autorouter.


  Back on topic now, we might get some good hints for future features from
Toporouter (the commercial autorouter product).  One of the ones that
they tout is understanding logical equivalence of certain pins.  You
could further imagine a very advanced version of this that could select
which slot of (say) a quad op-amp to use.

  But, let me also voice that I'm 100% behind getting the basics working
first.  I would *love* to be able to use this for even single sided
boards, today.  Adding in existing geometry is key.  Vias would be
great, too. :)

Honestly, optimization beyond what's already there would be great for a
future version, but I'm so craving just what I've seen so far.


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Re: gEDA-user: Toporouter update?

2010-03-17 Thread Anthony Blake
On Thu, Mar 18, 2010 at 1:37 PM, Windell H. Oskay wind...@oskay.net wrote:

 Haha nice..  I used to route boards by hand, but then I became
 awesome instead. True story.

    tea - keyboard

 I suggest it because (1) it's awesome and (2) it's suggestive of
 'autorouter.


  Back on topic now, we might get some good hints for future features from
 Toporouter (the commercial autorouter product).  One of the ones that
 they tout is understanding logical equivalence of certain pins.  You
 could further imagine a very advanced version of this that could select
 which slot of (say) a quad op-amp to use.

I've already had a first stab at implementing that, in an effort to
generate a good solution for DDR2-SDRAM - FPGA routing. It is very
hard to do well, as the problem just gets even more NP-complete =)
Since my first attempt year ago, I've learnt a few data
mining/machine learning tricks, and I'm feeling much more confident
about doing it *well* a second time around.

btw, those toporouter guys are rather misleading with their results..
they show off pictures of boards which have been fixed up afterwards..
e.g., 20 mins of toporouter time, and 40 mins of hand editing for
one of their boards.

And while I'm on the subject of comparing autorouters.. I was looking
at a Mentor license agreement the other day.. and I was shocked to see
that they prohibit you from using it to compare results with other
tools.. wtf..

 Honestly, optimization beyond what's already there would be great for a
 future version, but I'm so craving just what I've seen so far.

Thanks for your support!

-- 
Anthony Blake


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Re: gEDA-user: Toporouter update?

2010-03-17 Thread John Griessen

Anthony Blake wrote:

btw, those toporouter guys are rather misleading with their results..
they show off pictures of boards which have been fixed up afterwards..
e.g., 20 mins of toporouter time, and 40 mins of hand editing for
one of their boards.


That kind of partial route performance still enough to justify
plenty of tool spending until layout is
well automated.  As in, not needing more than a day after
netlist and footprints are verified to auto/hand route a
200 component board.



And while I'm on the subject of comparing autorouters.. I was looking
at a Mentor license agreement the other day.. and I was shocked to see
that they prohibit you from using it to compare results with other
tools.. wtf..


I guess the last thing the CAD companies want is a straight comparison.

Who's going to mentor you for GSOC purposes?

I hope Mentor or Cadence don't find out about you
and make you an offer you can't refuse.

John


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Re: gEDA-user: Toporouter update?

2010-03-17 Thread Anthony Blake

John Griessen wrote:

I guess the last thing the CAD companies want is a straight comparison.


We might be able to setup a system where people can anonymously post 
results generated with commercial tools, sort of like how deepchip.com 
works.



Who's going to mentor you for GSOC purposes?


Since Harry Eaton has never been shy with lots of really good criticism 
and comments regarding the toporouter (off list), I asked if he would be 
interested a few weeks ago..



I hope Mentor or Cadence don't find out about you
and make you an offer you can't refuse.


I doubt we are even on their radar =) In any case, I'm still a student 
for the next while, which isn't going to change..


Cheers,
Anthony



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