Re: gEDA-user: next PCB release - 1.99za vs 4.0
Okay, courtyard. Thanks for the nomenclature help :-) I'm just thinking of a couple of parts for a design that I'm working on where I need to make sure that I don't put any more parts in between areas of the footprint, but traces are ok because they're part of the board and won't interfere with the airspace. Is it possible that this (or the assembly layer concept mentioned by timecop) is already supported by PCB somehow, but I just don't know about it? I can't say I'd be surprised - I seem to learn something new every week or so... Thanks! -Jon On Sun, Sep 12, 2010 at 12:48 AM, DJ Delorie [1...@delorie.com wrote: I think the term you're looking for is a courtyard - the part of the PCB's airspace that's owned by the component. ___ geda-user mailing list [2]geda-u...@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Jonathon Schrader Bartlett, Illinois USA References 1. mailto:d...@delorie.com 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
PCB has nothing special for keep-outs of any sort. I just use the silkscreen to show where the part goes, including the courtyard. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB DRC crash with due to bloat / shrink breaking gemoetry
Peter Clifton wrote: Perhaps someone might like to take a stab at fixing this bug: https://sourceforge.net/tracker/index.php?func=detailaid=3064413group_id=73743atid=538811 I've triaged the cause of the crash, but don't really have the energy to start digging into the DRC engine's rules. I think the rule it is triggering on in this case is probably bogus, and the Shrink parameter should not apply to a pad solid inside a polygon. IMHO DRC should report an error if pad width is less than minimum trace width. Still, the test needs fixing, and there could be other legitimate cases where the geometry is broken just enough by the shrink / bloat parameter to cause problems. Why not just fix RectPoly this way: diff --git a/src/polygon.c b/src/polygon.c index 586e8cc..72e65d5 100644 --- a/src/polygon.c +++ b/src/polygon.c @@ -330,8 +330,8 @@ RectPoly (LocationType x1, LocationType x2, LocationType y1, LocationType y2) PLINE *contour = NULL; Vector v; - assert (x2 x1); - assert (y2 y1); + if (x1 = x2 || y1 = y2) +return NULL; v[0] = x1; v[1] = y1; if ((contour = poly_NewContour (v)) == NULL) Regards, Ineiev ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Hi all, -Original Message- From: geda-user-boun...@moria.seul.org [mailto:geda-user-boun...@moria.seul.org] On Behalf Of Bob Paddock Sent: Sunday, September 12, 2010 1:40 AM To: gEDA user mailing list Subject: Re: gEDA-user: next PCB release - 1.99za vs 4.0 In Protel there is a keep-out layer. A object, square, polygon etc, on that layer prevents traces from being run through that area, either manually or by the auto-router (which sucks so bad I never use it). Hmmm... Can we have multiple keep-outs for a single copper layer, e.g. digital keepout, analog keepout, HV keepout? That would be very useful! (Or maybe more appropriate to say keep-in.) Yes, the 'keep-out' should be per layer. In Protel it blocks all layers which is frequently what you do not want. Drawing a contain outline in copper, then remembering to delete it latter, can serve as pseudo keep-out/in. IMHO, we should be thinking about keepout as in: 1) traces keepout for copper layers (routing traces is out of bounds here), 2) placing parts op [top, bottom, buried components] in the keepout area for reasons of clashing with mounting holes, other parts courtyard (real estate), underlying stripline antennas, diff pair traces and other EMC reasons. Just my EUR 0.02 Kind regards, Bert Timmerman. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 12:24 AM, DJ Delorie [1...@delorie.com wrote: The top/bottom magic are needed to map footprints on import Don't over look buried components. Becoming more common. I think it would be better to just have layers, that you assign a function to, rather than have layers have magic properties. While allowing things like two Top Layers may sound silly, it is really not at the editing level. Different sections of the 'Top Layer' could be edited at different times, such as copypaste from older projects. Like layers in AutoCad or GIMP. References 1. mailto:d...@delorie.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 12:55 AM, DJ Delorie [1...@delorie.com wrote: I suspect that in the main GUI you'd get a simplified set of options, like add layers or remove layers to switch from, say, 2-layer PCBs to 4-layer PCBs, etc. In Protel there is such a dialog. Being able to move the Z-axsis of the layer is also needed in rare cases. The complete dialog shows the whole board stack-up. Copper thickness, pre-preg thickness (insulating glop between the conductive layers). Colors, impedance's etc. are assigned at this point as well. Also if this layer is considered a 'plane'. As for the color scheme, I suspect it will be plaid. With stripes. At work where we have a couple of different Protel Seats we can take the same board file, that contains the properties such as color, from one machine to an other. What looks good color wise on one machine, is completely unusable on an other machine due to differences in monitors, video cards etc. References 1. mailto:d...@delorie.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 1:40 AM, Jonathon Schrader jlsch...@jlschrad.net wrote: That is, a footprint (such as the battery mount mentioned previously) with a requirement not to place any parts between the tabs, but traces are fine? It would be good to be able to say place no component thicker than X in this area. Consider case clearances. Why didn't you tell me you drive a #6 bolt through the case to hold the board in place? It is not on any of the prints! :-( In the battery case here, traces on the top layer would not be allowed. Sliding the battery in and out could wear away the solder mask (which is not intended to by this type of isolator), exposing battery terminal to bare copper. Your point is still valid tho. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Hi all, -Original Message- From: geda-user-boun...@moria.seul.org [mailto:geda-user-boun...@moria.seul.org] On Behalf Of Bob Paddock Sent: Sunday, September 12, 2010 1:52 PM To: gEDA user mailing list Subject: Re: gEDA-user: next PCB release - 1.99za vs 4.0 On Sun, Sep 12, 2010 at 1:40 AM, Jonathon Schrader jlsch...@jlschrad.net wrote: That is, a footprint (such as the battery mount mentioned previously) with a requirement not to place any parts between the tabs, but traces are fine? It would be good to be able to say place no component thicker than X in this area. Consider case clearances. Why didn't you tell me you drive a #6 bolt through the case to hold the board in place? It is not on any of the prints! :-( Maybe you could add an attribute to an element defining the height. Something like: Attribute (element_height=, 5 mm) And write a plugin for parsing all elements and exporting this (and other) attribute as key-value pairs to whatever file (format) you can think of for further processing (mechanical DRC). Kind regards, Bert Timmerman ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Maybe you could add an attribute to an element defining the height. Something like: Attribute (element_height=, 5 mm) That would be required to do 3D also. There would also need to be a clearance space above the actual part thickness as well. Think about boards that are flexing/vibrating. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, 12 Sep 2010 14:49:02 +0900 timecop time...@gmail.com wrote: Most places handle this with the assembly layer. Of course, this wouldn't be part of DRC, but you'd have to be blind put stuff overlapping assembly layers and not see it right away. Imagine having to make a change to the layout that requires moving a bunch of components: you move parts around, put this transistor over there, move a capacitor over there, temporarily shift one IC underneath another IC, move a group of resistors off the board entirely... so on and on as you revise the layout. I can't count the number of times I've done stuff like this. When you finally get the layout back into a sane state, you pack it in for the day - except you don't notice that you forgot to move that one IC back out from under the other. Maybe you're tired, maybe the board just has a metric assload of parts, maybe you're pressed for time. Who knows? Everyone makes mistakes. -- There are some things in life worth obsessing over. Most things aren't, and when you learn that, life improves. http://starbase.globalpc.net/~ezekowitz Vanessa Ezekowitz vanessaezekow...@gmail.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 12:55:54AM -0400, DJ Delorie wrote: I suspect that in the main GUI you'd get a simplified set of options, like add layers or remove layers to switch from, say, 2-layer PCBs to 4-layer PCBs, etc. Outer special layers like silk and mask just exist, but you can enable/disable them. When you say just exist, you mean they are there by default on new boards, not that they're magic layers, right? So most users just see one copper drawing layer per physical copper layer, plus the usual top/bottom silk/mask/paste, plus an outline. But if you're in footprint mode you get top/inner/outer instead, plus the usual t/b s/m/p. Footprints are a special case of sub-assembly that never use specific layers, always layer classes, so they can map to your boards. There are some cases where you might want to have inner layers for footprint. In that case, the user would get the 'mapping' dialog when importing the component. (This mapping will need to be editable after the fact, of course). However, by /default/, we will only have top and bottom layers when creating a new footprint. Actually, we might need the mapping dialog in all cases, just for the case when the user wants to flip the component so the top is on bottom, bottom on top. Power users can change the association for a layer, so for example, one could create a footprint with copper on ALL layers, for a heatsink or physical strength. Or a both-sides silkscreen layer. Or two copper drawing layers per physical copper layer. I've used this before, to keep ground/power/signal colored differently. Gold finger plating might take advantage of this too, or multiple conductor types (metal plate over copper, conductive ink). Or two silkscreen layers for different ink colors. Well, a both-sides silkscreen layer makes little sense. If a user wanted that, he could duplicate the top silkscreen to get the bottom one. I don't think that would be common enough to require special code. I think that if we want components on multiple layers (or all layers), that should be a property of the component, not a layer group/physical layer thing. I don't know what people are going to be using it for, so it made sense to just let them do whatever they please, if they know what they're doing. Like I've said before, I want to make things easy for most users, and possible for the rest. As for the color scheme, I suspect it will be plaid. :) From a development stance, how do we want to structure layers and layer groups? It looks to me that we should have layer groups map to physical layers. Within each layer group, we can have as many drawing layers (of whatever types) as we want. The default setup would then look like (for a 4-layer board): GROUP: Top (TOP) LAYER: top-silk (SILK) LAYER: top-trace (COPPER) LAYER: top-paste (COPPER) GROUP: Inner 1 (INNER, z-index: 0) LAYER: inner1-trace (COPPER) GROUP: Inner 2 (INNER, z-index: 1) LAYER: inner2-trace (COPPER) GROUP: Bottom (BOTTOM) LAYER: bottom-silk(SILK) LAYER: bottom-trace (COPPER) LAYER: bottom-paste (COPPER) I think that all the UI suggestions voiced here will work well with this structure. Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
I think it would be better to just have layers, that you assign a function to, rather than have layers have magic properties. As flexible as I'd like to be, I think it's implied when designing circuit boards that there's going to be outside layers on them. From a practical viewpoint, designing normal footprints had better be *very* easy, and using them had better be *very* robust. In order to make the process somewhat intelligent, there needs to be at least *some* magic going on. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
When you say just exist, you mean they are there by default on new boards, not that they're magic layers, right? There by default on new boards - yes not magic - well, I still think intended purpose is something that PCB needs to know about, to do its job well. We can allow for exceptions by having an other type, but I think pcb really does want to know about magic layers like silkscreen, soldermask, etc. I don't mean that there has to be exactly two and they're treated differently, you can have three silkscreens all on inner layers if you want, but for efficiency and usefulness, a fast way to determine the type of a layer - conductor, silk, paste, mask, DRC, etc - is needed. To me, this means every layer gets a type and location value. There are some cases where you might want to have inner layers for footprint. In that case, the user would get the 'mapping' dialog when importing the component. (This mapping will need to be editable after the fact, of course). Right. Common is easy, uncommon is possible. However, by /default/, we will only have top and bottom layers when creating a new footprint. I can see default footprints using inner as well. Sometimes you'd want a part to have a keep-out for inner layers for EMI reasons. Actually, we might need the mapping dialog in all cases, just for the case when the user wants to flip the component so the top is on bottom, bottom on top. That happens so often that it's a special key in pcb already - 'b' Well, a both-sides silkscreen layer makes little sense. If a user wanted that, he could duplicate the top silkscreen to get the bottom one. I don't think that would be common enough to require special code. Outlines for bolts, cutouts, mechanical clamps, etc. But it's just a special case of support we need elsewhere - for example, a both-sides soldermask is very common, so much so that most FABs charge you less if both masks are the same. In that case, any customization to the mask would need to be on a both-sides layer. I think that if we want components on multiple layers (or all layers), that should be a property of the component, not a layer group/physical layer thing. What's the difference? It has to be implemented somehow. From a development stance, how do we want to structure layers and layer groups? It looks to me that we should have layer groups map to physical layers. Within each layer group, we can have as many drawing layers (of whatever types) as we want. I suspect the internal structure is... we have a list of layers. Anything that needs a layer group, really just wants a subset of layers, and we need to make sure that filtering layers is fast. I see no reason to have any more structure than that, it just complicates the design. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Vanessa Ezekowitz wrote: Maybe you're tired, maybe the board just has a metric assload of parts, maybe you're pressed for time. Who knows? +1 This is what DRC is meant for. A reliable check for stupid errors. I often feel like doh, how could I be so blind when DRC shows violations. Talking about DRCs: I really miss the ability to selectively let DRC ignore specific cases. Sometimes I just know better than dumb rules and need to override. This goes for rats, too. ---)kaiamrtin(--- -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=getsearch=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 12:53:57PM -0400, DJ Delorie wrote: Well, a both-sides silkscreen layer makes little sense. If a user wanted that, he could duplicate the top silkscreen to get the bottom one. I don't think that would be common enough to require special code. Outlines for bolts, cutouts, mechanical clamps, etc. But it's just a special case of support we need elsewhere - for example, a both-sides soldermask is very common, so much so that most FABs charge you less if both masks are the same. In that case, any customization to the mask would need to be on a both-sides layer. Alright, we'll allow a top and bottom layer group. I think that if we want components on multiple layers (or all layers), that should be a property of the component, not a layer group/physical layer thing. What's the difference? It has to be implemented somehow. Well, I'm trying to implement this, so somehow matters to me ;). From a development stance, how do we want to structure layers and layer groups? It looks to me that we should have layer groups map to physical layers. Within each layer group, we can have as many drawing layers (of whatever types) as we want. I suspect the internal structure is... we have a list of layers. Anything that needs a layer group, really just wants a subset of layers, and we need to make sure that filtering layers is fast. I see no reason to have any more structure than that, it just complicates the design. I disagree. If physical layers can contain multiple drawing layers (and they must, to keep silk and copper layers separate), it makes sense to have a rigid structure. Then we can display the layer selector in a tree- like display and it is clear to everyone what is what. See the current incarnation of my layer structures: http://download.wpsoftware.net/code/pcb/layer.h I'll copy out the important comment in that file: The layer structuring works as follows: 1. At the top level, each PCB has a layer stack. This is the ordered list of physical layers, plus one internal layer that is never saved out or edited. (For now, this will contain the ratsnest layer and nothing else.) 2. Each physical layer is called a layer group. It can contain indefinitely many drawing layers. Layer groups are one of TOP, BOTTOM, INNER or OUTER. There is at most one of each TOP, BOTTOM and OUTER layers. There can be any number of INNER layers, which will be ordered by their z-index. 3. Each drawing layer has a type associated with it - one of COPPER (conductive), SILK (non-conductive) or INTERNAL (not saved out: DRC highlights, etc, will be on such a layer). 4. TODO: There is no way to do keepouts. I have heard arguments for allowing global keepouts, per-layer keepouts, per-function-block keepouts, etc, and I don't know how it should be structured. Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Well, a both-sides silkscreen layer makes little sense. Actually it does make sense. Think about a transformer with through-hole pins. You want the top silk to show the courtyard, for clearances. You want the bottom silk to show the pin numbers/labels. -- http://blog.softwaresafety.net/ http://www.designer-iii.com/ http://www.wearablesmartsensors.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 12:38 PM, DJ Delorie d...@delorie.com wrote: I think it would be better to just have layers, that you assign a function to, rather than have layers have magic properties. As flexible as I'd like to be, I think it's implied when designing circuit boards that there's going to be outside layers on them. Flex Circuit in a Mobius configuration. I'd point you to a document by Davis that shows why you really would want to do such a thing, but Ales doesn't want those documents discussed here. From a practical viewpoint, designing normal footprints had better be *very* easy, and using them had better be *very* robust. In order to make the process somewhat intelligent, there needs to be at least *some* magic going on. It is all magic in the end, just have to have it on the correct end of the wand. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Alright, we'll allow a top and bottom layer group. With flex cable, top and bottom aren't limited to one layer each. I think that if we want components on multiple layers (or all layers), that should be a property of the component, not a layer group/physical layer thing. What's the difference? It has to be implemented somehow. Well, I'm trying to implement this, so somehow matters to me ;). Either we have one loop that filters layers by need, or a nested pair of loops. Same complexity. How do you handle layers that aren't assigned to physical layers? Like documentation layers? What about layers that apply to more than one physical layer, like outers or inners, or all? A tree structure ties you down to a specific physical structure, a list does not. What about buried vias? Do they go on a special layer that spans physical layers? I disagree. If physical layers can contain multiple drawing layers (and they must, to keep silk and copper layers separate), it makes sense to have a rigid structure. Then we can display the layer selector in a tree- like display and it is clear to everyone what is what. Internal structure and what we present to the user are two different problems. Yes, we need to keep track of the physical stackup. No, that does not need to dictate our internal structure. http://download.wpsoftware.net/code/pcb/layer.h I would add a LayerPos to each Layer, and store the Layers separately. 1. At the top level, each PCB has a layer stack. This is the ordered list of physical layers, plus one internal layer that is never saved out or edited. (For now, this will contain the ratsnest layer and nothing else.) Why one? Why not save it? We already save rats to file. What about layers that don't correspond to a physical layer? 3. Each drawing layer has a type associated with it - one of COPPER (conductive), SILK (non-conductive) or INTERNAL (not saved out: DRC highlights, etc, will be on such a layer). paste mask keepout fab drill notes Why not save DRC highlights? 4. TODO: There is no way to do keepouts. I have heard arguments for allowing global keepouts, per-layer keepouts, per-function-block keepouts, etc, and I don't know how it should be structured. keepouts are just another layer. Let DRC worry about what to do with it. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Flex Circuit in a Mobius configuration. They still have outsides, just not two of them. I'm going to go out on a limb and state that I refuse to support non-flat layers :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sep 12, 2010, at 10:35 AM, Bob Paddock wrote: Well, a both-sides silkscreen layer makes little sense. Actually it does make sense. Think about a transformer with through-hole pins. You want the top silk to show the courtyard, for clearances. You want the bottom silk to show the pin numbers/labels. +10. Obvious, important feature. Most of my boards have silkscreen on both sides. Every major fab shop supports it. We should too. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 01:56:43PM -0400, DJ Delorie wrote: Alright, we'll allow a top and bottom layer group. With flex cable, top and bottom aren't limited to one layer each. Aren't they? All layers except the top-most and bottom-most are considered inner layers. This whole top/inner/bottom thing is convienence for mapping footprints, and footprint mapping can be changed after-the-fact for weird use cases. What does it mean to have two top layers? I think that if we want components on multiple layers (or all layers), that should be a property of the component, not a layer group/physical layer thing. What's the difference? It has to be implemented somehow. Well, I'm trying to implement this, so somehow matters to me ;). Either we have one loop that filters layers by need, or a nested pair of loops. Same complexity. How do you handle layers that aren't assigned to physical layers? Like documentation layers? What about layers that apply to more than one physical layer, like outers or inners, or all? A tree structure ties you down to a specific physical structure, a list does not. What about buried vias? Do they go on a special layer that spans physical layers? It's not the same complexity. Filtering layers by need requires filtering through all the layers - a tree structure is much more efficient for accessing specific layers. Outers is a special case. Inners and multiple layers should be handled on a per-element basis; vias (or anything) can be assigned to more than one drawing layer, which in turn map to physical layers. What use case is there for layers that map to multiple physical layers? I did not consider layers that are not mapped to physical layers, except the rats layer. I think the best way to do this would be to have another class of layer group: Top, Bottom, Inner, Outers, None I disagree. If physical layers can contain multiple drawing layers (and they must, to keep silk and copper layers separate), it makes sense to have a rigid structure. Then we can display the layer selector in a tree- like display and it is clear to everyone what is what. Internal structure and what we present to the user are two different problems. Yes, we need to keep track of the physical stackup. No, that does not need to dictate our internal structure. They are different problems, but they are closely related. If our presentation layer is obscenely inefficient because our backend isn't appropriate, that is a problem. http://download.wpsoftware.net/code/pcb/layer.h I would add a LayerPos to each Layer, and store the Layers separately. 1. At the top level, each PCB has a layer stack. This is the ordered list of physical layers, plus one internal layer that is never saved out or edited. (For now, this will contain the ratsnest layer and nothing else.) Why one? Why not save it? We already save rats to file. What about layers that don't correspond to a physical layer? Why have a different number than one? I could not think of a good reason for this. 3. Each drawing layer has a type associated with it - one of COPPER (conductive), SILK (non-conductive) or INTERNAL (not saved out: DRC highlights, etc, will be on such a layer). paste mask keepout fab drill notes Noted. Why not save DRC highlights? You're right, we should be saving everything. 4. TODO: There is no way to do keepouts. I have heard arguments for allowing global keepouts, per-layer keepouts, per-function-block keepouts, etc, and I don't know how it should be structured. keepouts are just another layer. Let DRC worry about what to do with it. Ah, but what happens when you want a keepout on all layers? On one layer? For only HV lines? For footprints but not traces? All these have been mentioned on the list, and don't work well with keepouts are just another layer. Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 01:57:32PM -0400, DJ Delorie wrote: I meant ONE silk layer printed on BOTH sides of the pcb. Much like fabs often have an option for same mask both sides - one layer, used twice. Okay, I see what you're gettting at here with same layer, multiple physical layers. And I also see the benefit of having a many-to-many mapping between drawing layers and physical layers, rather than a tree structure. Now, how is the relationship between drawing layers and physical layers going to be shown to the user? I think dual-color traces would be nice. (That is, have the main color correspond to the physical layer, with a stripe on the left side (say) corresponding to the drawing layer.) What will the layer-selector look like? How will the user edit drawing layers? How about physical layers? I take it that only physical layers will have a stacking order, and drawing layers will be mapped to one or more of these? Also, will we require one of both top and bottom physical layers, to ease footprint mapping? What happens when these physical layers have no drawing layers mapped to them? If they have more than one drawing layer mapped to them? Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
With flex cable, top and bottom aren't limited to one layer each. Aren't they? No. Different areas of the cable may have extra layers or pcbs attached, changing the number of layers in that area. So one drawing layer might be top on the left side of the cable, but inner on the right side. What use case is there for layers that map to multiple physical layers? Single solder mask for both sides. Keep-outs. copper heatsinks. stripline. I did not consider layers that are not mapped to physical layers, except the rats layer. I think the best way to do this would be to have another class of layer group: Top, Bottom, Inner, Outers, None How does none map to your physical tree structure? Why one? Why not save it? We already save rats to file. What about layers that don't correspond to a physical layer? Why have a different number than one? I could not think of a good reason for this. autorouter might use it to store information. DRC might. I don't know what future uses, it just seems that one is a special case. Why not just have a save me flag, and let each layer decide if it needs to be saved or not? Paste buffers (cut-n-paste, not solder paste) might need multiple temporary layers. keepouts are just another layer. Let DRC worry about what to do with it. Ah, but what happens when you want a keepout on all layers? On one layer? For only HV lines? For footprints but not traces? All these have been mentioned on the list, and don't work well with keepouts are just another layer. I meant, if you have a keepout layer, it's just another layer. I didn't mean to imply that there weren't other ways to specify keepouts. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Now, how is the relationship between drawing layers and physical layers going to be shown to the user? I think dual-color traces would be nice. (That is, have the main color correspond to the physical layer, with a stripe on the left side (say) corresponding to the drawing layer.) What will the layer-selector look like? How will the user edit drawing layers? How about physical layers? I take it that only physical layers will have a stacking order, and drawing layers will be mapped to one or more of these? Also, will we require one of both top and bottom physical layers, to ease footprint mapping? What happens when these physical layers have no drawing layers mapped to them? If they have more than one drawing layer mapped to them? All good questions :-) The times I've done many-to-one mappings, I used shading for within the group. For example, the top layers were all red-ish and the bottom layers were all green-ish. Interesting thought - for buried vias, the top and bottom layers correspond to inner physical layers, yet they need to be treated differently as the annulus often needs to be bigger on layers where the trace connects. So an internal buried via element, before it's placed, is not like other elements... ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: file formats again (was: next PCB release - 1.99za vs 4.0)
At 04:46 PM 9/11/2010, you wrote: On Sat, Sep 11, 2010 at 09:28:16PM +0200, kai-martin knaak wrote: Peter Clifton wrote: Yes, indeed.. magic silk (and other) layers should probably go and die. Please do. My local list of warts and rooms for improvement contains many complaints about things that can't be done with silk. Worst of all: You can't selectively print top-silk and bottom-silk like the regular layers. Doing this will almost certainly require changes to the file format, which I am loath to do unless we switch entirely to a new, more flexible file format. Are there any concrete plans in that direction? Yeah, I think the consensus is to switch to a light weight XML format... ;^) Rick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
At 03:42 PM 9/10/2010, you wrote: On Sep 10, 2010, at 1:01 PM, DJ Delorie wrote: I figure we need each layer to specify: * type (copper, silk, mask, anti-copper, keepout, etc) There are no types, there are only properties. The conductors may not be copper. I've even worked with a board that had two different conductive materials on the same physical layer. Wouldn't that by definition then be two different physical layers, just like the solder mask and silk screen are two physical layers. The fact that they connect without vias doesn't mean to me they are the same physical layer. I've worked with boards that had buried resistors. The resistors were a layer of conductive material that had a controlled resistivity in contact with a copper layer. The resistors were considered a separate layer. The support layers are also not always FR4. The board I noted above had different numbers of layers in different places, and the support layers weren't all the same material and thickness. Sounds suspicious. Are you sure you aren't talking about an assembly with boards and a case? Bolts aren't normally considered vias. ;^) Rick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
At 03:45 PM 9/12/2010, you wrote: Interesting thought - for buried vias, the top and bottom layers correspond to inner physical layers, yet they need to be treated differently as the annulus often needs to be bigger on layers where the trace connects. So an internal buried via element, before it's placed, is not like other elements... Bigger??? Why do you need an annulus on an inner layer that doesn't connect to a trace? Rick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Bigger??? Why do you need an annulus on an inner layer that doesn't connect to a trace? Depending on the fab technique, you may need an annulus just to fill the gap between fr4 layers so that the electroplating is reliable. Either that, or you need to keep *other* copper far enough away that the prepreg can fill the gap. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 03:45:18PM -0400, DJ Delorie wrote: Interesting thought - for buried vias, the top and bottom layers correspond to inner physical layers, yet they need to be treated differently as the annulus often needs to be bigger on layers where the trace connects. So an internal buried via element, before it's placed, is not like other elements... Worse, vias may be connected to from more than two layers. I suspect that via will need to be a special element type, with two different footprints (a big one and little one). Should we require vias to only appear on consecutive layers? How do we handle two separate buried vias on top of each other? Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 03:40:24PM -0400, DJ Delorie wrote: With flex cable, top and bottom aren't limited to one layer each. Aren't they? No. Different areas of the cable may have extra layers or pcbs attached, changing the number of layers in that area. So one drawing layer might be top on the left side of the cable, but inner on the right side. Should we support this? What problems will we encounter if we allow layers to have arbitrary geometries? It looks to me that our top/inner/bottom distinctions will then only appear (a) in footprint mode and (b) when importing footprints. In all other cases, we simply have a layer stack. What use case is there for layers that map to multiple physical layers? Single solder mask for both sides. Keep-outs. copper heatsinks. stripline. All of these make sense for individual components, not for entire layers. Why one? Why not save it? We already save rats to file. What about layers that don't correspond to a physical layer? Why have a different number than one? I could not think of a good reason for this. autorouter might use it to store information. DRC might. I don't know what future uses, it just seems that one is a special case. Why not just have a save me flag, and let each layer decide if it needs to be saved or not? Paste buffers (cut-n-paste, not solder paste) might need multiple temporary layers. What are we talking about? I meant one layer-stack per board. Adding multiple virtual layers for whatever you can think of, is fine. keepouts are just another layer. Let DRC worry about what to do with it. Ah, but what happens when you want a keepout on all layers? On one layer? For only HV lines? For footprints but not traces? All these have been mentioned on the list, and don't work well with keepouts are just another layer. I meant, if you have a keepout layer, it's just another layer. I didn't mean to imply that there weren't other ways to specify keepouts. Fair enough. Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On 09/12/2010 03:17 PM, Windell H. Oskay wrote: On Sep 12, 2010, at 10:35 AM, Bob Paddock wrote: Well, a both-sides silkscreen layer makes little sense. Actually it does make sense. Think about a transformer with through-hole pins. You want the top silk to show the courtyard, for clearances. You want the bottom silk to show the pin numbers/labels. +10. Obvious, important feature. Most of my boards have silkscreen on both sides. Every major fab shop supports it. We should too. I think he is referring to a single silkscreen that printed on both top and bottom. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
At 04:06 PM 9/12/2010, you wrote: Bigger??? Why do you need an annulus on an inner layer that doesn't connect to a trace? Depending on the fab technique, you may need an annulus just to fill the gap between fr4 layers so that the electroplating is reliable. Either that, or you need to keep *other* copper far enough away that the prepreg can fill the gap. I guess I'm not following. Prepreg is the insulator used between copper laminate layers. I know of no requirement to keep copper away to allow the prepreg to exist or do its job. There are always some gaps or cracks in drilled hole walls even within insulation layers; the sides of the drill holes are never uniform in FR4 because the material is not uniform. These cracks fill up with electroplating quickly because they are very narrow and don't cause a problem. The only issue I am aware from these cracks being filled with plating is the need for keeping copper away from the holes to prevent shorts. That is normally dealt with by a hole to copper design rule. I have never been told by a board fab house that vias need to have an annulus on every layer to help with any problems. To allow for maximum density of routing, separate design rules are needed for hole to trace from via pad to trace and also different between outside layers and inner layers. I don't see that as a reason to use an annulus on each layer, to make the design rules work. Rick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 01:56:43PM -0400, DJ Delorie wrote:
http://download.wpsoftware.net/code/pcb/layer.h
I would add a LayerPos to each Layer, and store the Layers separately.
Okay, here is the structure: attached to the PCB is a physical layer stack.
This has a well-defined stacking order, knows about layer geometries(?) and
knows what the TOP and BOTTOM layers are at any given point on the board.
In footprint mode, this also includes a dedicated Top and Bottom layer.
Normal PCBs don't have a dedicated Top or Bottom layer, since as you said,
we may want irregularly shaped PCBs and have different layers be the Top
at different positions.
From there, any number of drawing layers exist. Each of these is linked to
a number of physical layers (may be zero).
Vias exist on the physical stack independent of the drawing layers. I don't
really like this but I think it makes sense. Similarly, footprints that are
imported should exist on the physical layer stack (since they have Top and
Bottom layers, and what does the top drawing layer mean?).
Here are the relevant structures:
/*** BEGIN ***/
/*!
* The type of drawing layer
*/
typedef enum
{
LYR_COPPER, /*! conductive */
LYR_SILK, /*! non-conductive */
LYR_KEEPOUT, /*! keepout layer */
LYR_VIRTUAL /*! internal (ie, ratsnest) */
}
LayerStyle;
/*!
* Qualitive position in the physical layer stack
*/
typedef enum
{
LYR_TOP, /*! top (component side) */
LYR_INNER,/*! middle */
LYR_BOTTOM/*! bottom (solder side) */
LYR_OUTER /*! both top and bottom */
}
LayerPos;
/*!
* Physical layer structure
*/
typedef struct
{
const char *name; /*! Layer name */
const char *color;/*! Layer color */
LayerPos position;/*! Top/Inner/Bottom (for footprints) */
unsigned z_index; /*! Stacking order (for PCBs and inner footprint
layers) */
void *geometry; /*! The shape of the layer */
}
PhysicalLayer;
/*!
* Drawing layer structure
* Drawing layers are contained within layer groups or physical layers,
* which in turn are placed on the layer stack.
*/
typedef struct
{
const char *name; /*! Layer name */
const char *color;/*! Layer color */
LayerStyle style; /*! Layer material */
PhysicalLayer **layer;/*! Associated physical layers */
unsigned n_physical_layers; /*! Number of physical layers */
int b_visible;/*! Visible in GUI */
int b_active; /*! Active layer in GUI */
int b_vacuum; /*! Hole mode in GUI */
int b_locked; /*! Un-editable in GUI */
}
DrawingLayer;
/*!
* Layer stack structure
*/
typedef struct
{
PhysicalLayer **layer;/*! List of layers */
unsigned n_layers;/*! Number of layers */
unsigned _allocated_layers; /*! private */
}
LayerStack;
/*** END ***/
Andrew
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Re: gEDA-user: PCB DRC crash with due to bloat / shrink breaking gemoetry
On Sun, 2010-09-12 at 06:57 +, ineiev wrote: Peter Clifton wrote: Perhaps someone might like to take a stab at fixing this bug: https://sourceforge.net/tracker/index.php?func=detailaid=3064413group_id=73743atid=538811 I've triaged the cause of the crash, but don't really have the energy to start digging into the DRC engine's rules. I think the rule it is triggering on in this case is probably bogus, and the Shrink parameter should not apply to a pad solid inside a polygon. IMHO DRC should report an error if pad width is less than minimum trace width. Still, the test needs fixing, and there could be other legitimate cases where the geometry is broken just enough by the shrink / bloat parameter to cause problems. Why not just fix RectPoly this way: That might just do it ;) I'm still not sure the DRC check is correct though. Also, we'll have to do a cursory scan to ensure that nothing is trying to call with x2 x1 or y2 y1. I realise there are/were asserts to this effect, but since hardly anyone build PCB with debugging asserts disabled, you can never be 100% sure! -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sep 12, 2010, at 12:29 PM, Andrew Poelstra [1]as...@sfu.ca wrote: On Sun, Sep 12, 2010 at 01:56:43PM -0400, DJ Delorie wrote: Alright, we'll allow a top and bottom layer group. With flex cable, top and bottom aren't limited to one layer each. Aren't they? All layers except the top-most and bottom-most are considered inner layers. This whole top/inner/bottom thing is convienence for mapping footprints, and footprint mapping can be changed after-the-fact for weird use cases. What does it mean to have two top layers? I think that if we want components on multiple layers (or all layers), that should be a property of the component, not a layer group/physical layer thing. What's the difference? It has to be implemented somehow. Well, I'm trying to implement this, so somehow matters to me ;). Either we have one loop that filters layers by need, or a nested pair of loops. Same complexity. How do you handle layers that aren't assigned to physical layers? Like documentation layers? What about layers that apply to more than one physical layer, like outers or inners, or all? A tree structure ties you down to a specific physical structure, a list does not. What about buried vias? Do they go on a special layer that spans physical layers? It's not the same complexity. Filtering layers by need requires filtering through all the layers - a tree structure is much more efficient for accessing specific layers. Outers is a special case. Inners and multiple layers should be handled on a per-element basis; vias (or anything) can be assigned to more than one drawing layer, which in turn map to physical layers. What use case is there for layers that map to multiple physical layers? I did not consider layers that are not mapped to physical layers, except the rats layer. I think the best way to do this would be to have another class of layer group: Top, Bottom, Inner, Outers, None None is a bad name, Documentation I disagree. If physical layers can contain multiple drawing layers (and they must, to keep silk and copper layers separate), it makes sense to have a rigid structure. Then we can display the layer selector in a tree- like display and it is clear to everyone what is what. Internal structure and what we present to the user are two different problems. Yes, we need to keep track of the physical stackup. No, that does not need to dictate our internal structure. They are different problems, but they are closely related. If our presentation layer is obscenely inefficient because our backend isn't appropriate, that is a problem. [2]http://download.wpsoftware.net/code/pcb/layer.h I would add a LayerPos to each Layer, and store the Layers separately. 1. At the top level, each PCB has a layer stack. This is the ordered list of physical layers, plus one internal layer that is never saved out or edited. (For now, this will contain the ratsnest layer and nothing else.) Why one? Why not save it? We already save rats to file. What about layers that don't correspond to a physical layer? Why have a different number than one? I could not think of a good reason for this. 3. Each drawing layer has a type associated with it - one of COPPER (conductive), SILK (non-conductive) or INTERNAL (not saved out: DRC highlights, etc, will be on such a layer). paste mask keepout fab drill notes Noted. Not all layers will be copper. Use conductor and the conductor then has the metal type attribute attached. As I think of silver ink flexes. Why not save DRC highlights? You're right, we should be saving everything. 4. TODO: There is no way to do keepouts. I have heard arguments for allowing global keepouts, per-layer keepouts, per-function-block keepouts, etc, and I don't know how it should be structured. keepouts are just another layer. Let DRC worry about what to do with it. Ah, but what happens when you want a keepout on all layers? On one layer? For only HV lines? For footprints but not traces? All these have been mentioned on the list, and don't work well with keepouts are just another layer. Layers with attributes here are a solution. The drc reads in the attribute and decide what to do. Oh this drc layer says Blah, another says foo. Andrew ___ geda-user mailing list [3]geda-u...@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:as...@sfu.ca 2. http://download.wpsoftware.net/code/pcb/layer.h 3. mailto:geda-user@moria.seul.org 4.
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sep 12, 2010, at 1:49 PM, Rick Collins wrote: At 03:42 PM 9/10/2010, you wrote: On Sep 10, 2010, at 1:01 PM, DJ Delorie wrote: I figure we need each layer to specify: * type (copper, silk, mask, anti-copper, keepout, etc) There are no types, there are only properties. The conductors may not be copper. I've even worked with a board that had two different conductive materials on the same physical layer. Wouldn't that by definition then be two different physical layers, just like the solder mask and silk screen are two physical layers. Perhaps. The fact that they connect without vias doesn't mean to me they are the same physical layer. Well, in this case they didn't connect without vias. The low current traces used a metal with low thermal conductivity, while the high current traces were copper. I've worked with boards that had buried resistors. The resistors were a layer of conductive material that had a controlled resistivity in contact with a copper layer. The resistors were considered a separate layer. The support layers are also not always FR4. The board I noted above had different numbers of layers in different places, and the support layers weren't all the same material and thickness. Sounds suspicious. Are you sure you aren't talking about an assembly with boards and a case? Bolts aren't normally considered vias. ;^) No, I'm talking about a narrow board with two rigid parts at the ends and a flexible part in the middle. The rigid parts had more layers: that's how they got to be rigid. It lived inside a cryostat, with circuitry that ran cold at one end, and circuitry that ran warm at the other. The point here is that the insulating planes are layers also: they need representation in the board description. They have their own shapes and material properties. And I think the only way to do blind/buried vias, buried components, and odd boards like this in a non-kludgy way is to treat the insulating planes as layers, each with its own geometry. Rick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: QFN soldering
does anyone have experience with this package? I want to know if they are hard to work with. The exposed pad underneath is a problem for hand soldering - but maybe could be left unsoldered for prototypes. Maybe just place some solder paste under there ? If the pcb pads are long enough, is it feasible to solder to the edge of the chip instead of getting it underneath the device? thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: QFN soldering
get a stencil, get solder paste, apply paste over stencil, heatgun, done. super simple. dont even bother doing it manually pin to pin, it probably wont work. On Mon, Sep 13, 2010 at 10:46 AM, gene glick carzr...@optonline.net wrote: does anyone have experience with this package? I want to know if they are hard to work with. The exposed pad underneath is a problem for hand soldering - but maybe could be left unsoldered for prototypes. Maybe just place some solder paste under there ? If the pcb pads are long enough, is it feasible to solder to the edge of the chip instead of getting it underneath the device? thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
And I think the only way to do ... in a non-kludgy way Yet another example of you automatically putting down any idea that isn't yours. Please stop that. Please consider the possibility that someone might come up with a better (or even equally good) idea than yours. Constructive criticism is welcome. Implied insults are not. is to treat the insulating planes as layers, each with its own geometry. So, you're saying drills and outlines should be stored on insulator drawing layers and the conductor drawing layers should only contain the actual conductor shapes? That means a simple two-layer board is going to give the user three drawing layers, minimum, not including the [expected] silk/mask/paste. I suspect asking about that third layer will become a FAQ if we don't get the GUI right. It also means that the boundary for an inner conductor layer may be one of two possibilities - PCB would then need to know not just the stackup, but the manufacturing sequence - which insulator carries the conductor film before etching/printing. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: QFN soldering
does anyone have experience with this package? Just did one today. I want to know if they are hard to work with. Harder than a QFP, but not impossible for home-fab. Pen flux the bottom of the chip before placing it on the paste - I wish I'd remember this more reliably :-) The exposed pad underneath is a problem for hand soldering - but maybe could be left unsoldered for prototypes. Depends on the chip. Some require an electrical connection, it may be the only ground for example. Maybe just place some solder paste under there ? If you have to solder an exposed pad manually, you have (IMHO) exactly two choices: 1. Put a via right under it, with a drill big enough to get your soldering iron in there to solder it from the back side. Keep in mind the big thermal sink this will be; your smallest iron tip might not be up to the task. Obviously, do this after soldering the edge pads :-) 2. Use a solder paste stencil of some sort and reflow it (heatgun, oven, hotplate). I make QFN stencils out of alumimum foil and UV film, I've done it with toner and thin brass too, and once with brass and a dremel drill press. But you can't just squeeze paste out of a tube and expect it to work - too little won't conduct and too much keeps the other pins from touching. Note that for home-etched boards, #1 requires a tiny wire, else you don't really have anything to solder to. Surface tension will keep the obvious idea from working :-) If the pcb pads are long enough, is it feasible to solder to the edge of the chip instead of getting it underneath the device? If you use #1 above, and the pads extend contiguously up the edges of the chip and not just on the bottom, yes. Use LOTS of pen flux and make sure the pcb's pads extend out far enough for a thermal connection with your iron. I've done this before, and the flux/iron trick can be used to fix reflow problems too. Note: some QFNs have copper on the side which is *not* contiguous with the pads on the bottom. The FT232RQ is such a chip. You have to reflow these, although the flux/iron trick can still repair them once there's *some* solder under the chip. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sep 12, 2010, at 7:53 PM, DJ Delorie wrote: And I think the only way to do ... in a non-kludgy way Yet another example of you automatically putting down any idea that isn't yours. Please stop that. Please consider the possibility that someone might come up with a better (or even equally good) idea than yours. Constructive criticism is welcome. Implied insults are not. is to treat the insulating planes as layers, each with its own geometry. So, you're saying drills and outlines should be stored on insulator drawing layers and the conductor drawing layers should only contain the actual conductor shapes? Typically, the user will draw composite objects that occupy multiple geometric layers. The GUI will have a library of common composite objects. Users are not going to want to work directly with geometric primitives unless it's necessary. But when it *is* necessary, the underlying data representation must allow the user to make direct contact with primitive geometry. That means a simple two-layer board is going to give the user three drawing layers, minimum, not including the [expected] silk/mask/paste. That's geometry. In engineering, never fight the mathematics or the physics. Instead, use them. I suspect asking about that third layer will become a FAQ if we don't get the GUI right. It's not so much the GUI, but the higher level description that matters. Users who don't bore down to the lowest levels need not see that detail. But if you don't have that solid low level foundation, you'll spend your life implementing kludges to get special behaviors. It also means that the boundary for an inner conductor layer may be one of two possibilities - PCB would then need to know not just the stackup, but the manufacturing sequence - which insulator carries the conductor film before etching/printing. In general it it needs that information. Consider a buried component: you need to know the stackup to know which insulating layer(s) host the cavity. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: QFN soldering
For quick breadboarding of an accelerometer I've deadbug soldered one successfully. Just superglued it upside down and soldered directly to the pads with very thin wire.. On Mon, Sep 13, 2010 at 12:04 PM, DJ Delorie d...@delorie.com wrote: does anyone have experience with this package? Just did one today. I want to know if they are hard to work with. Harder than a QFP, but not impossible for home-fab. Pen flux the bottom of the chip before placing it on the paste - I wish I'd remember this more reliably :-) The exposed pad underneath is a problem for hand soldering - but maybe could be left unsoldered for prototypes. Depends on the chip. Some require an electrical connection, it may be the only ground for example. Maybe just place some solder paste under there ? If you have to solder an exposed pad manually, you have (IMHO) exactly two choices: 1. Put a via right under it, with a drill big enough to get your soldering iron in there to solder it from the back side. Keep in mind the big thermal sink this will be; your smallest iron tip might not be up to the task. Obviously, do this after soldering the edge pads :-) 2. Use a solder paste stencil of some sort and reflow it (heatgun, oven, hotplate). I make QFN stencils out of alumimum foil and UV film, I've done it with toner and thin brass too, and once with brass and a dremel drill press. But you can't just squeeze paste out of a tube and expect it to work - too little won't conduct and too much keeps the other pins from touching. Note that for home-etched boards, #1 requires a tiny wire, else you don't really have anything to solder to. Surface tension will keep the obvious idea from working :-) If the pcb pads are long enough, is it feasible to solder to the edge of the chip instead of getting it underneath the device? If you use #1 above, and the pads extend contiguously up the edges of the chip and not just on the bottom, yes. Use LOTS of pen flux and make sure the pcb's pads extend out far enough for a thermal connection with your iron. I've done this before, and the flux/iron trick can be used to fix reflow problems too. Note: some QFNs have copper on the side which is *not* contiguous with the pads on the bottom. The FT232RQ is such a chip. You have to reflow these, although the flux/iron trick can still repair them once there's *some* solder under the chip. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Thinking about drills... If a cutout is a property of an insulating layer, the a drill through the whole PCB is really a composite of 2N+1 drills through N insulating layers and N+1 conductor layers. That seems kludgy to me. Drilling is a single operation, why do we have to represent it as multiple objects ? I'm thinking we structure the layers into composites. Each composite contains some conductor/insulator layers, including other composites, and an overall shape (outline, drills, slots). Thus, a drilling operation is stored as a single drill object in the composite's outline layer, and buried vias are just drills on a sub-composite. The heirarchy of composites represents the manufacturing process, so implicitely defines the possible blind and buried vias - you either drill through a composite or you don't. If a composite happens to represent copper layers 4 and 5 and the insulator between them, you get a buried via. If the composite is layers 0 and 1, you get a blind via. If it's the top-level composite, you get a regular via. Etc. This also solves the which insulator is the copper on problem, because it's on the ones it's in the composite with. They'd all have the same shape anyway, you just limit the conductor layers to the shape of the composite. Within each composite, we'd still need to figure out how to store the physical stackup (order, groups, etc) and do the usual top/bottom/drc stuff. I'm not sure how to reflect this though: consider two flex pcbs connecting the tops/bottoms of two rigid PCBs, one with two layers and one with four: - - = - = - Now what about two flex pcbs that leave a rigid pcb on the same side, one on the top and one on the bottom, yet lead to two unrelated rigid pcbs? Do those other pcbs need to share layer groups, or need to be separate? Where the two flex pcbs overlap on the one rigid pcb they're part of the same composite, but where they leave that pcb they become two separate things. Or does PCB need to know that a pcb assembly may be made of multiple separate PCBs assembled later? I.e. spit out separate gerber sets for the flex pcbs and the three rigid pcbs? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 11:09:25PM -0400, DJ Delorie wrote: Thinking about drills... If a cutout is a property of an insulating layer, the a drill through the whole PCB is really a composite of 2N+1 drills through N insulating layers and N+1 conductor layers. That seems kludgy to me. Drilling is a single operation, why do we have to represent it as multiple objects ? I'm thinking we structure the layers into composites. Each composite contains some conductor/insulator layers, including other composites, and an overall shape (outline, drills, slots). This is mathematically sound... Thus, a drilling operation is stored as a single drill object in the composite's outline layer, and buried vias are just drills on a sub-composite. ...but your number of sub-composites grows exponentially. In theory, whatever the lowest-level composite is, your sub-composite set is the power set of that! The heirarchy of composites represents the manufacturing process, so implicitely defines the possible blind and buried vias - you either drill through a composite or you don't. If a composite happens to represent copper layers 4 and 5 and the insulator between them, you get a buried via. If the composite is layers 0 and 1, you get a blind via. If it's the top-level composite, you get a regular via. Etc. This also solves the which insulator is the copper on problem, because it's on the ones it's in the composite with. They'd all have the same shape anyway, you just limit the conductor layers to the shape of the composite. Well, no, now you've got the which composite is the copper in problem ;) Within each composite, we'd still need to figure out how to store the physical stackup (order, groups, etc) and do the usual top/bottom/drc stuff. I'm not sure how to reflect this though: consider two flex pcbs connecting the tops/bottoms of two rigid PCBs, one with two layers and one with four: - - = - = - Exactly. I really like where you're going with this - it looks like it could be elegant and very expressive. How to get there, though, I don't know. Maybe sleeping on it will help. Now what about two flex pcbs that leave a rigid pcb on the same side, one on the top and one on the bottom, yet lead to two unrelated rigid pcbs? Do those other pcbs need to share layer groups, or need to be separate? Where the two flex pcbs overlap on the one rigid pcb they're part of the same composite, but where they leave that pcb they become two separate things. Or does PCB need to know that a pcb assembly may be made of multiple separate PCBs assembled later? I.e. spit out separate gerber sets for the flex pcbs and the three rigid pcbs? In theory, PCB never needs to know how an entire pcb assembly is composed. That's the fab's job. IME most multi-PCB projects involve socket/plug combinations so that the different components can plug into each other and you don't have to worry about shared traces or layers. To some extent, we can allow this sort of thing by giving complete freedom to the geometry of the composite. So you could have boards that look like (from the side, I can't ASCII anything better): === === == if you really wanted. I've contemplated all sorts of silly artistic designs, such as mounting ICs atop pyramids and running traces through tunnels, etc, and if I could find such a design tool I might even contemplate building such a thing. I'm sure there are practical uses, too. And if you combine this functionality with a 3D view, pcb would truly be a killer app. But I can dream... Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
...but your number of sub-composites grows exponentially. In theory, whatever the lowest-level composite is, your sub-composite set is the power set of that! No, because fabs can't drill that way. You can't have a copper layer that's part of two separate sub-assemblies before those sub-assemblies are assembled to each other. Let's say we're doing the top half of an 8-layer board... copper - 1 top fr4 = 2 copper - 3 fr4 = 4 copper - 5 fr4 = 6 copper - 7 fr4 = 8 center Now, depending on how the fab makes it, determines what combinations of buried vias are possible. For example, if the fab makes two two-sided boards and glues them to a core, you get this: copper - 1 -- fr4 = 2 ][ copper - 3 -- fr4 = 4 copper - 5 -- fr4 = 6 ][ copper - 7 -- fr4 = 8 Thus, you can via from 1-3 or from 5-7, but not 3-5 because you never have 3/4/5 as a separate drillable unit. Thus, the composite is: ((123) 4 (567) 8 ...) Blind and micro vias are just special cases of this. You'd sub-composite the top copper/fr4 so you could list drills there: (((12) 3) 4 (567) 8 ...) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: QFN soldering
There are a number of different QFN package styles. Some have pads only on the bottom, others have pads that wrap around the up the side a bit. These tend to be easier to hand solder since you have a place to contact with the solder iron. Sounds like yours don't have that plus they have a thermal pad on the bottom. If the thermal pad isn't required for an electrical connection, and you don't need to use the full power capability of the package, you can likely live without soldering the thermal pad for a prototype. But check the data sheet carefully. Sometimes they require you to provide an electrical connection. Is this a power supply devices? Those are the ones that are most demanding I've found. The assembly houses use a hot air tool. It heats up the entire part and everything in the immediate area such as the board. The solder flows, the part settles down onto the board and all is good. Rick At 09:46 PM 9/12/2010, you wrote: does anyone have experience with this package? I want to know if they are hard to work with. The exposed pad underneath is a problem for hand soldering - but maybe could be left unsoldered for prototypes. Maybe just place some solder paste under there ? If the pcb pads are long enough, is it feasible to solder to the edge of the chip instead of getting it underneath the device? thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
Hi all, We use Cadence Allegro at work, and how they implement keepouts may be interesting. There are several non-copper layers that are used to control the keep outs and keep-in. In this tool the keep in / keep out is related to how courtyards are defined. Each library symbol (called a package in allegro) has a layer called place-boundary upon which a shape is drawn which defines it's courtyard. This can be a simple rectangle for an SMD component, or something more complex. This shape can have a height property. This defines a 3-D No fly zone for other components. You can have multiple shapes on this layer for one library part and they can have different height properties, including a clearance area above the board (I believe specified by a negative height). This allows constructs like you can place a component here, as long as it is less than this tall. This is useful for odd components like a heatsink that overhangs part of the board. When placing components on the board, the shapes on this place-boundary layer (there is one for top and one for bottom) can not overlap. they can be adjacent but not overlap, unless the height of one of them fits under the minimum height of the other (the heatsink example above). This works well, but there is a downside in that the package to package spacing is defined in the library by the size of this shape on each part, but when you go to a high volume assembly house, they often have different rules as to how close some components can be. If their value is different than your . assumption, changing this value is not just a simple DRC rule change in the board, it has to be changed in the library. To do keepin / keep out there are special board layers called package keep in and package keep out (there are several of these layers, one for top, one for bottom, and one for all layers, you could generalize this to one per each layer if need be). On these layers you place outlines of the assorted regions you are trying to define. If any packages courtyard is even partially outside a package keepin layer, this is a DRC violation. If any packages courtyard is even partially inside a package keepout, this is also a violation. You can have multiple shapes on a package keep out layer, so there can be multiple regions you wish to keep parts out of. I believe you can also define a height property to these regions as well, so that you can have an area of the board for only components less tall than X, say under a shield can or under a heatsink. There are also analogous layers called route keepin and route keepout, which define where traces go and can not go. You can route a trace through a package keepout, under the assumption that the trace height wont cause a mechanical clearance issue. But a route keep out will prevent any traces from going through that area (good for an area where you remove soldermask for some reason). All traces (routes in allegro terminology) must be inside the route keepin. One way to use these is at the board edge. You may have an outline layer that defines the size of the board, but may wish a route-keepin shape that is say 20 mils inside the outline, to keep the traces away from the board edge, and a package keepin shape that is say 40 mils smaller, to keep components in from the edge. Incidentally the height property of the courtyard is often used by 3rd party 3D board rendering tools when a true 3d model of the component does not exist, the courtyard outline is extended upwards by the height property for a quick approximation of the 3D component. Regards, --Neil. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010 at 11:49:33PM -0400, DJ Delorie wrote: ...but your number of sub-composites grows exponentially. In theory, whatever the lowest-level composite is, your sub-composite set is the power set of that! No, because fabs can't drill that way. You can't have a copper layer that's part of two separate sub-assemblies before those sub-assemblies are assembled to each other. Let's say we're doing the top half of an 8-layer board... copper - 1 top fr4 = 2 copper - 3 fr4 = 4 copper - 5 fr4 = 6 copper - 7 fr4 = 8 center Now, depending on how the fab makes it, determines what combinations of buried vias are possible. For example, if the fab makes two two-sided boards and glues them to a core, you get this: copper - 1 -- fr4 = 2 ][ copper - 3 -- fr4 = 4 copper - 5 -- fr4 = 6 ][ copper - 7 -- fr4 = 8 Thus, you can via from 1-3 or from 5-7, but not 3-5 because you never have 3/4/5 as a separate drillable unit. Thus, the composite is: ((123) 4 (567) 8 ...) Blind and micro vias are just special cases of this. You'd sub-composite the top copper/fr4 so you could list drills there: (((12) 3) 4 (567) 8 ...) Alright, you've convinced me we won't encounter computationally infeasible problems ;) but we've still got a user-interface problem. Specifically, I expect most users don't care -at all- about this stuff, and if they do care, they don't know (yet) what the fab can/will do. Maybe they'll just fab whatever's cheapest and don't care about the material or thickness of the layers. Maybe they don't need blind or buried layers. Maybe they're just organizing protoboards or drawing road maps or something. So what happens for those users? Andrew ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
but we've still got a user-interface problem. We're used to that. So what happens for those users? They get exactly one composite, which ends up acting just like what we have today - one outline, one set of drills, all copper/insulator are on the one plain-built board. In our previous example, you'd get (1 2 3 4 5 6 7 8 ...) The pcb is a composite anyway, this just means that pcb's internal PCB global variable is a composite. Paste buffers, footprints, etc - those are separate composites. Of course, no reason why PCB couldn't keep multiple top-level composites in memory - we already do, with paste buffers - but editing them is the tricky part. Gschem avoids the problem by only editing one schematic at a time in a common window. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
