Re: gEDA-user: gnetlist -g drc2 and pintype
kai-martin knaak wrote: Karl Hammar wrote: Running gnetlist -g drc2 on a schematic I get: input/output -- pwr input and output are meant to refer to signals. The DRC assumes that signals should never be connected to power lines. With analog circuits there is no strict dividing line between signal and power. So DRC should be taken with a large grain of salt on these circuits. From what I know, it's a bad idea to leave logic inputs floating, so on TTL/CMOS gates, one will tie them to GND if not used. GND is a power line, isn't it? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist -g drc2 and pintype
Tying a digital input directly to a power rail is a bit like doing a crossword puzzle in ink. You need a lot of confidence to do that in a real design. I typically use a resistor to pull them up or down. That can always be hacked, power connections can be hard to access to modify them. Rick At 09:22 AM 9/27/2010, you wrote: kai-martin knaak wrote: Karl Hammar wrote: Running gnetlist -g drc2 on a schematic I get: input/output -- pwr input and output are meant to refer to signals. The DRC assumes that signals should never be connected to power lines. With analog circuits there is no strict dividing line between signal and power. So DRC should be taken with a large grain of salt on these circuits. From what I know, it's a bad idea to leave logic inputs floating, so on TTL/CMOS gates, one will tie them to GND if not used. GND is a power line, isn't it? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new footprint guidelines
I am curious about the reasoning for picking values of design rules. I have not found the assembly houses to be very useful for this sort of info. They seem to be willing to work with whatever they are sent and will only give feedback when something causes real trouble for them. At 12:51 PM 9/24/2010, you wrote: Yes, the old library parts are pre-hires and the pads can be way off and should be fixed. Thanks! If we're hand-coding footprints, we could use 0.5mm instead of 1965 and preserve the *meaning* of the units. We lose some compatibility with older PCBs, but if the purpose is to update the current distribution that shouldn't be a problem. We should probably go with build-time generated footprint files, rather than continue to use the m4 runtime generation. That allows us to use more than just m4, too. Makefile rules for standard %.whatever to %.fp conversions... My general rules: Mask should be 3 mil away from copper, and slivers should be at least 6 mil wide. That means, if there's less than 12 mil between pads you go with a gang-opening. Where did you get these numbers? Did a manufacturer give this as their capability limit? Silk should not overlap the *mask opening* and should be 3 mil away at least. 5 mil min silk lines. Same here, who's rules are these? Origin and license should be stored in element attributes, not file comments, so they're copied into schematics. IPC has developed a set of rules for designing footprints to match parts of all sorts and has even provided a library of data for this. They provide three standard sets, Most, Nominal, Least which differ in the amount of land protrusion. Armin's footprint is likely a Most catagory footprint from his description. IPC-7351 seems to be very widely adopted and would be a great starting point for any footprint library. It would probably be a good idea to have more than one design for each footprint; one for reflow'd boards and one with longer pads for hand soldering. All QFN parts should have some visual aids to centering :-) On my last board, I added four diagonal lines on the silk layer to align each corner (like a big X), that worked out well. Refdes should be properly placed and sized but I'm not sure what's best. For example, on every single RESC1608N part I place I have to make the refdes smaller and move it off the pads. Getting size right is far more important than position; it's easy (and often needed anyway) to move things around in only-text mode. I don't bother with putting the refdes in any particular location for a library part. The times a default location would work out is so seldom, that it just isn't worth the effort. I put the refdes in the middle of the library part and move it to suit the design. Rick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new footprint guidelines
Just 10 minutes ago I had my 1st talk with my first assembly house. Guess what! I'm asked to provide rotation data. In the other mail I'm currently editing, I'm trying to provide definitions on where X- and Y-axis is on a part, including where X+ is on mechanically doubly symmetrical polar parts etc. As of now, I'll probably have to check/provide every angle by hand, but for future footprints, the definitions have to be absolutely clear. If there are contradictory standards, we will have to opt for one. As Rick said, they are able to adapt to any coordinate system, but at least the designer must know, what he means himself ;-) Regards, Armin Rick Collins wrote: I am curious about the reasoning for picking values of design rules. I have not found the assembly houses to be very useful for this sort of info. They seem to be willing to work with whatever they are sent and will only give feedback when something causes real trouble for them. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new footprint guidelines
I had to go through all this some time ago and recently I wanted to iron out all the difficulties so that the assembly house could use my XYRS file (location and rotation data) directly without alteration. That ended up being a fool's errand, but I did learn a few things. IPC has a standard for this which everyone seems to use. For two pin symmetrical parts, pin one is to the left. For IC type parts, pin one is in the upper left quadrant for parts with pin one in a corner or for parts where pin one is in the center of a side pin one is on the upper most side. This is the zero degree rotation point for the part. All rotations are counter-clockwise from this position. Then comes the really tricky part. For parts on the bottom side, the general rule (not in the IPC standard) is to either view the parts from the bottom with the board mirrored about the Y axis with the same pin one orientation (upper left in the mirrored image) and rotation counter-clockwise, or to view the bottom from the top with rotation clockwise ( with the footprint mirrored about the Y axis so pin one is on the right, in the upper right corner or top) giving the same results. All X,Y positions are with respect to the centroid of the part. I would expect the software can do all of this, but you need to layout your footprint with this in mind. In Free PCB, they use a centroid vector to specify the location of the centroid of the part and the angle of the zero degree rotational position. Not sure how this is done in gEDA. As you say, you can deviate from this and the board house will likely still give you correct boards as long as you are consistent. But even though the parts on my board were clearly labeled with pin 1, a board house assembled all of my prototypes with the chips reversed once. Now I am much more cautious about the XYRS file, almost paranoid... 8-S Rick At 10:42 AM 9/27/2010, you wrote: Just 10 minutes ago I had my 1st talk with my first assembly house. Guess what! I'm asked to provide rotation data. In the other mail I'm currently editing, I'm trying to provide definitions on where X- and Y-axis is on a part, including where X+ is on mechanically doubly symmetrical polar parts etc. As of now, I'll probably have to check/provide every angle by hand, but for future footprints, the definitions have to be absolutely clear. If there are contradictory standards, we will have to opt for one. As Rick said, they are able to adapt to any coordinate system, but at least the designer must know, what he means himself ;-) Regards, Armin Rick Collins wrote: I am curious about the reasoning for picking values of design rules. I have not found the assembly houses to be very useful for this sort of info. They seem to be willing to work with whatever they are sent and will only give feedback when something causes real trouble for them. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new footprint guidelines
Mask should be 3 mil away from copper, and slivers should be at least 6 mil wide. That means, if there's less than 12 mil between pads you go with a gang-opening. Where did you get these numbers? Did a manufacturer give this as their capability limit? Yes. I've found this to be the usual rules for prototype services. I suspect you can pay more for better accuracy :-) Silk should not overlap the *mask opening* and should be 3 mil away at least. 5 mil min silk lines. Same here, who's rules are these? Many fabs automatically delete silk that overlaps mask holes. The 3 mil rule comes from the mask rules. Fabs I've talked to say the mask placement is +- 3 mil. Origin and license should be stored in element attributes, not file comments, so they're copied into schematics. IPC has developed a set of rules for designing footprints to match parts of all sorts and has even provided a library of data for this. They provide three standard sets, Most, Nominal, Least which differ in the amount of land protrusion. Armin's footprint is likely a Most catagory footprint from his description. IPC-7351 seems to be very widely adopted and would be a great starting point for any footprint library. We have IPC footprints in the ~geda library. Not all, but some. I don't bother with putting the refdes in any particular location for a library part. The times a default location would work out is so seldom, that it just isn't worth the effort. I put the refdes in the middle of the library part and move it to suit the design. Agreed. I think middle of the part, despite being bad for the *final* board, is the best starting point. *Size* of the refdes should be considered when making a footprint though. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new footprint guidelines
On Mon, Sep 27, 2010 at 9:56 AM, Rick Collins gnuarm.2...@arius.com wrote: They [Assembly houses] seem to be willing to work with whatever they are sent and will only give feedback when something causes real trouble for them. You have to ask, unfortunately. When you send a new project in to a house, ask to talk to the people on the line, about what would make the design better. Don't let the sales department give the no problem answer based on the customer is always right idea. Talk to the people doing the work. If you are making only a few boards the unspoken problems don't really mater that much, but if you are making any kind of quantity of boards it could mater a lot in the bottom line pricing you'd get from the assembly house. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb minor release, C++ and Gtk cleanup
Andrew Poelstra wrote: 2. We need to have a minor release (1.99za?) to get all the little crap out of the pipeline before we break everything. And please, please apply as much of Peter Cliftons pcb version as possible before you start. It is not only about the openGL and 3D hack for visuals, but a huge bag of little useful improvements. Let's not loose them on the way. ---)kaiamrtin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Zero length pins
Folks, In response to a question on the chat, I've been playing around with pins of zero graphical length. It turns out that these work quite well. Why would anyone want such? Well, they allow you to put a connection point on any graphic, not just the end of a line of a particular style. The only blemish is that you apparently can't create such a thing in the gschem GUI, so you have to go outside. Appending the following line to your .sym file will get you started: P 100 100 100 100 1 0 0 Once you have this object, you can move it, copy it, attach attributes to it, etc. in the gschem GUI. Unattached, it looks like a little red flag, while with a net attached it disappears. Gnetlist has no trouble treating it as a pin. Just another example of gEDA avoiding unnecessary assumptions about the process (except in the GUI), and thereby gaining unusual flexibility. Genius. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new footprint guidelines
I've done that. I go to the assembly house to test my boards so they can be repaired before I accept delivery and talk with them all the time. The only complaint they have is a connector that hangs over the edge of the board which I can't do anything about unfortunately, it is due to an old mistake by my customer which would require obsoleting lots of equipment in the field. Like I said, if it doesn't cause them any real problems, they don't worry about it. Rick At 12:52 PM 9/27/2010, you wrote: On Mon, Sep 27, 2010 at 9:56 AM, Rick Collins gnuarm.2...@arius.com wrote: They [Assembly houses] seem to be willing to work with whatever they are sent and will only give feedback when something causes real trouble for them. You have to ask, unfortunately. When you send a new project in to a house, ask to talk to the people on the line, about what would make the design better. Don't let the sales department give the no problem answer based on the customer is always right idea. Talk to the people doing the work. If you are making only a few boards the unspoken problems don't really mater that much, but if you are making any kind of quantity of boards it could mater a lot in the bottom line pricing you'd get from the assembly house. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb minor release, C++ and Gtk cleanup
Kai-Martin Knaak wrote: And please, please apply as much of Peter Cliftons pcb version as possible before you start. It is not only about the openGL and 3D hack for visuals, but a huge bag of little useful improvements. Let's not loose them on the way. I hope this won't break the Lesstif HID. Peter's branch is still several times slower than elder GUIs on all my machines, which makes the GL-based renderer actually unusable for me. Kind regards, Ineiev ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist -g drc2 and pintype
Hi Karl, El dom, 26-09-2010 a las 11:33 +0200, Karl Hammar escribió: [snip] Checking pins without the 'pintype' attribute... Checking type of pins connected to a net... WARNING: Pin(s) with pintype 'output': U2:9 are connected by net 'unnamed_net61' to pin(s) with pintype 'input/output': U1:30 WARNING: Pin(s) with pintype 'output': U2:7 are connected by net 'unnamed_net55' to pin(s) with pintype 'input/output': X1:9 WARNING: Pin(s) with pintype 'output': U3:3 are connected by net 'Vcc' to pin(s) with pintype 'input/output': Q8:A1 Q7:A1 Q6:A1 Q5:A1 ERROR: Pin(s) with pintype 'output': U3:3 are connected by net 'Vcc' to pin(s) with pintype 'power': U2:16 U1:6 U1:4 U1:18 WARNING: Pin(s) with pintype 'input/output': Q8:A1 Q7:A1 Q6:A1 Q5:A1 are connected by net 'Vcc' to pin(s) with pintype 'power': U2:16 U1:6 U1:4 U1:18 Checking unconnected pins... ERROR: Unconnected pin U2:11 [snip] Type of pins Why does it warn about output -- input/output input/output -- pwr Because drc2 can't check if an input/output pin is really an input or an output (or even both, depending on the design). It gives you warnings (not errors) about this, so you can check by your own. It tries to catch errors like connecting an output to another output, or an output to a power rail. Drc2 is not perfect, and has limitations, but it's all we have by now. The ERROR is a lm7805's output (U3:3) connected to other pins of type pwr. How do I make it accept that? There is no concept like pwr in or pwr out, so just giving it the pwr pintype should be ok. [snip] The unconnected pins can be left unconnected, how can I make it accept that? If you connect them to a special nc (no connection) symbol, drc2 will ignore them. Best regards, Carlos ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Icarus Verilog 0.9.3 is Available
The developers are pleased to announce the next stable release in the 0.9 series, version 0.9.3. Icarus Verilog is a mostly complete implementation of the hardware description language Verilog, as described in IEEE Std 1364-2005. It also includes a number of user requested extensions. It is freely available (open source), is supported on most operating systems, and will be available as a precompiled package for many of these systems. Icarus Verilog 0.9.3 improves language coverage over the previous stable release, but is primarily a bug fix release. Therefore, we recommend people using the 0.9.2 release upgrade to 0.9.3 as soon as possible. Version 0.9.3 is the recommended version for all new users. More details, including known limitations, deviations from IEEE Std 1364-2005, where to obtain the source code, and links to some of the precompiled packages can be found in the Release Notes located here: http://iverilog.wikia.com/wiki/Release_Notes_Icarus_Verilog_0_9_3 -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Zero length pins
John Doty wrote: Appending the following line to your .sym file will get you started: P 100 100 100 100 1 0 0 Nice. I added this to the wiki. http://geda.seul.org/wiki/geda:faq-gschem#is_it_possible_to_have_zero_length_pins Unattached, it looks like a little red flag, while with a net attached it disappears. Gnetlist has no trouble treating it as a pin. With your permission, I used these two sentences unaltered. and thereby gaining unusual flexibility. Genius. So flexible, that it can't deal properly with µ and ?, let alone right to left scripting, or Chinese. Multi line text cannot be centered or flushed to the right. Ellipses are impossible, lines bear no thickness. Color space is limited to a whooping 19. The mark at the active end of a pin relies purely on color. This leaves those with color blindness in the dark. The flexibility you praise, is very narrowly defined. ---)kaimartin(--- -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=getsearch=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist -g drc2 and pintype
kai-martin knaak wrote: The unconnected pins can be left unconnected, how can I make it accept that? I don't know. I put my own nc.sym at pins that are deliberately not connected. This symbol contains just one pin and no net. However, DRC still complains, because the generated net is connected to only one pin. How about a special net no_net to deal with this situation? This net would be ignored for generation of the net list. Update: There are already not-connected symbols in the default library. The following symbols live in the misc department: nc-bottom-1.sym nc-top-1.sym nc-right-1.sym nc-left.sym The drc2 backend ignores them and does not throw errors, or warnings. The magic is achieved by: device=DRC_Directive value=NoConnection graphical=1 I combined this magic with the zero pin size trick John D. told about in the other thread, to get a simplified nc-symbol. http://www.gedasymbols.org/user/kai_martin_knaak/symbols/power/nc.sym ---)kaimartin(--- -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=getsearch=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
