gEDA-user: new vhd2vl on its way
Friends - I have a new release of vhd2vl pretty much ready to post. If any existing user wants a preview -- especially to check for regressions -- contact me by private email in the next 48 hours. Sorry Steve Wilson, still no VHDL package support. :-( Changes 2.3 to 2.4 (XXX incomplete, do not distribute!!!) (Larry Doolittle, November 2010) Grammar: * Drop DOS-style returns at end of comments * Allow FLOAT in expressions (maybe a mistake) * fixed regression in "others" handling since 2.1 (the following were submitted by Shankar Giri) * Verilog 2001 module declaration (select at runtime with -g2001) * named generate block support for XST compatibility * support for array of vectors * some generic enhancements on architecture body Coding: * CLI enhancement (added more switches) * factor out push_clkedge(), pull_clkedge() * fully const-correct (XXX remove strdup, use error-checking) * minor whitespace and coding style cleanup - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: New branch of PCB
I guess I didn't realize PCB was mainly for hobby use... WHAT??? Rick At 06:09 AM 11/16/2010, you wrote: With TopoR having a freeware version for 2 layers and up to 256 nets (or some other fairly high for 'hobby' use limitation), there's not really any point on bothering improving built in autorouter... Does PCB have Specctra DSN/SES export/import? Just use that (or implement if it doesn't) and then use any of the autorouters that work. -tc On Tue, Nov 16, 2010 at 7:52 PM, Jan Martinek wrote: > On 11/15/2010 09:24 PM, Stephen Ecob wrote: >> >> On Tue, Nov 16, 2010 at 12:47 AM, Kai-Martin Knaak >> wrote: >>> >>> Stephen Ecob wrote: >>> Motivation Having laid out a couple of boards with PCB 20091103 I became aware of some bugs in the autorouter that made the job difficult: >>> >>> Are you talking about the default auto router. Or is this about the >>> shiny, >>> new "toporouter"? >> >> I'm talking about the default auto router. >> > > Oh, that's a pity. But are there any common parts of source code which both > routers share? I mean - if you fix some bug in default auto router, will > that fix the same bug in toporouter? > > I suppose that if Anthony Blake finishes his toporouter someday, all effort > for improvement the default autorouter may be pointless. Toporouter's > algorithm is really better, but there are "failed asserts" sometimes. > > Jan Martinek > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: STEP Format? [WAS: Re: PCB+GL+3D Packages??]
On Wed, 2010-11-17 at 18:01 -0600, John Griessen wrote: > I put an example with rectangular solid, cylinder and some lines in a > triangle at > http://ecosensory.com/diybio/pcb-testing.zip I'm not sure there is any colour information in any of the files, but to me it would seem that the order of ease in processing would be: stl (very nice) iges (simple format, but I have no clue what the syntax is ;)) STEP (_utterly_ evil format). -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: STEP Format? [WAS: Re: PCB+GL+3D Packages??]
On 11/17/2010 12:50 PM, Peter Clifton wrote: Can someone send me a handful of __SIMPLE__ geometric models in a STEP format (readable text?), so I can get a feel for what I'd be letting myself in for? I put an example with rectangular solid, cylinder and some lines in a triangle at http://ecosensory.com/diybio/pcb-testing.zip It unzips to make a dir with this: j...@toolbench:~/EEProjects/junk$ ls pcb-testing pcb-example.heeks pcb-example.iges pcb-example.opencamlib.py pcb-example.step pcb-example.stl John -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: STEP Format? [WAS: Re: PCB+GL+3D Packages??]
On 11/17/2010 04:00 PM, Armin Faltl wrote: If we need only a hand full of primitives to describe our parts, IGES is probably much easier and does the job. It's understood by practically all systems that understand STEP, and some, that don't understand STEP. Yes, HeeksCAD and many others can use IGES. JG ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: STEP Format? [WAS: Re: PCB+GL+3D Packages??]
Peter Clifton wrote: On Mon, 2010-11-15 at 10:09 -0600, John Griessen wrote: On 11/14/2010 08:37 PM, Peter Clifton wrote: 3. What format would people like to make models in? STEP, so I can load it in HeeksCAD and use HeeksCNC to carve enclosures. Step looks obscenely complicated, and I'm not really sure what subset we can support. If we need only a hand full of primitives to describe our parts, IGES is probably much easier and does the job. It's understood by practically all systems that understand STEP, and some, that don't understand STEP. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: STEP Format? [WAS: Re: PCB+GL+3D Packages??]
On Mon, 2010-11-15 at 10:09 -0600, John Griessen wrote: > On 11/14/2010 08:37 PM, Peter Clifton wrote: > > 3. What format would people like to make models in? > STEP, so I can load it in HeeksCAD and use HeeksCNC to carve enclosures. Step looks obscenely complicated, and I'm not really sure what subset we can support. Can someone send me a handful of __SIMPLE__ geometric models in a STEP format (readable text?), so I can get a feel for what I'd be letting myself in for? I'm wondering if STEP to VRML might be nicer, as VRML should be a lot easier to parse. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
