Re: gEDA-user: control verilog module parameter order when converting .sch and .sym with gnetlist?
Hello Al Davis and Paul Tan, you solved problem, thank alot. To summarize: If I create schematic and assign the attribute 'netname=' to the nets coming from our going to the i-/opads and a symbol with the attribute 'pinnumber=' at the appropriate pin, they are connected explicitly using that name. If I want to create a verilog module that accepts parameters in a specific order, I have to assign the 'pinnumber=[IN | OUT]' in top- to bottom order to the pins of the symbol and the netnames of the schematic and include the attribute 'VERILOG_PORTS=POSITIONAL'. Cool, thanks :) Btw: The bufif1 symbol from the verilog library get's compiled with it's inputs in the wrong order. That is the gnetlist -g verilog produced bufif1(IN,OUT,CNTRL) instead of bufif1(OUT,IN,CNTRL). How can I change that? I changed the INPUT0 and INPUT1 statements in the attributes of the pins, but that didn't change anything. Cheers, Chris --- On Sun, 11/21/10, al davis wrote: From: al davis Subject: Re: gEDA-user: control verilog module parameter order when converting .sch and .sym with gnetlist? To: geda-user@moria.seul.org Date: Sunday, November 21, 2010, 10:07 PM On Sunday 21 November 2010, Paul Tan wrote: > Since most Verilog simulators (including Icarus Verilog) > support "EXPLICIT connection" method for the lower level > Module Instanciations, so it is not absolutely necessary > (although desirable) to match the Module portname order > with the Module instantiation portname order. I think it is safe to assume that ALL Verilog simulators support the explicit form. The explicit form is preferred. I don't see any practical way that the netlister can reliably support connection mapping strictly by order. It's a real pain in Spice. If someone is going to improve the Verilog netlister, there are other points that really do need to be addressed, such as passing parameters and net types other than "wire". Gnucap needs them. ___ geda-user mailing list [1]geda-u...@moria.seul.org [2]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. file://localhost/mc/compose?to=geda-u...@moria.seul.org 2. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: exporting single pcb layers
> in the process of cnc-milling a pcb with a custom shape using pcb2gcode > [1], i created a polygon on a separate layer... Have you ever tried the g-code exporter included in PCB? I've never been able to make pcb2gcode work with minimally complex boards. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Different slot types within on symbol
Peter, Different symbols for each slot is no problem. I will try that tomorrow. I was messing around with the slot=1 slot=2 trying to make things work and getting no where. Does the slot keyword do anything other than define the beginning of a slot? Oliver __ From: Peter Clifton To: gEDA user mailing list Sent: Sun, November 21, 2010 6:30:27 PM Subject: Re: gEDA-user: Different slot types within on symbol On Sun, 2010-11-21 at 16:52 -0800, Oliver King-Smith wrote: > Is it possible to create a symbol with two types of slots. For >example, in a 4 OR gates logic chip, one slot type would be the OR >gate, while the other slot type would be the power connections. I see >people typical wire the pins that are not part of a slot to nets, but >that seems to hide them. I prefer to explicitly see the power on my >chips so I can check the decoupling strategy. >If you have any suggestions or examples please let me know. >Thanks in advance >Oliver Not exactly, but you can have multiple symbols all instantiated with the same refdes= to build up your part. You can have one symbol for the OR gate parts, another for the power. See for example 74power-1.sym in the library. That is a slightly bad example though, as all the 74* symbols in the library also have hidden "net=" attributes which wire up their power pins. The idea is solid though. Best regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list [1]geda-u...@moria.seul.org [2]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:geda-user@moria.seul.org 2. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: control verilog module parameter order when converting .sch and .sym with gnetlist?
On Sunday 21 November 2010, Paul Tan wrote: > Since most Verilog simulators (including Icarus Verilog) > support "EXPLICIT connection" method for the lower level > Module Instanciations, so it is not absolutely necessary > (although desirable) to match the Module portname order > with the Module instantiation portname order. I think it is safe to assume that ALL Verilog simulators support the explicit form. The explicit form is preferred. I don't see any practical way that the netlister can reliably support connection mapping strictly by order. It's a real pain in Spice. If someone is going to improve the Verilog netlister, there are other points that really do need to be addressed, such as passing parameters and net types other than "wire". Gnucap needs them. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: control verilog module parameter order when converting .sch and .sym with gnetlist?
Hi Chris, Last time I checked, when netlisting a schematic, the gEDA Verilog netlister does not order the top MODULE portnames by user specified sequence order(such as using the refdes attribute's numeric suffix value of I/O PADS to order the portnames). Since most Verilog simulators (including Icarus Verilog) support "EXPLICIT connection" method for the lower level Module Instanciations, so it is not absolutely necessary (although desirable) to match the Module portname order with the Module instantiation portname order. The following hierarchical netlist format is legal in Verilog. // module DFF ( R, D, C, ... ); wire R; ... end module; // module REGX32 (DBUS, CLK, RD, WR, RST, ...); wire [31:0] DBUS; wire CLK; // Modules instantiations DFF U1 ( // portname connected-signal-netname .D ( DBUS[0] ), .C ( CLK ), .R ( RST ), ... ); ... end module; // However, last time I checked, Icarus Verilog does not support EXPLICIT connection method when wire connects to Verilog Primitives, such as pmos, nand, xor, etc. So your Primitive Instantiation section of your netlist should look like the following "IMPLICIT" connection: nand U5 ( // portname(commented out) connected netname /* OUT */ net1, /* IN0 */ net2, /* IN1 */ net3 ); gEDA Verilog netlister handles this situation correctly if you add to all the primitive symbols (nand, etc) the attribute "VERILOG_PORTS=POSITIONAL", and if you make sure your symbol file, e.g.,and8-1.sym (open in text editor) list the "pinnumber=???" in top to bottom order. Refer to the stocked Verilog symbol file and8-1.sym file as an example: pinnumber=OUT pinnumber=IN0 . pinnumber=IN7 (please refer to the gEDA document "README.verilog" file or the gEDA wiki). Best Regards, Paul Tan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB+GL resistor p0rn
If it was me, I think I'd make a script for some 3D modelling package like FreeCAD to generate a 3D model using PCB's XY place file output. The process would be: 1. make FreeCAD 3D models for each of the components 2. generate an XY place file, board outline file and drill file in PCB 3. run a python script in FreeCAD that generates a model of the board based on the outline gerber file. Make holes using data from the drill file. 4. Run a script that makes an assembly by placing components based on the XY place file. At this point you should have a 3D model of the board, right in a 3D CAD program that can be used to model enclosures and other parts. - Original Message From: John Griessen To: gEDA user mailing list Sent: Sun, November 21, 2010 1:29:38 PM Subject: Re: gEDA-user: PCB+GL resistor p0rn On 11/21/2010 11:49 AM, Dave McGuire wrote: > Perhaps pixel shaders and bump mapping is a little overkill for a few > resistors, but it has kept me amused for a while. Looks fab! Will actually be useful. Why not have processors churn for us? Overkill? There are so many ways to kill the problem of not-fully-designed circuits...and enclosures... How could one have overkill? The more ammo the better! Thanks, John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Different slot types within on symbol
On Nov 21, 2010, at 7:30 PM, Peter Clifton wrote: > That is a slightly bad > example though, as all the 74* symbols in the library also have hidden > "net=" attributes which wire up their power pins. The idea is solid > though. Every tutorial on gEDA should state up front: LIBRARY SYMBOLS ARE ONLY STARTING POINTS. COPY AND CUSTOMIZE THEM TO FIT *YOUR* DESIGN FLOW AS NEEDED. So, if you want to use separate power symbols, copy the library symbols to your project's symbol repository, and delete the net= attributes. That the symbol browser doesn't copy the symbol to a project repository by default (assuming that this is defined in gafrc) is a problem. It perpetuates the illusion that the library is universal to all flows, and that such a library is possible. On the other hand, ONCE YOU HAVE MADE THE PROJECT LOCAL COPY, Hierarchy->Down Symbol is very useful. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB+GL resistor p0rn
On Sun, 2010-11-21 at 22:45 +0100, kai-martin knaak wrote: > John Griessen wrote: > > > How could one have overkill? > > Inefficient use of developer cycles. Traditionally, the most valuable > resource open source projects. Developers having fun are happy developers, and might even find time for some more boring work. I've almost been tempted to set myself the goal of merging the PCB+GL (non-3D) bits this week ;) -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Different slot types within on symbol
On Sun, 2010-11-21 at 16:52 -0800, Oliver King-Smith wrote: > Is it possible to create a symbol with two types of slots. For >example, in a 4 OR gates logic chip, one slot type would be the OR >gate, while the other slot type would be the power connections. I see >people typical wire the pins that are not part of a slot to nets, but >that seems to hide them. I prefer to explicitly see the power on my >chips so I can check the decoupling strategy. >If you have any suggestions or examples please let me know. >Thanks in advance >Oliver Not exactly, but you can have multiple symbols all instantiated with the same refdes= to build up your part. You can have one symbol for the OR gate parts, another for the power. See for example 74power-1.sym in the library. That is a slightly bad example though, as all the 74* symbols in the library also have hidden "net=" attributes which wire up their power pins. The idea is solid though. Best regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Different slot types within on symbol
Is it possible to create a symbol with two types of slots. For example, in a 4 OR gates logic chip, one slot type would be the OR gate, while the other slot type would be the power connections. I see people typical wire the pins that are not part of a slot to nets, but that seems to hide them. I prefer to explicitly see the power on my chips so I can check the decoupling strategy. If you have any suggestions or examples please let me know. Thanks in advance Oliver ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB+GL resistor p0rn
John Griessen wrote: > How could one have overkill? Inefficient use of developer cycles. Traditionally, the most valuable resource open source projects. ---<)kaimartin(>--- -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=get&search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: a different approach to 3D modeling
On 21 November 2010 02:05, Peter Clifton wrote: > On Sat, 2010-11-20 at 22:48 +, Gareth Edwards wrote: >> The usability of the Blender 2.5x betas is a step-change from the >> existing versions. I'm not saying it's easy, but it's considerably >> less insane. > > Just installed it, seems pretty good compared with 2.45. > Thanks for the pointer! > Also, I have a reasonable amount of Blender experience so feel free to ping me if you need any help (on- or off-list). I think that in spite of its faults, Blender is the dominant FOSS 3D application and it should be at least an option for getting models into a 3D-capable pcb. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB+GL resistor p0rn
On 11/21/2010 11:49 AM, Dave McGuire wrote: Perhaps pixel shaders and bump mapping is a little overkill for a few resistors, but it has kept me amused for a while. Looks fab! Will actually be useful. Why not have processors churn for us? Overkill? There are so many ways to kill the problem of not-fully-designed circuits...and enclosures... How could one have overkill? The more ammo the better! Thanks, John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB+GL resistor p0rn
On 11/19/10 12:21 PM, Peter Clifton wrote: http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d_packages_mockup3.png http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d_packages_mockup4.png Perhaps pixel shaders and bump mapping is a little overkill for a few resistors, but it has kept me amused for a while. I'm working on a VRML importer at the moment, as this will give us access to models people have created for KiCad. (And hopefully the converse too, when PCB+GL+3D lands and users start creating models). WOW that is gorgeous! -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: If you also think the PCB lower-case letter 's' is ugly, here's a replacement
On Sun, 2010-11-21 at 02:03 -0800, Cory Cross wrote:
> Symbol('s' 10)
> (
> SymbolLine(0 50 20 50 8)
> SymbolLine(20 50 25 45 8)
> SymbolLine(20 40 25 45 8)
> SymbolLine(5 40 20 40 8)
> SymbolLine(0 35 5 40 8)
> SymbolLine(0 35 5 30 8)
> SymbolLine(5 30 25 30 8)
> )
Tried it, and prefer the original. The weight of the ends of the glyph
stroke seem wrong, and need shortening. I tried this and realised the
whole glyph is just too wide, and is out of proportion. I came up with
this:
Symbol('s' 8)
(
SymbolLine(2 50 18 50 8)
SymbolLine(18 50 23 45 8)
SymbolLine(18 40 23 45 8)
SymbolLine(5 40 18 40 8)
SymbolLine(0 35 5 40 8)
SymbolLine(0 35 5 30 8)
SymbolLine(5 30 21 30 8)
)
It still isn't perfect by any means, and I would be tempted to
re-introduce the inflections on the end of the stroke which your glyph
removed. (Keeping them small though).
To make gsch2pcb pick it up, you would need to adjust the template file
in $PREFIX/share/gEDA/scheme/gnet-gsch2pcb.scm
(OR change PCB's default font file).
The gsch2pcb template is currently based on a VERY old PCB file format,
and would need updating. Once you've done that, you can include the font
block from a more modern PCB file, but you will have to define every
glyph.
The future is not using gsch2pcb to make a PCB file directly of course,
DJ has been working on a better import mechanism, which we should teach
gsch2pcb to make use of. (Which would then make PCB create the file).
In this idealised version of the future, the only immediate way you
would have to override the font is to edit PCB's default font,
$PREFIX/share/pcb/default_font
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
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gEDA-user: control verilog module parameter order when converting .sch and .sym with gnetlist?
Hello mailing list,
I need some help here. I want to use gschem to create a hierarchical
design and simulate that using icarus verilog. "gnetlist -g verilog"
works fine, but I have some trouble figuring out how to create a
matching symbol for the schematic and using gnetlist to assign module
parameters in a certain order.
In particular, I can't figure out how to enforce the module parameter
order in the verilog file by assigning attributes to my schematic and
symbols. I suspect that the pinnumber of the symbol are somehow matched
to the INPUT# values of the schematics pads, but I can't find any
documentation how that is done (and reading the
/usr/share/gEDA/scheme/gnet-verilog.scm was also not all too helpfull).
Starting of with the basics, I built a rs-flipfop schematic with the
inputs A,B,CLK,Q and nQ. I want the module created with "gnetlist -g
verilog" to create the module with that exact parameter order, that is
it should produce a header looking like "module rs_ff ( S, R, CLK, Q,
nQ);". Instead when I convert the schematic, I end up with a "module
rs_ff (R,CLK,S,nQ,Q)". Pinnumber, Pinsequence and Pintypes ("INPUT0",
"OUTPUT0"...) are set on the ipads and opads but obviously get ignored.
I then created a symbol for the rs-flipflop (pinnumbers, pinsequence
and pintypes of the same value as those of the pads in the schematic)
and placed it into a schematic file forming a d-flipflop. The input
nets and output net are correctly translated to the module parameter
order, but I am not sure if this is just luck or not.
RS_FF.symVerliog assignment
0| |3rs_ff rs_ff0 (nD,CLK,D,nQ,Q);
--D--=|S Q|=---Q
1| |
-CLK-=|CLK|
2| |4
--nD-=|RnQ|=---nQ---
|___|
RS_FF.schmVerilog Assignement
__
|S \_netname=S__ ...
|__/ __
..._netname=Q___/ Q|module (R,CLK,S,Q,nQ);
\__|
__
|C \_netname=CLK_ ...
|__/ __
..._netname=nQ__/nQ|
\__|
__
|R \_netname=R__ ...
|__/
I can't really get a grip on which pin of the symbol get's assigned to
which pin of the hierarchically underlying schematic when a schematic
containing the symbol get's converted to verilog. Equally, when running
the symbol's schematic through gnetlist I can't control in what order
the Inputs and Outputs get listed as module Parameters.
How can I enforce a certain parameter order in verilog modules when
using ipads and opads in a schematic or pins in a symbol?
Thanks for you help and time,
Cheers,
Chris
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gEDA-user: If you also think the PCB lower-case letter 's' is ugly, here's a replacement
Hi all,
I've always hated the lower-case letter 's' in PCB, but couldn't come up
with a better one until now. And if anyone knows where I could put it to
make gsch2pcb use it, I'd be much obliged.
Cory
Symbol('s' 10)
(
SymbolLine(0 50 20 50 8)
SymbolLine(20 50 25 45 8)
SymbolLine(20 40 25 45 8)
SymbolLine(5 40 20 40 8)
SymbolLine(0 35 5 40 8)
SymbolLine(0 35 5 30 8)
SymbolLine(5 30 25 30 8)
)
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Re: gEDA-user: a different approach to 3D modeling
Hi all, > -Original Message- > From: geda-user-boun...@moria.seul.org > [mailto:geda-user-boun...@moria.seul.org] On Behalf Of Armin Faltl > Sent: Saturday, November 20, 2010 11:53 AM > To: gEDA user mailing list > Subject: Re: gEDA-user: a different approach to 3D modeling > > Patrick Doyle wrote: > > On Thu, Nov 18, 2010 at 10:01 PM, kai-martin knaak > wrote: > > > >> Looks like there is no open 3D exchange format that fits > the need of > >> pcb: > >> > >> a) render a beautiful image of a populated board > >> > >> b) integrate pcb in a 3D work-flow to fit the board into > some tight > >> space. > >> > >> The existing formats are either limited to surfaces rather than > >> objects (STL, VRML). This prevents efficient processing of > the 3D geometry. > >> Or they lack attributes for eye candy (IGES). Or they are overly > >> complex and geared to completely different use cases (STEP) > >> > > Not knowing anything of which I speak (write?), would COLLADA > > > (https://collada.org/mediawiki/index.php/COLLADA_-_Digital_Asset_and_F > > X_Exchange_Schema) > > fit the bill? > Reading > > https://collada.org/mediawiki/index.php/COLLADA_FAQ#What_is_COLLADA.3F > > I believe COLLADA is a format mainly concerned about DCC > (digital content creation). > It's probably very good at meshes, textures and some freeform > surfaces, but I didn't see anything about geometric > primitives like spheres, cylinders dimensions and layers. > Don't confuse "rigid body" with "solid geometry". > Maybe my view is to pessimistic, but one needs to read the > spec to prove. > > > Just my thoughts on this matter: The COLLADA FAQ says (amongst many other things): Q: Are COLLADA documents included as part of games? A: COLLADA is not designed to be used as a final game format. COLLADA allows 3D content to be created in any 3D package, exported to COLLADA format and edited with a variety of tools from different vendors. Once the content is finalized, it is usually processed into whatever format is most efficient for the game engine and hardware platform being used. AFAICT, THE COLLADA format can transport 3D-data from A to many Bs. 3D data can either be a set of vertexes or primitives. It does not solve the "primitives versus vertexes" discussion for us, that is a decision the pcb dev/user community has to make, or just do both so the user has a choice. A pcb exporter (or plugin) will still have to generate this 3D data. Do you take the blue pill or the red pill, Neo ? For now I continue with the OpenSCAD route. When and if this gets to work according to my expectations, as I hope it will (there are some limitations that need be solved on the OpenSCAD side), then maybe gEDA can get some leverage in the Makerbot and Reprap communities. There seems to a variety of encasings for pcbs made with them plastruders. http://www.thingiverse.com/thing:4071 http://www.thingiverse.com/thing:3944 http://www.thingiverse.com/thing:3665 http://www.thingiverse.com/thing:3559 http://www.thingiverse.com/thing:3372 http://www.thingiverse.com/thing:3363 http://www.thingiverse.com/thing:2982 Printable RC filter redux (should have been done with pcb) http://www.thingiverse.com/thing:2360 http://www.thingiverse.com/thing:1904 Parametric QF Breakout Board (should have been done with pcb) http://www.thingiverse.com/thing:1716 Just my EUR 0.02 Kind regards, Bert Timmerman ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Need papers of Toporouter
The most relevant of those can be found with a google search. Good luck! -- Anthony Blake ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
