date:20110115

On Fri, 2011-01-14 at 21:14 -0500, al davis wrote:
 Reading a file is easy.  The hard part about the geda format, 
 where use of libgeda may be advantageous, is establishing 
 connectivity.

A mix of libgeda, with gnetlist wading in and flattening things (perhaps
unhelpfully). I want to see all connectivity code move into libgeda, and
flattening be optional.

   I don't know where that is done, or if it is done 
 in a form that would be useful here, or whether there exists the 
 code to go the other way (generate a schematic given a netlist 
 and rendering info) which is equally needed.

Not done. Would be nice though - but I'd rate it of similar complexity
to a board auto-router. (Not as rigidly constrained topologically, but
to do well would require a decent auto-place, and a decent auto-router -
even if the rules are different to that used with a PCB).

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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Re: gEDA-user: Rant about Make Inv Text Vis

On Sat, 2011-01-15 at 07:54 +, Peter TB Brett wrote:
 - Original message -
  What is the point of the command Make Inv Text Vis in gschem, other than 
  aggravating me.
 
 Good question. I'm not aware of a use-case for it either.  At the very
 least, it should be undo-able.  Please file a bug report.

Lets kill it with fire.

If it wants to come back, it should be in the form of bulk editing of a
set of selected attributes.

Are there any use-cases for invisible text which is not an attribute?
Since it might exist already though - we MAY have to add an:
Invisble [x] option to the text edit dialogue box.

The Make Inv text vis option is hardly a friendly way to work around
that (non-existant) option though.. so I don't think removing it will
hurt.

As a kludge, to make invisible non attribute text visible, you have to
put an =foo in it or something like that, so it registers as an
attribute.. change the attribute visibility, then edit it with an
explicit ex (edit text), to change it back.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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Re: gEDA-user: Rant about Make Inv Text Vis

2011-01-15 Thread Markus Hitter



Am 15.01.2011 um 09:47 schrieb Peter Clifton:


On Sat, 2011-01-15 at 07:54 +, Peter TB Brett wrote:

- Original message -
What is the point of the command Make Inv Text Vis in gschem,  
other than

aggravating me.


Good question. I'm not aware of a use-case for it either.  At the  
very

least, it should be undo-able.  Please file a bug report.


Lets kill it with fire.


One use-case would be to quickly inspect all of these attributes. It  
makes a difference wether you see attributes in a seperate sheet vs.  
you see them right next to each symbol.


For making this use-case, this command should actually do what it  
says: make invisible text visible, i.e. leave everything stored in  
the schmatic's file untouched. Instead, it sets the visible flag on  
all texts, which is nonsense, of course.



Markus

- - - - - - - - - - - - - - - - - - -
Dipl. Ing. (FH) Markus Hitter
http://www.jump-ing.de/







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Re: gEDA-user: Rant about Make Inv Text Vis

2011-01-15 Thread Bob Paddock

 Lets kill it with fire.

 One use-case would be to quickly inspect all of these attributes. It makes a
 difference wether you see attributes in a seperate sheet vs. you see them
 right next to each symbol.

I don't know if it applies to the feature you are discussing or not,
but I have a use case where I need to turn off global visibility of
values for items.
In any normal schematic, destined for a PCB layout, there is normally
a designator and a value, like R1 : 1k.

A Government agency that I have the misfortune of submitting
schematics to for approval of my devices rejects any schematics that
shows the value.
They say it makes to much work for them to compare the schematic and
BOM to make sure the values match.


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Re: gEDA-user: Soft and Hard symbols

2011-01-15 Thread Stephan Boettcher

Peter Clifton pc...@cam.ac.uk writes:

 On Fri, 2011-01-14 at 21:14 -0500, al davis wrote:
 Reading a file is easy.  The hard part about the geda format, 
 where use of libgeda may be advantageous, is establishing 
 connectivity.

 A mix of libgeda, with gnetlist wading in and flattening things (perhaps
 unhelpfully). I want to see all connectivity code move into libgeda, and
 flattening be optional.

   I don't know where that is done, or if it is done 
 in a form that would be useful here, or whether there exists the 
 code to go the other way (generate a schematic given a netlist 
 and rendering info) which is equally needed.

 Not done. Would be nice though - but I'd rate it of similar complexity
 to a board auto-router. (Not as rigidly constrained topologically, but
 to do well would require a decent auto-place, and a decent auto-router -
 even if the rules are different to that used with a PCB).

Why would anybody want such a schematic?

I see two semi-graphical ways to express a netlist in gschem format.

1. Each element uses the same generic symbol, with the proper attributes
attached, and net= attributes for connectivity.  Placed on some grid in
arbitrary order, optionally so that the attribute lists do not overlap
when viewed graphically.

2. When symbols are available for the elements, those can be placed on
some grid, and each pin gets a little net stub with netname= for
connectivity.

Last millenium, some cadence netlister move such schematics from
synthesized Verilog netlist, but I do not remember why they were needed
in the flow, certainly not for human inspection.  

A mixture between 1. and 2., in case there is some way to feed an
element to symbol map into the process, falling back to 1. for elements
without symbols.  But that use case is 

What are the use-cases?

Mix gschem schematics with synthesis output into gnetlist for ASIC or
simulation targets?

-- 
Stephan


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Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]

2011-01-15 Thread Bob Paddock

 a) They have Altium
 b) They have bits in Altium already (footprints etc..) - momentum.
 c) They need an auto-router which can handle really complex stuff.

Hun?  Three of us at work have spent weeks trying to get Altium's
autorouter to do much at all, and do it correctly when it does, and
finally gave up.
As far I can tell the native Altium router is just there to irritate
you enough to force your boss into spending the money for their high
end optional router.

The autorouter in PCB 'just works'.

 d) Blind / buried vias may be needed.

Which is why I still endure Altium.  I know there is a build of PCB
'out there' that does have the patch applied for this.

 No-one could in good conscience suggest PCB is going to be able to
 compete up with that sort of design.

I must be unconscious, as I use both regularly.  PCB has its faults,
mostly in the user interface, where Altium the faults are everyplace.
For example there are multiple places to set up the printer.  Some of
the places work, some of the places interact with the other places,
some places do nothing, and in the end you may or may not get what you
wanted on the printer.  My favorite is move a schematic from one place
to an other, or even open the same schematic with the same version of
Altium after reinstalling it due to a hard disk failure, and all of
the schematic symbols now have 'dots' in them that you can't get rid
of without redoing the schematic for every symbol.

 git HEAD rendering speed alone
 would make it prohibitive.

You don't turn on the Altium's autorouter's 'show trials' unless your
goal is to goof off.

 Not necessarily.. but whatever happens, it may well be beneficial to the
 community as a whole.

I've never had much luck with Altium's own Import/Export working in
trying to go between that and PADS.
Seems like they really don't want it to work.  You also have to know
what version of Altium is being talked about because the
proprietary file formats have changed over the years, in ways that are
not backwards compatible with older versions.


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Re: gEDA-user: Rant about Make Inv Text Vis

On Sat, 2011-01-15 at 10:43 +0100, Markus Hitter wrote:
  Lets kill it with fire.
 
 One use-case would be to quickly inspect all of these attributes. It  
 makes a difference wether you see attributes in a seperate sheet vs.  
 you see them right next to each symbol.

For that we have Edit-Show/Hide invisible text That is the one which
does as you suggest.

It is the option which _changes_ visibility we wish to kill.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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Re: gEDA-user: Rant about Make Inv Text Vis

On Sat, 2011-01-15 at 07:06 -0500, Bob Paddock wrote:
 I don't know if it applies to the feature you are discussing or not,
 but I have a use case where I need to turn off global visibility of
 values for items.
 In any normal schematic, destined for a PCB layout, there is normally
 a designator and a value, like R1 : 1k.
 
 A Government agency that I have the misfortune of submitting
 schematics to for approval of my devices rejects any schematics that
 shows the value.
 They say it makes to much work for them to compare the schematic and
 BOM to make sure the values match.

There was no proposal to remove the ability to hide attributes, just the
magic break my schematic button which makes every hidden attribute
visible in a way which is not trivial to undo.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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Re: gEDA-user: Soft and Hard symbols

On Sat, 2011-01-15 at 13:10 +0100, Stephan Boettcher wrote:
 
 What are the use-cases?

IMO, only viewing of synthesis results, or matching up / creating a
schematic which matches an extracted netlist - either from reverse
engineering, layout extraction, or from another program.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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Re: gEDA-user: Rant about Make Inv Text Vis

2011-01-15 Thread Stephan Boettcher

Peter Clifton pc...@cam.ac.uk writes:

 On Sat, 2011-01-15 at 07:54 +, Peter TB Brett wrote:
 - Original message -
  What is the point of the command Make Inv Text Vis in gschem, other than 
  aggravating me.
 
 Good question. I'm not aware of a use-case for it either.  At the very
 least, it should be undo-able.  Please file a bug report.

 Lets kill it with fire.

Yes, please!

-- 
Stephan


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Re: gEDA-user: Rant about Make Inv Text Vis


On 01/15/2011 06:59 AM, Stephan Boettcher wrote:

Yes, please!


+1

John


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Re: gEDA-user: Rant about Make Inv Text Vis

On Sat, 2011-01-15 at 09:10 -0600, John Griessen wrote:
 On 01/15/2011 06:59 AM, Stephan Boettcher wrote:
  Yes, please!
 
 +1

Consider it napalmed.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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gEDA-user: gEDA flow for chip design?

2011-01-15 Thread Florian E. Teply

Hi folks,

I seem to recall that some guys here use gEDA for chip design. John
Doty comes to mind, but i think there are others too. I'd be interested
in the workflow as i will have to make up some clever test chips in the
next few years for PhD work and i'm not in the position to be able
to sell my grandma for a full-fledged cadence seat, nor am i willing to.

If reasonably possible, i'd want both simulation as well as generation
of production-ready data (GDS or OASIS files, preferably OASIS), but
have not the slightest idea on how to accomplish that or even if that's
possible with open source software, let alone from whithin gEDA.

Any suggestions?

Thanks,
Florian


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Re: gEDA-user: Rant about Make Inv Text Vis

2011-01-15 Thread Kai-Martin Knaak

Markus Hitter wrote:

 One use-case would be to quickly inspect all of these attributes. It  
 makes a difference wether you see attributes in a seperate sheet vs.  
 you see them right next to each symbol.

I regularly do this for the footprint attribute with
Attributes - Show/Hide_Specific_Text

---)kaimartin(---
-- 
Kai-Martin Knaak
Email: k...@familieknaak.de
Öffentlicher PGP-Schlüssel:
http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53



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Re: gEDA-user: gEDA flow for chip design?

2011-01-15 Thread Bob Paddock

 Any suggestions?

There is also Toped: http://code.google.com/p/toped/


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Re: gEDA-user: gEDA flow for chip design?

2011-01-15 Thread Patrick Doyle

Hello Florian,
I wish I could say that I could help, but instead I'd like to say I
too am interested in learning what's involved in using gEDA for chip
design.

I'm not even sure where to begin, other than to share the few things
I've thought about so far (however naive or clueless those thoughts
may be).

In no particular order...
I think it would be nice if I could open up existing Cadence designs
(Open Access versions) in gschem.  To that end, I have signed a
license agreement with Si2 to gain access to the OA documentation and
API and have gotten shell shocked by the fact that the OA tutorial is
over 1000 pages long.  I'm not sure if I've bitten off more than I can
chew or not.

I think it would be nice if I could run some transistor level chip
sims with gnucap.  Being a digital guy, I have absolutely no idea
what's involved in doing that, except to assume that there are other
folks (folks at Analog Rails come to mind) who must know more about
this than I ever will.

I have no idea where to start on the backend -- generating a layout.

--wpd


On Sat, Jan 15, 2011 at 11:52 AM, Florian E. Teply use...@teply.info wrote:
 Hi folks,

 I seem to recall that some guys here use gEDA for chip design. John
 Doty comes to mind, but i think there are others too. I'd be interested
 in the workflow as i will have to make up some clever test chips in the
 next few years for PhD work and i'm not in the position to be able
 to sell my grandma for a full-fledged cadence seat, nor am i willing to.

 If reasonably possible, i'd want both simulation as well as generation
 of production-ready data (GDS or OASIS files, preferably OASIS), but
 have not the slightest idea on how to accomplish that or even if that's
 possible with open source software, let alone from whithin gEDA.

 Any suggestions?

 Thanks,
 Florian


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Re: gEDA-user: gEDA flow for chip design?

2011-01-15 Thread David W. Schultz

On 01/15/2011 10:52 AM, Florian E. Teply wrote:
 Hi folks,
 
 I seem to recall that some guys here use gEDA for chip design. John
 Doty comes to mind, but i think there are others too. I'd be interested
 in the workflow as i will have to make up some clever test chips in the
 next few years for PhD work and i'm not in the position to be able
 to sell my grandma for a full-fledged cadence seat, nor am i willing to.
 
 If reasonably possible, i'd want both simulation as well as generation
 of production-ready data (GDS or OASIS files, preferably OASIS), but
 have not the slightest idea on how to accomplish that or even if that's
 possible with open source software, let alone from whithin gEDA.
 
 Any suggestions?


http://opencircuitdesign.com/index.html

It has been a while but Magic is what I used in grad school. (It outputs
CIF and GDSII but not OASIS.) Since you are in grad school you should
find the local guru/professor. They can tell you who will do the fab and
any details specific to that. They probably even have access to the
required tools.


MOSIS is popular:

http://www.mosis.com/design/flows/design-flow-scmos-kits.html


-- 
David W. Schultz
http://home.earthlink.net/~david.schultz
Life without stock is barely worth living... Anthony Bourdain


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Re: gEDA-user: Rant about Make Inv Text Vis

2011-01-15 Thread Vanessa Ezekowitz

On Sat, 15 Jan 2011 16:25:39 +
Peter Clifton pc...@cam.ac.uk wrote:

 On Sat, 2011-01-15 at 09:10 -0600, John Griessen wrote:
  On 01/15/2011 06:59 AM, Stephan Boettcher wrote:
   Yes, please!
  
  +1
 
 Consider it napalmed.

Napalmed ain't enough - I want that option *nuked* (from orbit yet).   :-)

-- 
There are some things in life worth obsessing over.  Most
things aren't, and when you learn that, life improves.
http://starbase.globalpc.net/~ezekowitz
Vanessa Ezekowitz vanessaezekow...@gmail.com


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Re: gEDA-user: Rant about Make Inv Text Vis

2011-01-15 Thread Peter TB Brett

  Consider it napalmed.
 
 Napalmed ain't enough - I want that option *nuked* (from orbit yet).    

It's the only way to be sure.

                   Peter

-- 
Peter Brett pe...@peter-b.co.uk
Remote Sensing Research Group
Surrey Space Centre



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Re: gEDA-user: Rant about Make Inv Text Vis

2011-01-15 Thread Stephan Boettcher

Vanessa Ezekowitz vanessaezekow...@gmail.com writes:

 On Sat, 15 Jan 2011 16:25:39 +
 Peter Clifton pc...@cam.ac.uk wrote:

 On Sat, 2011-01-15 at 09:10 -0600, John Griessen wrote:
  On 01/15/2011 06:59 AM, Stephan Boettcher wrote:
   Yes, please!
  
  +1
 
 Consider it napalmed.

 Napalmed ain't enough - I want that option *nuked* (from orbit yet).   :-)

The worst part is the keyboard shortcut e v, just the reverse of the
frequently used v e.

-- 
Stephan


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Re: gEDA-user: gEDA flow for chip design?

2011-01-15 Thread Joe Chisolm - Gmail

On 01/15/2011 10:52 AM, Florian E. Teply wrote:

Hi folks,

I seem to recall that some guys here use gEDA for chip design. John
Doty comes to mind, but i think there are others too. I'd be interested
in the workflow as i will have to make up some clever test chips in the
next few years for PhD work and i'm not in the position to be able
to sell my grandma for a full-fledged cadence seat, nor am i willing to.

If reasonably possible, i'd want both simulation as well as generation
of production-ready data (GDS or OASIS files, preferably OASIS), but
have not the slightest idea on how to accomplish that or even if that's
possible with open source software, let alone from whithin gEDA.

Any suggestions?

Thanks,
Florian

Here is a EETimes article from 2009 about a guy who did a teach myself
project. From the article intro:

... it describes how an experienced engineer undertook to teach himself
analog IC design, including his planning, the tools, the sequence of
events, and the actual IC fabrication process. Whether you are thinking
about learning analog IC design yourself, or just want to see how you
can use available resources as part of self-paced continuing education
regardless of your engineering career stage, you'll find it of interest
and with actionable lessons and take-away information you can use

Hands-on: Get started in analog IC design and fab (Part 1 of 3)

http://www.eetimes.com/design/analog-design/4010380/Hands-on-Get-started-in-analog-IC-design-and-fab-Part-1-of-3-

--
Joe Chisolm
Marble Falls, Tx.

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Re: gEDA-user: gEDA flow for chip design?


On 01/15/2011 10:52 AM, Florian E. Teply wrote:

  i'd want both simulation as well as generation
of production-ready data (GDS or OASIS files, preferably OASIS), but
have not the slightest idea on how to accomplish that or even if that's
possible with open source software, let alone from within gEDA.

Any suggestions?

Thanks,
Florian



I've done chip logic and layout with Cadence tools and it was at
a small start up at first -- Cadence didn't care much about our
success and we had to do all kinds of self starting to get a working
flow even though it cost tons of money.  I've not done work with
magic, http://opencircuitdesign.com/verilog/index.html , but from
asking about it on its list, it can
generate GDS2 output and you can extract capacitance from layout with it.
If you sign up for its mail list you can ask Tim Edwards, the current
maintainer and guru about feasibility for your project.

John Doty mentioned his layout is hired out, but I can't remember what tools
are used.  He's going to be your resource for simulation.

What will you make?  some kind of sensor?

John Griessen


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Re: gEDA-user: gEDA flow for chip design?


On 01/15/2011 02:21 PM, Joe Chisolm - Gmail wrote:

Hands-on: Get started in analog IC design and fab (Part 1 of 3)

http://www.eetimes.com/design/analog-design/4010380/Hands-on-Get-started-in-analog-IC-design-and-fab-Part-1-of-3-


It's nice to read about what he stressed as he went after his goal.
He mentioned simulation taking the forefront and that's true -- I'd add
characterization also.  Those MOSIS runs could tell a lot with
decent test structures along with the main circuit -- structures that
don't take  a big area, but include some amplification so
you can accurately deduce some of the low level properties
of your circuitry.  Like a capacitor hooked up with some resistance
and drive transistor chain so you can feed a signal through it and
probe the response easily as a check on capacitance per area
for the process.  And long resistors with probe pads for checking R.
per area of the process.  And whatever else is crucial to your
design.

John


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Re: gEDA-user: gEDA flow for chip design?

http://www.eetimes.com/design/analog-design/4010382/Hands-on-Get-started-in-analog-IC-design-and-fab-Part-3-of-3-

an excerpt from above section:
==
Convergence and noise modeling were key issues. At each change, I had
to learn about the new tool and adapt the models and circuit files to
the new simulator. As you can imagine, all that cost a huge amount of
time, though I learned a lot. Different simulators have different
MOSFET models and adapting parameters from one to another can be difficult.
HSpice is the big bucks professional tool that the foundry's model
parameters often target. Fortunately, I was able to get temporary
access to it to complete the design.

He takes a pragmatic view, aiming for results where he could not afford to fail
by aiming at an easy commercial design, avoiding letting the scope enlarge
during his project, and choosing the mainstream proprietary tool based
on old open source Berkeley SPICE. It's tempting to fall into that
thinking and abandon open tools, but John Doty has a work flow figured out
with NG-SPICE and no proprietary tools except maybe layout.

Another way you might get around
the convergence problems and get even better performance than
Doty is to use gnucap. Al says he's done tests
on large circuits to make it perform well and converge better than
many versions of SPICE. Not yet tested by me though.

There are some hurdles to using gnucap -- I had a hard time
getting a wave viewer installed on my debian linux computer -- neither
gtkwave nor gwave are easy except on Red Hat due to some good packaging
effort by Chitlesh et al:
http://fedoraproject.org/wiki/Features/FedoraElectronicLab

debian has a new version of gtkwave since I last used it, so
I'm installing and... there aren't any examples for gnucap
I can find.

Would gnuplot work OK for gnucap? I've used it since forever and
it might even be fast now...

Here's a recipe I found searching for a gtkwave gnucap example
that suggests scripting gnuplot is less hassle than getting gwave to build...
So it could be used for gnucap as well as gwave or gtkwave, right?

John Griessen
no longer a chip designer, but thinking of down-to-the-material circuit design
for printable organic semiconductors soon. That will reset circuit density to
1978 levels,
but be throw away chp to print.

=http://chitlesh.wordpress.com/2007/07/11/life-without-gwave-when-using-gspiceui/=
A much simpler and more convenient way is using gnuplot, mimicking
gwave‘s behaviour for gspiceui.
Put the following into the file “/usr/bin/gwave”:

———-
#!/bin/bash

FILE=”$1″
HEAD=`head -n 1 “$FILE” | tr -s ‘ ‘`
COLS=`echo $HEAD | wc -w`

{
echo plot ‘\’
for x in `seq 2 $COLS`
do
echo -n ‘ ‘ \”$FILE\” using 1:$x with lines ti \”`echo $HEAD | cut -d ‘ ‘ -f
$x`\”
if [ ! $x -eq $COLS ]
then
echo -n ‘,\’
fi
echo
done
} | gnuplot -persist
—-

That way you simply can click the “plot” button. gnuplot‘s window will pop up
and show the plot automagically.

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Re: gEDA-user: gEDA flow for chip design?

   On 01/15/2011 10:52 AM, Florian E. Teply wrote:
Hi folks,
   
I seem to recall that some guys here use gEDA for chip design. John
Doty comes to mind, but i think there are others too. I'd be
   interested
in the workflow as i will have to make up some clever test chips in
   the
next few years for PhD work and i'm not in the position to be able
to sell my grandma for a full-fledged cadence seat, nor am i willing
   to.
   
If reasonably possible, i'd want both simulation as well as
   generation
of production-ready data (GDS or OASIS files, preferably OASIS), but
have not the slightest idea on how to accomplish that or even if
   that's
possible with open source software, let alone from whithin gEDA.
   
Any suggestions?
   I have just made my first ASIC.  I used gEDA and LTSpice for the front
   end.  To get from gschem to Magic I wrote a gnetlist translator.  I did
   this by writing a small scheme back end that called into a standard C++
   program to do the heavy lifting.  Inside Magic I did the layout with a
   crude DRC based on the process I was using.  I extracted back out of
   Magic and reran the extract circuit in LTSpice as my LVS checker.  You
   can also run a simple LVS in Magic, but I did not find that entirely
   reliable.
   I then use a tool call KLayout and wrote scripts in ruby (the
   automation language for KLayout) to manipulate the layer data to get
   the resulting files I want.  Klayout can export to OASIS if you wish to
   use that format.  I myself used GDSII.  So to summarize my flow:
   gschem - gnetlist spice-oks - LTSpice (I use my own spice back end as
   well)
   For doing the designing, and then
   gschem - gnetlist magic - C++ code - Magic - KLayout - Ruby -
   GDSII
   to do the layout.  There is no need to use the C++ code if you are a
   whiz at scheme, but I really don't like LISP.  I am not anti functional
   languages, I just don't like the syntax of LISP.  I find it hard to
   maintain and read.
   Oliver


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Re: gEDA-user: gEDA flow for chip design?

   I looked at Toped quiet a bit and did not think it was as good as magic
   yet.  I like the idea behind it, and it is much more modern feeling
   that Magic, but it is still pretty immature.
   Oliver
 __

   From: Bob Paddock bob.padd...@gmail.com
   To: gEDA user mailing list geda-user@moria.seul.org
   Sent: Sat, January 15, 2011 9:45:05 AM
   Subject: Re: gEDA-user: gEDA flow for chip design?
Any suggestions?
   There is also Toped: [1]http://code.google.com/p/toped/
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References

   1. http://code.google.com/p/toped/
   2. mailto:geda-user@moria.seul.org
   3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user

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Re: gEDA-user: gEDA flow for chip design?


On 01/15/2011 07:39 PM, Oliver King-Smith wrote:

I extracted back out of
Magic and reran the extract circuit in LTSpice as my LVS checker.  You
can also run a simple LVS in Magic, but I did not find that entirely
reliable.


I'd like to hear more about this.  Are you meaning functional simulation to 
decide
on layout vs schematic match?  You're saying the extract
function of magic is fully reliable?

John


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Re: gEDA-user: gEDA flow for chip design?

I extracted back out of
   Magic and reran the extract circuit in LTSpice as my LVS checker.
   You
   can also run a simple LVS in Magic, but I did not find that
   entirely
   reliable.
   I'd like to hear more about this.  Are you meaning functional
   simulation to decide
   on layout vs schematic match?  You're saying the extract
   function of magic is fully reliable?
   I found the extraction from Magic to be very reliable, although getting
   the parasitics setup is hard.  You can easily remove clearly bad
   parasitics.  The LVS function in magic was a little buggy.  Tim Edwards
   has some examples from me, and he is pondering why they might be
   failing.  I reduced it to a pretty simple case.  It unfortunately also
   breaks the auto-router so you should use that with care.
   Oliver
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References

   1. mailto:geda-user@moria.seul.org
   2. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user


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Re: gEDA-user: gEDA flow for chip design?

2011-01-15 Thread Kai-Martin Knaak

Oliver King-Smith wrote:

  There is no need to use the C++ code if you are a whiz at 
 scheme, but I really don't like LISP.

You are not alone :-)

Would you  contribute the scheme glue script to the project? Maybe
it can even be added to the main distro of gnetlist. What do ye 
developers think?

---)kaimartin(---
-- 
Kai-Martin Knaak
Email: k...@familieknaak.de
Öffentlicher PGP-Schlüssel:
http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53



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Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]

2011-01-15 Thread al davis

On Saturday 15 January 2011, Kai-Martin Knaak wrote:
 I looked at lang_verilog_in.cc
 Unfortunately, my c++ is not fluent enough to read the code
 right away.   This is aggravated by the lack of comments on
 what the various code blocks do. Since I also don't know
 verilog by heart, the whole file looks more like a puzzle.
 Sorry, but this fruit is hanging too high for me. (You can
 call me programming coward)
 Is there a comprehensive specification, what gnucap expects
 to get from  the import plugin? If so, it might make a
 gschem import component a lot easier.

I started to write up things like that:
http://gnucap.org/dokuwiki/doku.php?id=gnucap:manual:tech:plugins

but then other things came up so I didn't have time to do more.

If somebody actually wants to help, wants to write a language 
plugin, I will work with you and complete the documentation.  
The interaction is a necessary part of completing the work.


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Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]

2011-01-15 Thread al davis

On Saturday 15 January 2011, Kai-Martin Knaak wrote:
 I don't see how this could possibly work. Both, gschem and
 altium  contain a graphical representation of the circuit.
 Unless I massively missed something, verilog is completely
 procedural. Graphics information would be lost during the
 process.

Yes .. you missed something.  Verilog has a structural part too, 
which is well documented, has a published standard, and 
completely adequate for this.


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Re: gEDA-user: gEDA flow for chip design?

2011-01-15 Thread Florian E. Teply

On Sat, 15 Jan 2011 17:44:33 -0600
John Griessen j...@ecosensory.com wrote:

 On 01/15/2011 10:52 AM, Florian E. Teply wrote:
i'd want both simulation as well as generation
  of production-ready data (GDS or OASIS files, preferably OASIS), but
  have not the slightest idea on how to accomplish that or even if
  that's possible with open source software, let alone from within
  gEDA.
 
  Any suggestions?
 
  Thanks,
  Florian
 
 
 I've done chip logic and layout with Cadence tools and it was at
 a small start up at first -- Cadence didn't care much about our
 success and we had to do all kinds of self starting to get a working
 flow even though it cost tons of money.  I've not done work with
 magic, http://opencircuitdesign.com/verilog/index.html , but from
 asking about it on its list, it can
 generate GDS2 output and you can extract capacitance from layout with
 it. If you sign up for its mail list you can ask Tim Edwards, the
 current maintainer and guru about feasibility for your project.
 
 John Doty mentioned his layout is hired out, but I can't remember
 what tools are used.  He's going to be your resource for simulation.
 
 What will you make?  some kind of sensor?
 
First, thanks to all for the contributions, they are much appreciated.

What exactly i will make isn't entirely sure yet. My plans are to
explore the degradation properties of some 0.25 micron and/or 0.13
micron BiCMOS processes of a small research fab in mixed radiation
environments.
But I'm still at a very early stage, mostly trying to digest the
literature in order to find a small niche where genuinely new insights
could be gained.
In the long run I plan to integrate the findings into specialized
models for simulation.

After all the radiation testing and modeling, one might consider this a
radiation sensor ;-)

Greetings,
Florian


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Re: gEDA-user: gEDA flow for chip design?