Re: gEDA-user: [PATCH] Drag without selection in gschem
On Tue, 2011-03-22 at 11:48 +1100, Geoff Swan wrote: I had a couple of issues with the patch process - I didn't bother checking which version I should have had (i'm using 1.7.0 20110116) but went and manually patched it myself. Its against git HEAD, which I had just previously pushed some clean-up to.. so it would probably not apply easily against anything else. Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: subcircuit definition and channelised design
On Tue, 2011-03-22 at 10:51 +1100, Geoff Swan wrote: Lots is possible, but I'm not sure how you would best go about it. gEDA's bus support is almost non-existent... it is just a graphical nicety, and relies upon named nets. (I vaguely recall that Altium buses can work like this too if you want) I haven't really used busses properly in Altium - as you described, I've primarily used them just as a graphical nicety while explicitly naming all the connected nets. There may have been a few cases where I named the bus and then connected nets were given the bus prefix, or something like that. But at the time I was just experimenting and didn't really need or find this sort of functionality added much value. (I imagine with a number of 32/64 bit busses something that removed the need to individually name nets would be handy though) In terms of the channelisation functionality my current thought is that I may be able to augment the gnetlist pcb backend to recognise something similar to a bus notation and recognise when a symbol/subcircuit needs to be replicated. (btw - I haven't yet started looking through the gnetlist backend sourcode or doco so if this sounds like something impossible - feel free to give me a heads up :) It might be possible, but I'm not as familiar with gnetlist as with other parts of the suite. I mostly do rendering / UI stuff (in gschem and PCB). I vaguely recall that the verilog backend does something with nets named something[12-9] (or whatever the verilog bus syntax is), but that just maps onto the data-types used when producing the netlist, not the structure of the schematic. I'm fairly sure you cannot dynamically instantiate channels within gnetlist though (short of implementing a lot of hackery in the netlist backend). When I've done channels in the past, I've kept them on separate schematic pages, then used a makefile and some simple bash / sed / awk scripting to increment component numbers and spit out each channel as a new page. I would then create a symbol which represents all the channels (in a hierarchical design), then wire that into the schematic. If we supported buses properly, this could even be done with bus pins - but we don't at present. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB question
I layed a board out and then decided to make changes. I didn't want to loose all of my work so in pcb I saved the layout as another name. I now mistakenly deleted an inductor in the layout and need to re-gsch2pcb the design. Do I just do gsch2pcb new-name to get the new-name.pcb file? Thanks ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB question
If you used a project file with gsch2pcb, you can make a copy of the gsch2pcb project file with the new name in it. Otherwise, you'll probably need to create such a file, as the pcb and sch file names won't match any more. (note: this isn't a pcb question, it's a gsch2pcb question) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB question
Yes, that's what I meant. I should have thought about it better before I asked. So if I say in the project file 'output-name new-name' It will know to check the new-name.pcb file to see what components are missing and will give me a knew file with the layout data to load into the layout buffer? Not trying to be wise but is classifying a question properly critical here? On Tue, Mar 22, 2011 at 7:14 PM, DJ Delorie [1]d...@delorie.com wrote: If you used a project file with gsch2pcb, you can make a copy of the gsch2pcb project file with the new name in it. Otherwise, you'll probably need to create such a file, as the pcb and sch file names won't match any more. (note: this isn't a pcb question, it's a gsch2pcb question) ___ geda-user mailing list [2]geda-user@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:d...@delorie.com 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB question
Rob Butts r.but...@gmail.com writes: Yes, that's what I meant. I should have thought about it better before I asked. So if I say in the project file 'output-name new-name' It will know to check the new-name.pcb file to see what components are missing and will give me a knew file with the layout data to load into the layout buffer? Not trying to be wise but is classifying a question properly critical here? It helps, to understand the answer :-) I do recommend a vcs (subversion, git) for pcb projects. No need to rename layout files, then. -- Stephan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB question
Yes, that's what I meant. I should have thought about it better before I asked. So if I say in the project file 'output-name new-name' It will know to check the new-name.pcb file to see what components are missing and will give me a knew file with the layout data to load into the layout buffer? Yes. For completeness, solving this problem with the new importer involves setting an attribute in the new layout, indicating which schematic it's importing from. By default, it chooses a schematic with the same name, but that default doesn't work when you rename the *.pcb file. Not trying to be wise but is classifying a question properly critical here? If you want the right people to *read* the question, yes. gsch2pcb was not written by the pcb developers. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
