Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Can you be a bit more specific, please?
What aspects did you have to tune? What were road blocks that needed to
be removed? Did yo use any other helper software?
I'd like to compile this info to a page in the wiki. So next time we can
build upon your experience.
Hello,
first you have to install MinGW compiler and MinSYS environment to run the
script which builds PCB for Windows. It is about 20 or more different packages.
I had to do that with iterations - run the script, see, what does not work,
install another package and so on.
You will need GLIB+GTK+plenty of other packages as well. Not only those listed
in README. And GD library as well.
Then you need to arrange GLIB/GTK headers and libs in a special way because
Makefiles contain just glib-2.0 include and not all proper include directories.
The same applies (as far as I remember) for linking process.
Then, after your makefiles are successfully generated, you will need (or maybe
not, but I needed) the script which removes white spaces at ends of all lines
in all makefiles. Here it is:
find ./ -type f -name Makefile | while read FILENAME; do cat ${FILENAME}| sed
-e 's/ $//g' ${FILENAME}_new; mv ${FILENAME}_new ${FILENAME}; done
So far so good. For installer, I just included DLLs only as there is no need to
have plenty of unnecessary stuff like headers, EXEs etc from GTK and GD
distributions.
This complete building process took me about 10 hours. But, as you can see,
headline is PCB can be built with MinGW.
If you try to do it by yourselves, check files in pcb-HEAD.zip . They can help
you when you get stuck.
If somebody requires GTK sources - let download them directly from
http://gtk.org/ I used GTK etc. libs unmodified.
I have seen no bug reports so far. Does it mean that even Import schematic
works for all of you ? Or nobody have tried PCB on Windows ?
Vaclav
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Re: gEDA-user: Where is pcb-20100929 for Win32 ?
If somebody requires GTK sources - let download them directly from http://gtk.org/ I used GTK etc. libs unmodified. Unfortunately, the GPL does not allow this. If we're shipping GTK dlls, we must offer the GTK sources ourselves. Do you have a list of the various source tarballs that went into the pcb installer's files, so that Kai and I can download them? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
If somebody requires GTK sources - let download them directly from http://gtk.org/ I used GTK etc. libs unmodified. Unfortunately, the GPL does not allow this. If we're shipping GTK dlls, we must offer the GTK sources ourselves. Do you have a list of the various source tarballs that went into the pcb installer's files, so that Kai and I can download them? Unfortunately I don't. I did not have fresh Minsys/MinGW installation. So I still did not have to download all packages. Next time I will write every step of the building process. I am sorry. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
On Tue, May 10, 2011 at 2:18 AM, DJ Delorie d...@delorie.com wrote: If somebody requires GTK sources - let download them directly from http://gtk.org/ I used GTK etc. libs unmodified. Unfortunately, the GPL does not allow this. If we're shipping GTK dlls, we must offer the GTK sources ourselves. Why are individuals who are trying to help the project being held to a higher standard that the projects own download page? http://pcb.gpleda.org/ 's download link does not contain GTK sources, sources of compilers or sources for the Windows operating system. Doesn't PCB's source code actually predate the GPL? When and who put it under GPL? All of this legal crap just takes the fun and desire out of working on the project. Do you have a list of the various source tarballs that went into the pcb installer's files, so that Kai and I can download them? Using the 'minipack' build system takes care of downloading the sources so they would be available to upload to be GPL compliant. It is also a lot less painful that what Vacla just described. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Bob Paddock wrote: Why are individuals who are trying to help the project being held to a higher standard that the projects own download page? I'll check, whether this legal fine tuning actually applies to me. After all, this is Germany here. We are governed by civil law as opposed to common law. In addition, the intellectual property hype does not seem to be as heated here in Cis-Pondia. Anyway, to be extra secure, I may offer GTK sources for download, too. Using the 'minipack' build system takes care of downloading the sources so they would be available to upload to be GPL compliant. If there were a ready to use installer, or tar ball, or whatever, I'd be happy to host this, too. It is not just for the benefit of others, but to provide a decent standing for here in the institute. The majority of PhDs and masters have that other OS installed. ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Vaclav Peroutka wrote: I have seen no bug reports so far. Does it mean that even Import schematic works for all of you ? Or nobody have tried PCB on Windows ? It means, that I don't have a current version of geda available for windows. So, no gschem, or gnetlist available, yet. How did you succeed to compile geda for windows? ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
How did you succeed to compile geda for windows? I've used 'minipack'. It builds those too, not just PCB. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Bob Paddock graceindustr...@gmail.com writes: On Tue, May 10, 2011 at 2:18 AM, DJ Delorie d...@delorie.com wrote: If somebody requires GTK sources - let download them directly from http://gtk.org/ I used GTK etc. libs unmodified. Unfortunately, the GPL does not allow this. If we're shipping GTK dlls, we must offer the GTK sources ourselves. Why are individuals who are trying to help the project being held to a higher standard that the projects own download page? http://pcb.gpleda.org/ 's download link does not contain GTK sources, sources of compilers or sources for the Windows operating system. Neither did I find any libgtk executables, that would require to provide corresponding sources. -- Stephan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
On 05/10/2011 12:50 PM, Bob Paddock wrote: Why are individuals who are trying to help the project being held to a higher standard that the projects own download page? Because they are not. anybody who distributes binaries must provide the corresponding source. http://pcb.gpleda.org/ 's download link does not contain GTK sources, sources of compilers or sources for the Windows operating system. http://pcb.gpleda.org doesn't contan any binaries. Doesn't PCB's source code actually predate the GPL? No, it doesn't. When and who put it under GPL? Its original author, Thomas Nau, in the previous millenium; every new piece of code since then was put under the same license, and no contributor suggested anything different. All of this legal crap just takes the fun and desire out of working on the project. It also ensures that my contribution won't be used to mistreat you. Best wishes, Ineiev ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Why are individuals who are trying to help the project being held to a higher standard that the projects own download page? They are not. Why do you think I'm trying to fix this problem? I want to be able to auto-build an installer *and* source set for the official windows releases, so we can avoid having to make anyone else do it, and so that we're in full compliance at all times. http://pcb.gpleda.org/ 's download link does not contain GTK sources, sources of compilers or sources for the Windows operating system. Please read the GPL so you understand what needs to be included, and what doesn't. The sources need NOT include anything that's a normal part of the OS, development kit, or included runtime, UNLESS YOU DISTRIBUTE THAT WITH YOUR BINARY. Doesn't PCB's source code actually predate the GPL? The issues is not the PCB license. The issue is the GTK license (and other libraries we use). If we distribute the GTK dll, we must distribute the GTK sources. If we had a Win32api native pcb, we would not need to distribute the Win32api sources, because the're a normal part of the OS. If we forced people to install MinGW to get the GTK dlls, we would not need to distribute the GTK sources. All of this legal crap just takes the fun and desire out of working on the project. Which is why I'm trying to get to the point where I can do it myself, so that the unfun onus is on me (or better, on some script somewhere ;) Using the 'minipack' build system takes care of downloading the sources so they would be available to upload to be GPL compliant. I think everyone agrees that's the way to go. I just didn't have much luck with minipack last time I tried. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Refresh all polygons
Sometimes when moving polygons, PCB gets confused and leaves the holes of old objects. Is there a refresh polygons option, which would recalculate all the polygons? At present, I have to move every polygon in my design a tiny bit, then move it back, to get it to recalculate them; this takes time, as I have many polygons in my complex designs. Thanks! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Refresh all polygons
Make sure you have my patch to src/insert.c that calls ClearFromPolygon() and RestoreToPolygon(). Failing that, Peter says calling InitClip() for every polygon will recompute them, but at the moment, there's no way to do that from the GUI. In theory, you should never have to. If you can come up with a small self-contained test case, file a bug so we can fix it. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Am 10.05.2011 um 19:39 schrieb DJ Delorie: If we distribute the GTK dll, we must distribute the GTK sources. Not if you use the sources unmodified, because they're distributed elsewhere, then. Markus - - - - - - - - - - - - - - - - - - - Dipl. Ing. (FH) Markus Hitter http://www.jump-ing.de/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Not if you use the sources unmodified, because they're distributed elsewhere, then. The GPL doesn't let you rely on someone else's source distribution, unless you have an arrangement with them to do so. Yes, I've been down this road with the FSF many times... Consider, for example, if the someone else's site decides to remove their copies of everything (happens all the times - it's called upgrading :). Now your binary distribution has no corresponding sources. So the FSF's rule is same site, same method - i.e. http://*.foo for binaries, http://*.foo for sources, etc. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
http://pcb.gpleda.org/ 's download link does not contain GTK sources, sources of compilers or sources for the Windows operating system. Please read the GPL so you understand what needs to be included, and what doesn't. The sources need NOT include anything that's a normal part of the OS, development kit, or included runtime, UNLESS YOU DISTRIBUTE THAT WITH YOUR BINARY. I've read it many times, due to its ambiguity, case in point: The issues is not the PCB license. The issue is the GTK license (and other libraries we use). If we distribute the GTK dll, we must distribute the GTK sources. Is GTK not part of the development kit? If we forced people to install MinGW to get the GTK dlls, we would not need to distribute the GTK sources. I don't follow, GTK dll's are not part of MinGW. I think everyone agrees that's the way to go. I just didn't have much luck with minipack last time I tried. Give it a try again, as I think Ceasar fixed several issues, that I reported to him when I had trouble getting it going. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
part of the OS, development kit, or included runtime, UNLESS YOU DISTRIBUTE THAT WITH YOUR BINARY. I've read it many times, due to its ambiguity, case in point: The issues is not the PCB license. The issue is the GTK license (and other libraries we use). If we distribute the GTK dll, we must distribute the GTK sources. Is GTK not part of the development kit? Doesn't matter, we ship GTK dlls, we're responsible for providing those sources. That's why the emphasis on unless you distribute If we didn't ship the GTK dlls, we wouldn't have to distribute the sources[1]. But, we *do* ship the GTK dlls, so we *do* have to distribute the sources[2]. [1] because they're part of the development kit and/or OS, in a way. [2] because of the unless you include it exception. Note that [1] is the ambiguous part, due to the word common in the GPL, but [2] is not ambiguous at all. If we forced people to install MinGW to get the GTK dlls, we would not need to distribute the GTK sources. I don't follow, GTK dll's are not part of MinGW. ... or somehow install GTK dlls on their own, then ;-) Give it a try again, as I think Ceasar fixed several issues, that I reported to him when I had trouble getting it going. Yup. *time* is my other enemy :-P ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Refresh all polygons
Thomas Oldbury wrote: Is there a refresh polygons option, which would recalculate all the polygons? No. My work-around: Save the layout and do file - revert On reload, the polygons are freshly calculated. ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Bob Paddock wrote: I think everyone agrees that's the way to go. I just didn't have much luck with minipack last time I tried. Give it a try again, as I think Ceasar fixed several issues, that I reported to him when I had trouble getting it going. Oh, finally I realize, that minipack is a crosscompile approach and I should be able to compile it on my Debian desktop. So, I am am giving minipack a try right now. Thankfully, the instructions Cesar gave in 2008 are still valid: http://www.mail-archive.com/geda-dev@moria.seul.org/msg06312.html At the moment, the build script downloads cairo from cairographics.org at a screaming 20 kB/s ;-) Seems like the process will take some time. I'll let it run over night. Will report my mileage. ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Kai-Martin Knaak wrote: At the moment, the build script downloads cairo from cairographics.org at a screaming 20 kB/s ;-) Seems like the process will take some time. I'll let it run over night. Will report my mileage. Hmm. The script got stuck at the download of libgd. The site www.libgd.org seems to be down. The address resolves to 213.251.181.15 which does not even respond to ping :-| ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Important gsch2pcb fixes in git HEAD
Hi Everyone, Anyone using git HEAD gEDA fetched after March 8th should fetch again from git and rebuild. There is an important fix for gsch2pcb which may prevent random crashes, failures and generally bad behaviour which has been present in the git HEAD version since the commit after a7a0bd24515bef8bcad69ae9321b4a8e5cbba738 (The above commit is the one which has the mistake, but it was not enabled until the commit after). Best regards, Peter Clifton ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Refresh all polygons
On May 10 2011, DJ Delorie wrote: Make sure you have my patch to src/insert.c that calls ClearFromPolygon() and RestoreToPolygon(). Failing that, Peter says calling InitClip() for every polygon will recompute them, but at the moment, there's no way to do that from the GUI. In theory, you should never have to. If you can come up with a small self-contained test case, file a bug so we can fix it. In addition to the patch DJ mentioned, the one I think you're more likely to be hitting (depending on what version of PCB you have), is the one fixed by this: commit 79417191949173c16579554dc8f8d5b9cbb22b3a Author: Peter Clifton pc...@cam.ac.uk Date: Fri Apr 22 18:38:20 2011 +0100 Fix geometry errors caused by commit 2d8dc8a3a3a55158b4e6278dd9f40588e4111c2d This fixes up problems from the following commit: [PATCH] fix bug 2793480 (vias/arcs-to-polygon clearances) frac_circle(): introduce radius_adjustment factor to make the polygon outline the arc rather than connet points on the arc ArcPolyNoIntersect(): compute number of segments so that polygon diverges from the arc no more than 0.02 of required thickness; adjust outer arc radius like in frac_circle() The object bounding boxes for arcs, vias, lines and rounded pads which determine the maximum area affected by that object were no longer correct, leading to artaefacts when doing incremental polygon processing. It also lead to missing fragments in (the non-curved + and x type thermals). These are also fixed up by this patch. Could you elaborate as to what PCB version (git SHA1 if you built from git), and what symptoms you're seeing (perhaps with a screen-shot of the problem). It is far more important to us that polygons Just work, rather than adding kludges in to let the user force recalculating them. This said, I know where are some very rare cases with degenerate or complex curved geometry where PCB's polygon routines do get very confused, and will need to be forced to recalculate. (If necessary, I use the file save, file revert method as Kai-Martin suggested). Best regards, Peter Clifton ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Refresh all polygons
Here is one way to break it that works 100% of the time: 1. Highlight only one layer and the top side components. The layer must have a plane or large polygon area for the bug to be easily visible. 2. Move that layer and the components. 3. Hit Undo or U, notice polygon has holes where they used to be, in the wrong positions. 4. Save-Revert refreshes the PCB and works fine. I have no idea about git, sorry. All I know is: This is PCB, an interactive printed circuit board editor version 1.99z Compiled on May 2 2011 at 15:36:55 The release I used was the most recent available on the 2nd May at about 15:36 GMT. However I noticed this bug in older versions of PCB. It has been around for a while, it just didn't really bother me until recent when I started working on a very complex PCB design with many polygons. On 10 May 2011 20:58, Peter C.J. Clifton [1]pc...@cam.ac.uk wrote: On May 10 2011, DJ Delorie wrote: Make sure you have my patch to src/insert.c that calls ClearFromPolygon() and RestoreToPolygon(). Failing that, Peter says calling InitClip() for every polygon will recompute them, but at the moment, there's no way to do that from the GUI. In theory, you should never have to. If you can come up with a small self-contained test case, file a bug so we can fix it. In addition to the patch DJ mentioned, the one I think you're more likely to be hitting (depending on what version of PCB you have), is the one fixed by this: commit 79417191949173c16579554dc8f8d5b9cbb22b3a Author: Peter Clifton [2]pc...@cam.ac.uk Date: Fri Apr 22 18:38:20 2011 +0100 Fix geometry errors caused by commit 2d8dc8a3a3a55158b4e6278dd9f40588e4111c2d This fixes up problems from the following commit: [PATCH] fix bug 2793480 (vias/arcs-to-polygon clearances) frac_circle(): introduce radius_adjustment factor to make the polygon outline the arc rather than connet points on the arc ArcPolyNoIntersect(): compute number of segments so that polygon diverges from the arc no more than 0.02 of required thickness; adjust outer arc radius like in frac_circle() The object bounding boxes for arcs, vias, lines and rounded pads which determine the maximum area affected by that object were no longer correct, leading to artaefacts when doing incremental polygon processing. It also lead to missing fragments in (the non-curved + and x type thermals). These are also fixed up by this patch. Could you elaborate as to what PCB version (git SHA1 if you built from git), and what symptoms you're seeing (perhaps with a screen-shot of the problem). It is far more important to us that polygons Just work, rather than adding kludges in to let the user force recalculating them. This said, I know where are some very rare cases with degenerate or complex curved geometry where PCB's polygon routines do get very confused, and will need to be forced to recalculate. (If necessary, I use the file save, file revert method as Kai-Martin suggested). Best regards, Peter Clifton ___ geda-user mailing list [3]geda-user@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:pc...@cam.ac.uk 2. mailto:pc...@cam.ac.uk 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb: strategies for 2-layer polygon planes? (chopped up polygons...)
I tried to use a nice big ground plane floods on my 2-layer PCB design to provide a low impedance ground and to implement the reference design for the RF IC (Atmel AT86RF231) and PCB antenna designs I was using. I know you can't have a perfect ground plane on a 2-layer board when you are routing tracks on both layers, but I figure that if there are some islands without ground plane, that's fine. Perhaps my concept is wrong. Anyway, here's the process I used: 1. Import schematic into pcb, disperse components. 2. Lay out major components (radio transceiver IC, antenna, data connector). 3. Create ground plane rectangles on both top and bottom layer. 4. Route tracks. Now after a while of routing tracks, there were so many tracks that my ground plane polygons were chopped to bits and pcb started drawing only the left half of the polygon, for instance. This obviously created problems since nets that were already successfully routed got broken. Furthermore, I couldn't edit my ground plane polygon easily since pcb doesn't draw any indication of where the vertices are, and the polygon itself was half missing. It looked like the logical thing for pcb to do would be to draw two halves of the polygon. In fact it looked like the missing half was the larger half, so it seemed a really bad choice. I tried to patch up the missing parts with more rectangles, but it was not great. It was such a mess that I had to delete my ground planes and start over. The second time, I didn't create one large rectangle, but instead inserted 3 or 4 smaller rectangles on both top and bottom layers in specific areas where I needed the ground plane. This worked better but seems cumbersome, especially in the early layout when you don't have components and tracks already figured out, so you don't know where the ground plane polygons might fit. Does anyone have any strategies or tips for general design of ground planes in 2-layer PCBs? Do you do a ground flood, or do you remove all extra copper? Regards, Colin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Kai-Martin Knaak wrote: The script got stuck at the download of libgd. The site www.libgd.org seems to be down. The address resolves to 213.251.181.15 which does not even respond to ping :-| The website is still down. Can someone mail me the required gd sources? The script seems to ask for version 2.0.35 The debian repositories contain v2.0.36. Any chance, that this will work? ---)kaimartin(--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb: Track routing strategies and tips
As a rather inexperienced PCB designer, I find that I have to throw away two or three layouts until I get one that is usable--and still not entirely satisfactory. I always end up with such a mess of traces that I know I need better organization and a method to the madness. But I am a newb with little knowledge so I fall back on trial-and-error. Does anyone have any tips on how to plan a layout for easy and clean track routing? In particular for 2-layer boards. One strategy that I have seen and recently tried is to use the top layer for all horizontal trace runs and the bottom layer for all vertical trace runs, or vice-versa. Do you ever use the pcb autorouter or do you always route by hand? Do you ever study other people's PCB designs to learn from them? I think you could find both good and bad examples: things to emulate and things to avoid yourself. Thanks for any suggestions. There are some incredibly experienced and talented electronic designers on the list and I'd love to learn anything I can from you all. Regards, Colin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
On 05/10/2011 04:28 PM, Kai-Martin Knaak wrote: Hmm. The script got stuck at the download of libgd. The site www.libgd.org seems to be down. The address resolves to 213.251.181.15 which does not even respond to ping :-| This site has been down for quite a while. I have just found the location of a copy from Slackware and updated the recipe accordingly. Please pull minipack from git and try again. Regards, Cesar ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: strategies for 2-layer polygon planes? (chopped up polygons...)
Colin D Bennett wrote: Does anyone have any strategies or tips for general design of ground planes in 2-layer PCBs? Do you do a ground flood, or do you remove all extra copper? I usually route everything, including ground connections with ordinary tracks. Then I select all ground connections and set their join flag with the setflag() action and draw a large polygon. Sometimes I need to draw additional rectangles because the dicer removed some parts. ---)kaimartin(--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Track routing strategies and tips
Colin D Bennett wrote: Does anyone have any tips on how to plan a layout for easy and clean track routing? In particular for 2-layer boards. Put extra care into component placement. IMHO, placement is more critical to the design than routing. One strategy that I have seen and recently tried is to use the top layer for all horizontal trace runs and the bottom layer for all vertical trace runs, or vice-versa. Yep. This is a good default. It avoids road blocks by tracks on both sides. Do you ever use the pcb autorouter Rarely. or do you always route by hand? Mostly. Do you ever study other people's PCB designs to learn from them? Sometimes I look with awe at computer motherboards ;-) ---)kaimartin(--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Cesar Strauss wrote: I have just found the location of a copy from Slackware and updated the recipe accordingly. Please pull minipack from git and try again. Thanks! I pulled the changes. Now gd-2.0.35.tar.bz2 loads fine :-) currently, the build progresses with a whole bunch of warnings for the compile of gettext (500 lines). Should I post the dump? ---)kaimartin(--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Track routing strategies and tips
Colin D Bennett wrote: As a rather inexperienced PCB designer, I find that I have to throw away two or three layouts until I get one that is usable--and still not entirely satisfactory. I always end up with such a mess of traces that I know I need better organization and a method to the madness. But I am a newb with little knowledge so I fall back on trial-and-error. I am also new to routing my own stuff but have a bunch of experience telling others how to do it for me (day job ;) On a prior job, the layout house did all auto-routes. They'd start several jobs with different router restrictions, allow them to route for a while, then pick one, and optimize it - probably by hand. Yes, starting over is common. Kai-Martin posted that placement is more important than routing. I'd say they are equally important. The best layout guy in the world can't fix a lousy placement. Bogus layout guys throw more layers at the problem. So yeah, take the time to plan it out before routing. Does anyone have any tips on how to plan a layout for easy and clean track routing? In particular for 2-layer boards. No substitute for experience here. But, partitioning the design by type may help : analog, digital, low-speed, high-speed. Try to think beyond blindly connecting the parts. Sometimes swapping gates, adding parts or other strategies become clear as you route. This is a huge benefit when you route your own board. Layout guys just connect the pieces together. One strategy that I have seen and recently tried is to use the top layer for all horizontal trace runs and the bottom layer for all vertical trace runs, or vice-versa. 2-layer is tough. You also have to account for power and ground. The parts themselves also crowd routing area. 2-layer is not particularly suitable for high-speed anything. Seems good for power supply design, and some audio work (I've seen a lot of audio ref boards on 2 layer). You can make good designs with 2-layer, just is more work. Cost difference to 4-layer is not bad. Yes X-Y routing is the way to go to avoid blocking. Works great for digital stuff. Do you ever use the pcb autorouter or do you always route by hand? I have yet to make the auto router work - but haven't really tried very hard. Hand routing is my preference but it takes longer. Do you ever study other people's PCB designs to learn from them? Yeah, a lot. You will find good and bad. There's a whole world of opinion out there - and you know what they say about opinions :) SI-LIST is a great place to exchange ideas on layout. Several industry experts frequently post. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: crosscompile for windows with minipack
As mentioned in the thread Where is pcb-20100929 for Win32 ? I tried to go the minipack way to crosscompile geda and PCB for windows. There were warnings at compile time -- about 2200 lines. The build script declared itself successful. Unfortunately, the binaries fail when started with wine. They fail with different symptoms: -gnetlist kmk@bibo:/tmp$ wine /usr/local/src/pcb/pcb-for-windows/minipack/result/bin/gsch2pcb.exe pidpeltier.g2p gsch2pcb: gnetlist command (gnetlist -q -g gsch2pcb -o pidpeltier.pcb -m gnet-gsch2pcb- tmp.scm pidpeltier.sch) failed. At least gnetlist 20030901 is required for m4-xxx options. --PCB kmk@bibo:/usr/local/src/pcb/pcb-for-windows/minipack/result/bin$ wine ./pcb.exe (pcb.exe:8): GLib-WARNING **: Passing a non-NULL package to g_win32_get_package_installation_directory() is deprecated and it is ignored. Share installation path is Z:\usr\local\src\pcb\pcb-for- windows\minipack\result\share\pcb (pcb.exe:8): GLib-WARNING **: Passing a non-NULL package to g_win32_get_package_installation_directory() is deprecated and it is ignored. wine: Unhandled page fault on read access to 0x at address 0x7ec3a74a (thread 0009), starting debugger... --gschem kmk@bibo:/usr/local/src/pcb/pcb-for-windows/minipack/result/bin$ wine ./gschem.exe wine: Unhandled page fault on read access to 0x at address 0xf7566110 (thread 0009), starting debugger... Unhandled exception: page fault on read access to 0x in 32-bit code (0xf7566110). Register dump: CS:0023 SS:002b DS:002b ES:002b FS:0063 GS:006b EIP:f7566110 ESP:0066fc18 EBP:0066fc38 EFLAGS:00010246( - 00 -RIZP1) EAX: EBX:7bc89444 ECX: EDX: ESI: EDI: Stack dump: 0x0066fc18: 7bc68b4d 0066fc48 0x0066fc28: 0002 7bc68b39 0066fe68 0x0066fc38: 0066fc68 6bfcf498 001ed5c0 0x0066fc48: 66304430 0066fe68 00132a48 0001 0x0066fc58: 0066fc78 0066fe68 00132a48 0001 0x0066fc68: 0066fc78 6bfcf4b9 Backtrace: =1 0xf7566110 in libc.so.6 (+0x74110) (0x0066fc38) 2 0x6bfcf498 in libguile-17 (+0x4f498) (0x0066fc68) 3 0x6bfcf4b9 in libguile-17 (+0x4f4b9) (0x0066fc78) 4 0x66305913 in libgeda-38 (+0x5913) (0x0066fc88) 5 0x66306daa in libgeda-38 (+0x6daa) (0x0066fc98) 6 0x00408a02 in gschem (+0x8a02) (0x0066fcd8) 7 0x6bfad09a in libguile-17 (+0x2d09a) (0x0066fcf8) 8 0x6bf84af2 in libguile-17 (+0x4af2) (0x0066fd08) 9 0x6bfe84f2 in libguile-17 (+0x684f2) (0x0066fd88) 10 0x6bf84f26 in libguile-17 (+0x4f26) (0x0066fdd8) 11 0x6bf84fc1 in libguile-17 (+0x4fc1) (0x0066fe08) 12 0x6bfe6c5b in libguile-17 (+0x66c5b) (0x0066fe38) 13 0x6bfe6ca1 in libguile-17 (+0x66ca1) (0x0066fe58) 14 0x6bfad041 in libguile-17 (+0x2d041) (0x0066fe78) 15 0x004088bb in gschem (+0x88bb) (0x0066fea8) 16 0x004010a7 in gschem (+0x10a7) (0x0066fee8) 17 0x00401143 in gschem (+0x1143) (0x0066ff08) 18 0x7b8783a8 in kernel32 (+0x583a8) (0x0066ffe8) 0xf7566110: pcmpeqb 0x0(%esi),%mm0 Modules: Module Address Debug info Name (117 modules) PE24- 2ba000 Deferredlibpixman-1-0 PE40- 461000 Export gschem PE67- a6b000 Deferredlibgtk-win32-2.0-0 PE 61a0-61a34000 Deferredlibpng14-14 PE 61cc-61cda000 Deferredlibintl-8 PE 6294-6296b000 Deferredlibatk-1.0-0 PE 63a4-63a87000 Deferredlibgobject-2.0-0 PE 650c-6515 Deferredlibfreetype-6 PE 6534-65384000 Deferredlibgdk_pixbuf-2.0-0 PE 6558-655cd000 Deferredlibpango-1.0-0 PE 65c4-65c52000 Deferredlibgthread-2.0-0 PE 6600-660f1000 Deferredlibiconv-2 PE 6630-66336000 Export libgeda-38 PE 6660-5000 Deferredlibtiff-3 PE 685c-686cc000 Deferredlibglib-2.0-0 PE 6890-68949000 Deferredlibjpeg-7 PE 68a8-68ace000 Deferredlibgmp-3 PE 68dc-68e7 Deferredlibcairo-2 PE 6b28-6b29a000 Deferredlibpangowin32-1.0-0 PE 6bf8-6c03a000 Export libguile-17 PE 6c34-6c3f1000 Deferredlibgdk-win32-2.0-0 PE 6d48-6d494000 Deferredlibltdl-7 PE 6d4c-6d4d5000 Deferredlibpangocairo-1.0-0 PE 6d58-6d60a000 Deferredlibgio-2.0-0 PE 6dd0-6dd11000 Deferredlibgmodule-2.0-0 PE 6e8c-6e8df000 Deferredlibz PE 7104-71059000 Deferredlibgnurx-0 ELF 7b80-7b939000 Export kernel32elf \-PE 7b82-7b939000 \
Re: gEDA-user: pcb: Track routing strategies and tips
On Tue, May 10, 2011 at 04:26:06PM -0700, Colin D Bennett wrote: As a rather inexperienced PCB designer, I find that I have to throw away two or three layouts until I get one that is usable--and still not entirely satisfactory. I always end up with such a mess of traces that I know I need better organization and a method to the madness. But I am a newb with little knowledge so I fall back on trial-and-error. Does anyone have any tips on how to plan a layout for easy and clean track routing? In particular for 2-layer boards. As a hobbyist, I work mainly with 2-layer boards, since those are what I can make at home. This means that I also minimize the number of vias I use, which presents its own challenges. My latest pcb is here: http://wpsoftware.net/andrew/stereo_bike.pcb This was also interesting because I was space-constrained (the board needs to fit into a small cast iron box on my bicycle) and since this is a high-powered audio application, I needed large power traces and a lot of heat sink. As has been said, experience is a huge factor in laying out boards. Don't be afraid to rotate things 180 and try odd ways of connecting components. Using source control on PCBs is a good idea. Do things locally (in my case, the power supply, main amp and guitar pre-amp were all laid out separately) and worry about connecting them later. Figure out how to avoid intersections before spacing things out. If you get stuck, it can help to decide ``I'll just use a jumper wire here'' and move on. Often problems are easier to solve once more of the board is in place. One strategy that I have seen and recently tried is to use the top layer for all horizontal trace runs and the bottom layer for all vertical trace runs, or vice-versa. Do you ever use the pcb autorouter or do you always route by hand? The autorouter uses too much space in my experience and isn't good at deciding what trace widths to use. Do you ever study other people's PCB designs to learn from them? I think you could find both good and bad examples: things to emulate and things to avoid yourself. Yes :) fortunately, in my line of work I am also often able to ask the designers of said boards what they were thinking. Thanks for any suggestions. There are some incredibly experienced and talented electronic designers on the list and I'd love to learn anything I can from you all. -- Andrew Poelstra Email: asp11 at sfu.ca OR apoelstra at wpsoftware.net Web: http://www.wpsoftware.net/andrew/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
