gEDA-user: PCBs using desktop inkjet
When will gEDA start providing support for printed circuits? :) Tarun Modified ink printer churns out electronic circuits * 18:24 18 April 2007 * NewScientist.com news service * Tom Simonite A desktop printer loaded with a silver salt solution and vitamin C has been used to produce electronic circuits. The UK researchers behind the feat say their experimental device could pave the way for safer and cheaper electronics manufacturing. Being able to print out electronic components and whole circuit boards could provide an alternative to current manufacturing techniques, which are energy intensive and environmentally unfriendly. Printing conductive polymer ink (see Goodbye wires and silicon, hello plastic chips), or pastes containing graphite or metal particles are two existing options. But researchers at Leeds University in the UK wanted to avoid the solvents needed for these processes. PhD student Seyed Bidoki loaded a standard Hewlett Packard ink-jet printer with a solution of metal salts and water. After a pattern is printed using the solution, a chemical known as a reducing agent is then printed over the top to make solid silver form. We wanted to be able to use a totally water-soluble base, explains team member and chemist Matthew Clark. That allows for much more environmentally friendly processes. Metal ink Bidoki loaded two separate chambers in the printer's cartridge, which normally contain different ink, with the metal solution and the reducing agent. Using silver nitrate solution as the metal ink and ascorbic acid (vitamin C) as the reducing agent proved the most successful combination. He then programmed the printer to produce a variety of circuits and radio antennas on different surfaces including paper, cotton and acetate, all of which were placed in the printer like a normal sheet of paper. One test involved patterning an antenna like that used in a mobile phone on transparent film, says Clark. It was possible to bend it almost in half without any loss of conductivity. After a circuit is printed using silver nitrate, vitamin C is overlaid a few minutes later. Water can then be used to wash away other products, leaving the silver behind. Scanning electron microscope images reveal a rough surface of silver nanoparticles. Join the dots Printing the same pattern two or three times improves conductivity because it increases the number of contacts between silver nanoparticles. Desktop printers make images from tiny dots of ink that do not overlap, but bleed slightly into each other, explains Clark: In future, we'd like to use an industrial jet printer that can so we'll need fewer passes. Graham Martin at the University of Cambridge, UK, agrees that ink-jet technology could make new kinds of devices possible. But he says competing with existing technology could be difficult: This concept are often simple but there are many challenges to meet. Creating a low enough resistance to match current standards is one of them. But ink-jet printing definitely has a future, he adds. Currently, circuit boards and other components are made by etching the desired design out from a layer of metal, which is an energy intensive process. Printing is an additive, not subtractive process, making it more environmentally effective, says Martin. Journal reference: Journal of Micromechanics and Microengineering (DOI:10.1088/0960-1317/17/5/017) http://www.newscientisttech.com/article/dn11632?DCMP=NLC-nletternsref=dn11632 -- attachment: InkjetPCBs.jpg ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A suggestion about the stuff on gedasymbols
Gedasymbols is primarily a contributor place, not a replacement for the shipped libraries. Symbols which have proven themselves, and are popular, should be migrated from gedasymbols to the official libraries. In any case I'll elaborate what I was thinking. I was thinking that open-source components are like open-source software, and we can pick up a repository and use its components, with a caveat emptor. The danger of picking up a buggy symbol or footprint is not reduced or increased by my approach compared to the current pick-one-at-a-time interface. My approach just makes it easier for a user to download all the components in one shot and make them all accessible to gschem and pcb. The caveat emptor will remain. Today, even the downloading the elements takes time and effort. I was thinking we could do the following: 1. We first discuss and freeze on a directory structure. Democracy will slow things down, but I am sure we can arrive at a library structure for scripts, symbols, and footprints it won't be an NP-complete process. 2. After that, we ask all contributors to create this dir-tree structure in their own CVS areas on the site. This way, we all know which of the elements from, say, John's CVS area are meant for which library category. 3. A small script runs once a night and picks up element files from each contributor's CVS area, and copies to the corresponding locations in an aggregated libraries area. This script can also create tar.gz of the aggregated libraries, for easy download. 4. Name conflict: whenever there is a name conflict, the aggregating script can append the contributor's name to the original element filename to create a new filename. Simplistic, but the recipient of the final library can then look through the various versions of the part and decide to keep one. At that point, he renames that file from R-0207-10mm-Chandra_Tarun to R-0207-10mm. He can probably leave all the alternate R-0207-10mm* files as they are, with the author names tagged, for future reference. I'm trying to make it as easy as possible for people to contribute symbols and footprints. Thus, adding more restrictions on how things are contributed goes against my purposes. I thought it would be nice to make it easy for a user to use the elements, without sacrificing the ease for the contributor. The current system (to each their own) doesn't require any work on my part, and scales well. Trying to organize the whole thing would not be trivial. Such efforts are better spent on the official libraries. I feel that once the hierarchy of directories is decided for the official libraries, the same can be applied here too. And once decided, the entire thing can run without any manual work from your side. Combining them that way would lose attribution, unless I modified the files somehow to include it. We really want feedback to go to the authors, so they can track the quality of their contributions. Such history is useful when trying to merge them into official libraries. The aggregation script can automatically add a comment into each element file, giving the full name of the contributor. Even an email address and other details could be added this way, if each contributor is asked to keep a small file in the top dir of his CVS area with a few lines of comments. This small file will be picked up verbatim and added into each element file that he contributes. This will be done automatically by the aggregator script. Tarun -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A suggestion about the stuff on gedasymbols
Note, also, that any user can use cvs to download (and update) the entire web site, which includes the symbols and footprints in their current structure. Agreed. I feel that for someone who is not interested in updating/uploading anything, a tarball is much easier than setting up CVS. At least it is for me. :) -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
I am a beginner, and I have a lot of exposure to Eagle, so please keep these limitations/biases in mind. I would really like to see the following additions: 1. In gschem, when selecting a footprint, I would like to see the footprint _and_ its description in a popup window. I should be able to browse the footprint library _visually_, basically. 2. In PCB, when I create a Convert buffer contents into an element, it should ask me for a description of the element. This should get embedded in the description field in the element header line. 3. There should be native support for elongated vias (they are called pads in Eagle) when defining an element. Since pin addition while creating a footprint in PCB is done by adding a via, maybe this elongated shape should be added as an option to the via itself, like you can flip between circular and octagonal. And then of course one would need the ability to rotate a via, so that the elongated shape could be aligned the way I want. The current method to define elongated pads (pins in PCB element terminology) is really roundabout, and error-prone, and needs manual editing of the element file in a text editor, if I understand correctly. You have to define (at least) two pads manually, one for the solder layer, one for the component layer, and make sure they both match the pin/via in diameter and centering, and then manually edit the element file to make the pad numbers match the pin number. I feel elongated pads is a sufficiently universally used feature to require native support in the software. I suspect that I am unaware of the heated arguments some of these issues must've seen in the period before I joined the list, in which case please excuse my raking them up again. :) BTW, I like the way PCB has unified the concepts of pads for element footprints, vias, and holes. Good engineering design, I thought. :) Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: installation
This is almost a religious issue. Aren't most questions which have many correct answers? :) However, I personally recommend users to install into a new directory, /usr/local/geda, and then set their $PATH variables to point to it... Great. This is really I wanted to know. I wanted to know how a user would install in some system area which would be outside all home directories, and how he would set the ownership of the package files to be someone other than the human users of the system. If the installer does this, that's all that's needed, IMHO. Tarun -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
3. There should be native support for elongated vias (they are called pads in Eagle) when defining an element. The way to do this in pcb is to put a pin and a pad in the same place. The pin gives you the drill hole, and the pad defines the elongated copper shape. Yes, I've tried this with my footprints. The problem is that you need two pads (for a traditional double-layer footprint) and you need to edit the text file of the element to set the numbering of the pads. (Can I set the pad number through the GUI of PCB the way I can for the pin number by pressing 'n'?) This approach is error-prone, I felt. When I open up the text file of the element, I see a list of pads but I don't know which two pads are associated with pin 1, and so on. It's not heated, it's just nobody has had the time to do it right, yet. For example, a true multipin (my name) would need to know more about the physical layer stack than pcb currently knows. But I do envision a multipin having the ability to independently specify: * top, inner, and bottom shapes * copper shapes, including hole-to-edge distance and radius of each corner * pads defined by polygons * copper, paste, and mask each independently defined The current plan is to defer this until after the layer type flags project is done, as that project gives us proper mask, paste, etc layers. Yes, I've been reading some of the discussions about the multipin and the layer-type projects, and I got the sense that these would make a lot of the work easier for elongated pads. I think it's a good idea to do it in the sequence you intend. Will make the implementation a whole lot cleaner and more powerful internally. Tarun -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
You may want to try one of the many footprint scripts that are around. Making the footprints in a batch using a script is a lot less error prone than one by one in the GUI. If you are looking for DIPs or SIP headers with rounded pads over pins you could try my website. Actually I've seen some of those scripts and they are lovely for the kind of things they do. But I need to build much simpler footprints like TO220 devices, but with elongated pads. These are best done by hand, I guess. I even like TO92 to have elongated pads. I suspect I'm just unsure of my soldering skills and like larger pads, that's all. :) One area where I'll be developing scripts is for simple capacitors. I want pretty-looking non-polar and cylindrical electrolytic caps of various sizes. (No elongated pads needed.) Resistors I've already done by hand. Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
A script to place TO220 pads can be pretty simple (see below). The poorly named routine element_add_pin_oval overlays a pin, a rounded pad on the component side and a rounded pad on the solder side. Very interesting. What's Pcb_8? Where do I find it? I'm looking through your Website to see if there's some Perl module there. Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
Very interesting. What's Pcb_8? Where do I find it? I'm looking through your Website to see if there's some Perl module there. Found Pcb_8 in your Perl library documentation. Thanks. Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
A script to place TO220 pads can be pretty simple (see below). The poorly named routine element_add_pin_oval overlays a pin, a rounded pad on the component side and a rounded pad on the solder side. I have been reading your (excellently-formatted reference-class) documentation on your library. The documentation does not mention that add_pin_oval adds two pads on two layers... it seems to say that this is a hybrid object consisting of a pad and a pin with the same centre point. Is the document out of sync with the library? Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hi.... first post
Thanks, all of you guys. Specially Dan, your explanation of pin names and numbers was desperately needed. Here is the problem. In PCB, pins have a name and a number. The number is specific to the package and the name is specific to whats inside the package. Lets take a SO8 package that happens to house an op-amp. In the schematic you have pin numbers and pin labels. You might have pin 2 labeled as IN- and pin 3 labeled as IN+ and pin 7 labeled as OUT. When you netlist, you refer to pin numbers. So for example, U1-2 and U1-3 and not U1-IN- and U1-IN+. The pin numbers define all of your connectivity information. The pin labels are simply informative. Now you load PCB. The rat lines key off of the pin number and uses the pin number in the netlist. Pin names are not used at all. So if pin numbers are broken in your symbol or footprint, thats it, game over, things are just broken. Now that the .cmd file does is it goes through and says U1-2 (i.e. pin #2 of U1) happens to be called the IN- pin on this particular op-amp. And it makes all those changes. Now if you query that pin in pcb, it will tell you pin #2 and IN-. This is useful when you're working with a big part and you don't know the pinout by heart or via the context and you want to quickly see the name of the pin you're connecting too. Thats all the .cmd file does. If you don't ever load it, nothing bad happens other than querying U1 pin #2 will just report this is pin #2. It is called '2' instead of . It is called IN-. This ought to go in a FAQ, and also into the gschem-pcb tutorial. This explanation is a MUST. I have read perhaps 100 A4-sized pages of text on gschem and pcb and the connection between the two, by going through the info pages for PCB and online tutorials and FAQs. And I remember feeling very uneasy about the names-versus-numbers issue. But I do not remember reading any good explanation. Your text above should not be allowed to be lost. In addition, the tutorial should add some explanation of the .cmd file generated by gsch2pcb, and also spend a bit more time explaining what refdes_renum does. (And references to the Screen menu in PCB should be removed.. the version of PCB I am seeing (200608xx) does not have a Screen menu at all.) Can you please put it in the gschem-pcb tutorial? I guess Bill Wilson is also on this mailing list? If there is something I could do, please tell me. Tarun -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hi.... first post
I just asked Ales for a http://geda.seul.org/wiki login. It's for the gEDA suite Great. How do I ask Ales for a login? Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Hi.... first post
Can any of you please help me with this question? Why didn't the .cmd file work? Tarun -- Forwarded message -- From: C P Tarun [EMAIL PROTECTED] Date: Mar 14, 2007 9:33 PM Subject: Re: gEDA-user: Hi first post To: gEDA user mailing list geda-user@moria.seul.org Guys, Can you please help me with one part of my original question? 1. When I load the netlist into the PCB program, it gives errors saying that it couldn't find pins with the names given in the footprints, or some such thing. Just try loading my .pcb file first, then try loading the netlist, and you will see what I mean. This problem does not go away even after you :ExecuteFile(test-schem.cmd) I believe we have all agreed that the pin numbers in the symbol and the footprint don't match, causing problems with the netlist. However, I did run the test-schem.cmd file after loading the layout into PCB. Shouldn't that have fixed these naming problems? For the set of my files, check http://www.dhandanought.org/tcpip/audio/EXP/geda-probs/ thanks, Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Hi.... first post
My Active crossover designe might be interested for you... if not, just ignore. http://web.interware.hu/lekovacs/xover/index.html Very interesting, thanks. I've bookmarked the page; will read it over the next few days and check out your gschem and PCB files. -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Hi.... first post
Hi guys, I'm new to this list, and I've just begun exploring gschem and PCB a week or so back. Thought I'd introduce myself. I am an engineer by qualification and am interested in audio system building. Hence my need for a circuit design environment. I have used Eagle (the free version) for a few years, and designed a few PCBs with it. I like Eagle a lot, and I began looking around for an alternative purely because of the board size limit of 6.4x4 for non-profit Eagle licences. Now I have discovered gschem and PCB, I'd really like to use this for the foreseeable future if I can. If you have time to kill, you can poke around at http://www.dhandanought.org/tcpip/site/ or check postings by tcpip on www.diyaudio.com I am a veteran user of Unix (since 1990 or so) and Linux (since kernel version 1.0.8) I use Windows only to run speaker design applications like Unibox (needs MS Excel) or Speaker Workshop, or run complex PPT presentations. I tried building a simple toy schematic using gschem and pushing it to PCB, but my netlist is not showing all the connections, because the pin names (numbers?) of the transistor symbols in the schematic are not matching with the TO92 pin names (numbers?) in the footprint, even after I run the .cmd file generated by gsch2pcb. Can you please help? If you want to see the test schematic and associated files, please check http://www.dhandanought.org/tcpip/audio/EXP/geda-probs/ Thanks, Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Some footprints I tried to create
I have tried to create some common footprints in PCB, partly just to learn how this thing works. Since I have some experience with Eagle, I liked the footprints in their library. So I saw the footprints for common components in PCB and didn't like their barebones shapes, and decided to create some of my own. I kept the following in mind: 1. Some portions of the PCB library have values associated with footprints, e.g. 1M resistors and 100K resistors, etc. I thought this was unnecessary. Or maybe I'm missing some vital point... you can tell me about it. 2. Eagle footprints are drawn using 6mil lines. I thought this was too thin, so I drew them using 8mil lines. (My PCB fab chap seems to generate really ultra-thin lines on the silkscreen with 6mil. YMMV.) Existing footprints with PCB seem to be drawn with all sorts of line thicknesses, including 10mil and 20mil, which I found too thick in some cases. 3. I tried to make the parts look like pictures, not diagrams or symbols. Being a novice circuit designer, I find this important. To me, accurate pictorial representation of a component on the silkscreen is akin to mnemonic variable names in code. The software works just as well with poorly chosen variable names, but it's easier to read and understand when the names are intelligently chosen. 4. I did not understand the rationale for the drill dias of the pads in some of the parts in the PCB database. I have tried to select the drill dia carefully here, based on my limited knowledge of the lead diameters. 5. In my hobby electronics experience, I find that the annular copper ring around a drill hole for a pad needs to be at least 10 mil in width, preferably 15mil, for easy soldering and de- soldering. I've tried to retain this in the pins I've done with my footprints. YMMV. But with this brilliant decision of PCB to keep all file formats as ASCII, it'll be easy for someone to write a script to patch the pin annular widths as per your preferences if you wish. (I would love to have a script which can do with a PCB layout what Eagle does in its DRC: set a min width and max width for annular rings, with a percentage of drill dia as the guiding rule for in-betweens.) 6. I did not like the transistor footprints for TO220, TO126, etc, which I found with PCB. Some of them did not give me any visual indication of which side was the front of the device. So I drew the shapes accordingly in my footprints, to give a clear visual indicator. 7. I found square pins for Pin 1 of a lot of non-polar passive components in the PCB library. I found this unnecessary and adding to visual clutter. So I just decided to design my footprints with both pins round for such devices. 8. I wanted elongated pins/pads for some of the higher-current devices. So I incorporated them. I don't know whether it'll work in reality when I include the device in PCB. I haven't yet generated Gerbers and checked. 9. I created separate sets of footprints for each resistor form factor. In the existing PCB library, when you move from a 200mil leg spacing to a 300mil spacing, the device also becomes wider. This is misleading, and you can't use the silk outline effectively to place devices tightly when you are short of space. You need accurate body shapes and sizes in the silk outline, IMHO. I tried to do this. I don't know whether these definitions will work. If any of you can give me feedback, I'll correct my mistakes and put them back up again. I need these things to be flawless, for my own sake. Check: http://www.dhandanought.org/tcpip/audio/EXP/geda-footprints/ Thanks for the help Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hi.... first post
Welcome ! Read your post on diyaudio as well. I am active as blu_line over there. Kewl!! So we diy audio guys do have some presence in the geda gang after all! Great. :) Hope to see interesting circuits built using geda. I'm waiting for the time I'll get my first audio circuits done using gschem+PCB. I'll post them on diyaudio and do some _serious_ hardsell about how this is a great EDA environment for the hobbyist. -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Some footprints I tried to create
Stuart, Thanks for a very helpful response. 1. Although it's not (yet) mandatory, we usually suggest that footprints use .fp as a file suffix. Yes, I saw the notes on gedasymbols.org, and also wrote to DJ asking him for a CVS upload account on his site. He hasn't yet gotten around to replying. I will change the filenames to conform to this standard sometime soon. 2. You may be interested in looking around our website for contributed footprints, symbols, and other materials: http://www.gedasymbols.org/ I've already begun. I wish there was a footprint viewer app which would just display one footprint file with variable mag, the way gerb does for gerbers. That way, I could quickly download and look at each footprint in detail. If wishes were horses... :) A couple of other footprint links for you, in case you haven't found them yet: http://geda.seul.org/wiki/geda:pcb_tips http://www.luciani.org/geda/pcb/pcb-footprint-list.html Thanks, I hadn't seen these. -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hi.... first post
What I really need to know is how did this happen? When using gschem, I tried moving each transistor to check whether the nets were connected to the pins or not, and they moved with the symbol, showing connection. After that, why did the connections not show up in the netlist? They did show up. I do not see connections for other than E pins in the schematic. There was one additional connection, to the base of one transistor. But that's only part of the story. The other part of the problem was that when I opened the generated .pcb file in the PCB program and loaded the netlist, the program gave me errors saying that it couldn't find pin names for the two transistors. (There were six errors for all six pins of the two transistors.) And in the ratsnest lines, I did not see any ratlines connecting to any of the pins of the transistors. This is the part that I'm concerned about. Why did this happen? What did I do wrong? Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hi.... first post
Yeah, like John pointed out this is a problem with the symbol
${geda install dir}/share/gEDA/sym/analog/npn-2.sym. It uses B, C,
and E as the pin numbers. The pinnumber needs to be a number, and
the numbers should correspond to the numbers on the footprint you want
to use.
Even if I assume that this is the cause of the problem, why didn't the
.cmd file fix it? What am I missing here?
Tarun
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Re: gEDA-user: Some footprints I tried to create
Yes, I saw the notes on gedasymbols.org, and also wrote to DJ asking him for a CVS upload account on his site. He hasn't yet gotten around to replying. Only because I didn't see it, please send again. Just did. Hope it reaches this time. I've already begun. I wish there was a footprint viewer app which would just display one footprint file with variable mag, PCB in cvs can load footprints directly, and it has variable mag. The startup time of the version of PCB I have is so huge that that alone may become a problem. A lighter program would have really helped, I thought. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hi.... first post
I use a part that has a NPN and a PNP in one package. Six leads, six position numbers, 2 C's, 2 B's, 2 E's. How would you deal with that? For any device other than transistors, I guess numbers are fine. After all, for those devices, you don't have a universally accepted single symbol which is available in multiple package pinouts, right? -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hi.... first post
2. Yes, lots of people call for heavy symbols, in which each symbol calls out a specific footprint, and there's no discrepancy between pinnumber on the symbol and on the footprint. Hmmm... I think this is the approach which is safest for a novice designer like me. I guess I'll just roll my own. Alternately, there does exist an opportunity for somebody to sell CDs full of heavy symbols in which each symbol calls out a specific footprint, and all symbols/footprints have been checked/vetted! You know who I mean ;-) :) Tarun -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
