gEDA-user: gpcb-menu.res
I noticed that recent PCB doesn't interpret my gpcb-menu.res file located in ~/.pcb. Instead it writes the following line to the standard output/error: @�: No such file or directory and the following line to the log window: Note: home directory is "/home/leva" Loading menus from Loading menus from Using default menus cheers, Levnte -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem vs. PCB diode pin numbering
On Mon, 29 Aug 2011 22:28:22 +0200 Levente Kovacs wrote: > On Mon, 29 Aug 2011 10:28:11 -0700 > Colin D Bennett wrote: > > > Nice! That sounds very slick. Have you shared your code for this > > pin-mapping tool? > > What I do is I share my git repositories... > > http://git.logonex.eu/?p=utils4geda.git;a=tree;f=scripts4geda;h=e2d27439fbed3df645cfc65248ef690dd32956f4;hb=HEAD > > The magic is done by light2heavy.pl and gen_heavy_sym.pl, but you > need other scripts as well. You should look at dbsym_update.pl as > well, which calls other scripts. > > You can examine my makefile system too. > > http://git.logonex.eu/?p=utils4geda.git;a=tree;f=pskel;h=4acca5f5b50d8943656cbd9a4faf46726a0e804f;hb=ce4516e8a351b54818abfaacb215d7864b6d1b43 > > Makefile.sch is the one for schematics. Bfff... this was an old commit... this one is "head". http://git.logonex.eu/?p=utils4geda.git;a=tree;f=pskel;h=e4a14b5b812f2b235f875a959ad3967cdb4bb471;hb=b8920019ddd79ce76d9644689fe847be9332bfa9 Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem vs. PCB diode pin numbering
On Mon, 29 Aug 2011 10:28:11 -0700 Colin D Bennett wrote: > Nice! That sounds very slick. Have you shared your code for this > pin-mapping tool? What I do is I share my git repositories... http://git.logonex.eu/?p=utils4geda.git;a=tree;f=scripts4geda;h=e2d27439fbed3df645cfc65248ef690dd32956f4;hb=HEAD The magic is done by light2heavy.pl and gen_heavy_sym.pl, but you need other scripts as well. You should look at dbsym_update.pl as well, which calls other scripts. You can examine my makefile system too. http://git.logonex.eu/?p=utils4geda.git;a=tree;f=pskel;h=4acca5f5b50d8943656cbd9a4faf46726a0e804f;hb=ce4516e8a351b54818abfaacb215d7864b6d1b43 Makefile.sch is the one for schematics. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem vs. PCB diode pin numbering
On Thu, 25 Aug 2011 14:03:35 +0200 Kai-Martin Knaak wrote: > Why not? Pinnumbers are "numbers" in the first place. Former versions of netlisters/PCB got confused by non-digital pinnumbers. With this approach you have to have a SOT23 footprint with 1,2,3 pinout, A,K,NC pinout, A1,A2,K pinout, B,C,E pinout etc. Sooner or later, your library will contain duplicated data. What if you discover that you want to modify the shape of the SOT23.fp footprint? You have to modify all of them. Yuk. I think a footprint must have only *one* pinout, that is a standard pinout of the package. Have an intermediate layer (scripts, database, pinmaps, etc.) that do the heavy lifting for you. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb HID GUI options: gtk, lesstif?
On Tue, 23 Aug 2011 16:31:49 -0400 DJ Delorie wrote: > I think dockable toolbars is the way to go. +1. And the ability to store toolbar states in configuration file, or *.pcb file. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb HID GUI options: gtk, lesstif?
On Tue, 23 Aug 2011 14:29:50 -0400 DJ Delorie wrote: > > That would play nice on a dual headed setup. > > One of my "dream projects" is to do a GUI for pcb that uses two or > more monitors, with one monitor heavy on the toolbars and showing an > overview "thumber" window, and the other monitor being 100% layout. > > > There were fights against GTK people not to take tear-off menus from > > gtk3. But they did AFAIK. > > The lesstif tear-off model isn't so hot either. I've been considering > writing my own from scratch to work around some of the weirdisms. As you might noticed I don't have too much programming skills but I support this as well. It would be nice to have for both HIDs. BTW... is there any TODO list of the project? File format change, GUI change, etc... with priorities... or the developers just do what they want to? Don't get me wrong, I don't say anything against it... just curious. But maybe it would be nice to have one... someone might pick up some of the tasks, and do it. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb HID GUI options: gtk, lesstif?
On Tue, 23 Aug 2011 09:55:21 -0700 Colin D Bennett wrote: > It would be great if the gtk GUI could provide some options to > increase available screen space Once I started to work on a patch to have the look and feel of the lesstif GUI in the GTK GUI. However, I think we should implement everything with toolbar (if I'm not mistaken) That would play nice on a dual headed setup. There were fights against GTK people not to take tear-off menus from gtk3. But they did AFAIK. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: viewing side vs. layers
On Mon, 22 Aug 2011 21:17:11 -0700 Andrew Poelstra wrote: > What should be happening? I will make sure this works > when I implement my new gtk layer selector. You see your board from component side, and you switch off the copper view of the other side. Optionally, switch off the "far side". Now press tap one time, and the other side will show up (components on the other side, copper on other side). Press TAB once again. Components on the component side will show up, and the copper on the other side will remain. Press TAB a few times to play with it. BTW. This mechanism is good when you work with two layers. However, it is not so good when you have a 4 layer board. Some more generic strategy would be better. However, thank you for your effort to make PCB better! :-) Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: viewing side vs. layers
On Mon, 22 Aug 2011 16:51:03 -0400 DJ Delorie wrote: > Which GUI ? GTK -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: viewing side vs. layers
The automatic layer change capability is missing from the current HEAD ( 7b590a617db3ca3ed69965b544f1468f82c39dfe ). I.e. when you swap viewing side with TAB. It works only once, then stops working. Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tag-Connect TC2030-MCP(NL) footprint, expert review
On Fri, 12 Aug 2011 11:04:54 -0700 Colin D Bennett wrote: > I've created gEDA/pcb footprints for the Tag-Connect I've done that before. I thought I made it public. I sent the footprints to the company, I received a tag connector for free, but my footprints didn't made to their homepage. :-) http://git.logonex.eu/?p=library.git;a=tree;f=electronic/footprint;h=1850fa21028a1f1e69284f1f6b67849e41fe4763;hb=HEAD tag_connector_*.fp Cheers, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Layer selective DRC
On Fri, 5 Aug 2011 17:36:25 + (UTC) Sparky wrote: > For my outline layer I did the following to add the attribute: > Edit->Edit attribute of->CurrentLayer > Left box: PCB::skip-drc > Right box: 1 I'm sorry for the late answer. I'm not sure if you need this for the layer called "outline". For the others, thank you for taking time playing with it. I didn't experienced any trouble with the feature. However, I'm not a heavy DRC user. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Layer selective DRC
If you add the attribute PCB::skip-drc to a layer, that won't be checked against DRC, and commections. Levente On Wed, 3 Aug 2011 23:56:23 -0700 Colin D Bennett wrote: > On Thu, 04 Aug 2011 01:48:09 +0200 > Kai-Martin Knaak wrote: > > > Colin D Bennett wrote: > > > > > A feature I have heard previously requested is to be able to mark > > > certain layers as “no-DRC”. For instance, to allow special trace > > > elements such as antennas that the DRC thinks are incorrect shorts > > > between two nets. > > > > These should be omited from update_rats, rather than be ignored on > > DRC. The DRC as it is currently implemented, does not check for > > correct connectivty. It does not detect a short. > > Oh, that's right. I forgot since I tend to consider the Optimize Rats > action and its feedback as a first pass of DRC, and the actual DRC > action as a more detailed pass... but it seems like it would be ideal > for a short to be detected by DRC. > > > I think, this > > functionality would be best implemented with a flag > > "don-t-check-connectivity" added to the object. Put these antennas > > in a separate layer and make DRC special for this layer would still > > feel like a crutch. > > My current workaround is to actually connect the antenna input > directly to ground on the schematic, so that pcb does not complain > that the PCB trace antenna is a short. (See attached figure from the > schematic.) For this specific and simple purpose, this works well > enough for the moment. > > Regards, > Colin > -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: skpi_drc patch
On Fri, 17 Jun 2011 17:30:22 -0400
DJ Delorie wrote:
> You want the (already global) AttributeGet() function.
>
> l->no_drc = AttributeGet (l, "PCB::skip-drc") != NULL;
>
> This does assume that the attribute has *some* value, even if the
> value is the empty string.
Thanks for pointing this out.
Attached is the new patch.
Levente
--
Levente Kovacs
http://levente.logonex.eu
diff --git a/src/find.c b/src/find.c
index eb4cac2..c5159ba 100644
--- a/src/find.c
+++ b/src/find.c
@@ -822,6 +822,8 @@ LookupLOConnectionsToPVList (bool AndRats)
/* now all lines, arcs and polygons of the several layers */
for (layer = 0; layer < max_copper_layer; layer++)
{
+ if (LAYER_PTR (layer)->no_drc)
+ continue;
info.layer = layer;
/* add touching lines */
if (setjmp (info.env) == 0)
@@ -1169,6 +1171,8 @@ LookupPVConnectionsToLOList (bool AndRats)
/* loop over all layers */
for (layer = 0; layer < max_copper_layer; layer++)
{
+ if (LAYER_PTR (layer)->no_drc)
+ continue;
/* do nothing if there are no PV's */
if (TotalP + TotalV == 0)
{
@@ -2901,6 +2905,21 @@ ListsEmpty (bool AndRats)
return (empty);
}
+static void
+reassign_no_drc_flags (void)
+{
+ int layer;
+
+ for (layer = 0; layer < max_copper_layer; layer++)
+{
+ LayerTypePtr l = LAYER_PTR (layer);
+ l->no_drc = AttributeGet (l, "PCB::skip-drc") != NULL;
+}
+}
+
+
+
+
/* ---
* loops till no more connections are found
*/
@@ -2908,6 +2927,7 @@ static bool
DoIt (bool AndRats, bool AndDraw)
{
bool newone = false;
+ reassign_no_drc_flags ();
do
{
/* lookup connections; these are the steps (2) to (4)
@@ -3350,6 +3370,7 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
/* check if there are any pins or pads at that position */
+ reassign_no_drc_flags ();
type
= SearchObjectByLocation (LOOKUP_FIRST, &ptr1, &ptr2, &ptr3, X, Y, Range);
@@ -3366,8 +3387,8 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
int laynum = GetLayerNumber (PCB->Data,
(LayerTypePtr) ptr1);
- /* don't mess with silk objects! */
- if (laynum >= max_copper_layer)
+ /* don't mess with non-conducting objects! */
+ if (laynum >= max_copper_layer || ((LayerTypePtr)ptr1)->no_drc)
return;
}
}
diff --git a/src/global.h b/src/global.h
index daa82a9..08abbb8 100644
--- a/src/global.h
+++ b/src/global.h
@@ -303,6 +303,7 @@ typedef struct /* holds information about one layer */
char *Color, /* color */
*SelectedColor;
AttributeListType Attributes;
+ int no_drc; /* whether to ignore the layer when checking the design rules */
}
LayerType, *LayerTypePtr;
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Re: gEDA-user: Bug in PCB's Gerber generation?
On Fri, 17 Jun 2011 10:40:50 -0700 Andrew Poelstra wrote: > Good catch. I missed this in my test case as well, since > I ran ``gerbv *.gbr'', forgetting about the .cnc file. I > have committed your fix, checked that the output (of ALL > files) is correct now, and fixed the test. > > Thanks for reporting! Thanks for commiting! -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: skpi_drc patch
Attached you can find the "skip_drc" patch for the current head.
It would be nice if it was checked in to git HEAD.
Thanks,
Levente
--
Levente Kovacs
http://levente.logonex.eu
diff --git a/src/action.c b/src/action.c
index 4f2e401..af93c19 100644
--- a/src/action.c
+++ b/src/action.c
@@ -6947,7 +6947,7 @@ find_element_by_refdes (char *refdes)
return NULL;
}
-static AttributeType *
+AttributeType *
lookup_attr (AttributeListTypePtr list, const char *name)
{
int i;
diff --git a/src/action.h b/src/action.h
index ee116e8..6dbaf2d 100644
--- a/src/action.h
+++ b/src/action.h
@@ -46,4 +46,5 @@ void warpNoWhere (void);
/* In gui-misc.c */
bool ActionGetLocation (char *);
void ActionGetXY (char *);
+AttributeType * lookup_attr (AttributeListTypePtr list, const char *name);
#endif
diff --git a/src/find.c b/src/find.c
index eb4cac2..cdd1063 100644
--- a/src/find.c
+++ b/src/find.c
@@ -94,6 +94,7 @@
#include "set.h"
#include "undo.h"
#include "rats.h"
+#include "action.h"
#ifdef HAVE_LIBDMALLOC
#include
@@ -822,6 +823,8 @@ LookupLOConnectionsToPVList (bool AndRats)
/* now all lines, arcs and polygons of the several layers */
for (layer = 0; layer < max_copper_layer; layer++)
{
+ if (LAYER_PTR (layer)->no_drc)
+ continue;
info.layer = layer;
/* add touching lines */
if (setjmp (info.env) == 0)
@@ -1169,6 +1172,8 @@ LookupPVConnectionsToLOList (bool AndRats)
/* loop over all layers */
for (layer = 0; layer < max_copper_layer; layer++)
{
+ if (LAYER_PTR (layer)->no_drc)
+ continue;
/* do nothing if there are no PV's */
if (TotalP + TotalV == 0)
{
@@ -2901,6 +2906,22 @@ ListsEmpty (bool AndRats)
return (empty);
}
+
+static void
+reassign_no_drc_flags (void)
+{
+ int layer;
+
+ for (layer = 0; layer < max_copper_layer; layer++)
+{
+ LayerTypePtr l = LAYER_PTR (layer);
+ l->no_drc = lookup_attr (&(l->Attributes), "PCB::skip-drc") != NULL;
+}
+}
+
+
+
+
/* ---
* loops till no more connections are found
*/
@@ -2908,6 +2929,7 @@ static bool
DoIt (bool AndRats, bool AndDraw)
{
bool newone = false;
+ reassign_no_drc_flags ();
do
{
/* lookup connections; these are the steps (2) to (4)
@@ -3350,6 +3372,7 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
/* check if there are any pins or pads at that position */
+ reassign_no_drc_flags ();
type
= SearchObjectByLocation (LOOKUP_FIRST, &ptr1, &ptr2, &ptr3, X, Y, Range);
@@ -3366,8 +3389,8 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
int laynum = GetLayerNumber (PCB->Data,
(LayerTypePtr) ptr1);
- /* don't mess with silk objects! */
- if (laynum >= max_copper_layer)
+ /* don't mess with non-conducting objects! */
+ if (laynum >= max_copper_layer || ((LayerTypePtr)ptr1)->no_drc)
return;
}
}
diff --git a/src/global.h b/src/global.h
index daa82a9..08abbb8 100644
--- a/src/global.h
+++ b/src/global.h
@@ -303,6 +303,7 @@ typedef struct /* holds information about one layer */
char *Color, /* color */
*SelectedColor;
AttributeListType Attributes;
+ int no_drc; /* whether to ignore the layer when checking the design rules */
}
LayerType, *LayerTypePtr;
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Re: gEDA-user: Jumpers on single layer PCBs
On Tue, 31 May 2011 21:59:04 +0100 Thomas Oldbury wrote: > Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like > each jumper to have a refdes and BOM entry if possible.) What I'd do is define a copper layer. Draw your jumpers on the that layer. Don't send the layer data to the fab house. Make sure you have mask openings on vias. Solder jumpers in the vias. I recommend using double sided boards. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GL on non-accelerated hardware?
On Mon, 16 May 2011 10:17:34 +0100 Peter Clifton wrote: > Anyway, it would be worth testing to check I tested it on my notebook. It has an Atom CPU with an intel GPU. With the GL renderer it can do 7fps. With the original renderer it is 7.2. No significant change. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB crash
On Tue, 17 May 2011 00:10:07 +0100 Peter Clifton wrote: > I'll try and fix it shortly. Peter, Thank you. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB GL Memory leak
On Sat, 14 May 2011 10:59:57 +0100 Thomas Oldbury wrote: > After using PCB+gl for more than an hour or so on a basic 4-layer > board, it is using nearly 3.5 GB of memory, slowing the system to a > crawl and forcing it to page a lot of data. Is anyone else > experiencing this issue? Do you have this issue with PCB compiled with --disable-gl ? Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: autocrop.c vs. pcb (git head)
I'm trying to load autocrop.so to my recently compiled (from git HEAD) pcb. What I get is this: dl_error: /home/leva/.pcb/plugins/autocrop.so: undefined symbol: ClearAndRedrawOutput Is there any way to tweak pcb and/or autocrop.c to work together? Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [spice] capacitor current
On Sat, 16 Apr 2011 15:13:33 -0600 John Doty wrote: > If the refdes is "V1", the current is "V1#branch". Thank you. That did the trick. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [spice] capacitor current
On Sat, 16 Apr 2011 13:10:50 -0400 al davis wrote: > With Gnucap, just ask for the capacitor current. > > print ac i(c*) > > (this prints all capacitor currents) I use ngspice... will it work with that? -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: [spice] capacitor current
I want to simulate my low pass filters. So far, I managed to have my theoretical results. Now I want to know the currents of the capacitors vs. the frequency. I remember that the best way is to put 0V voltage sources in series of the capacitors, but I don't know how to get the AC current of the source. Could you provide any hint on this? The schematic attached. Any help is appreciated. Thanks, Levente -- Levente Kovacs http://levente.logonex.eu PA_lpf.sch Description: application/geda-schematic ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Split ground planes and zero ohm jumpers
On Tue, 5 Apr 2011 13:11:25 -0700 Russell Dill wrote: > Perhaps I'll go with a solder blob jumper. A "drawbridge" component in > PCB that is just a special type of trace would be really nice. Yeah. I miss the concept of the "star point". -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: [gschem] netname refactor?
hi, Is there any way in gschem (or gattrib) to refactor netnames in a given set of schematics? Thnaks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: skip drc
On Thu, 10 Mar 2011 17:47:58 + Ineiev wrote: > Thank you! it would be nice if someone added corresponding bits > of documentation to the patch. Could you please upload it to the tracker? It might get more attention. I'd really see it checked into the HEAD. Every time I compile a new PCB, I have to patch. Browsing the source, I see that there is some movement to support non-copper layers. I don't know the state of that. Still I think it is a good feature. Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: skip drc
Hi,
I have rewritten the skip_drc patch (originally written by Ineiev) to apply
to the current git HEAD.
The original patch can be found here:
http://www.seul.org/pipermail/geda-user/2010-September/048721.html
My patch is attached.
Levente
diff --git a/src/action.c b/src/action.c
index de2738e..2ad20b1 100644
--- a/src/action.c
+++ b/src/action.c
@@ -7001,7 +7001,7 @@ find_element_by_refdes (char *refdes)
return NULL;
}
-static AttributeType *
+AttributeType *
lookup_attr (AttributeListTypePtr list, const char *name)
{
int i;
diff --git a/src/action.h b/src/action.h
index ee116e8..ca1cbc3 100644
--- a/src/action.h
+++ b/src/action.h
@@ -46,4 +46,7 @@ void warpNoWhere (void);
/* In gui-misc.c */
bool ActionGetLocation (char *);
void ActionGetXY (char *);
+
+AttributeType * lookup_attr (AttributeListTypePtr list, const char *name);
+
#endif
diff --git a/src/find.c b/src/find.c
index 615659d..167f149 100644
--- a/src/find.c
+++ b/src/find.c
@@ -94,6 +94,7 @@
#include "set.h"
#include "undo.h"
#include "rats.h"
+#include "action.h"
#ifdef HAVE_LIBDMALLOC
#include
@@ -822,6 +823,8 @@ LookupLOConnectionsToPVList (bool AndRats)
/* now all lines, arcs and polygons of the several layers */
for (layer = 0; layer < max_copper_layer; layer++)
{
+ if (LAYER_PTR (layer)->no_drc)
+ continue;
info.layer = layer;
/* add touching lines */
if (setjmp (info.env) == 0)
@@ -1169,6 +1172,8 @@ LookupPVConnectionsToLOList (bool AndRats)
/* loop over all layers */
for (layer = 0; layer < max_copper_layer; layer++)
{
+ if (LAYER_PTR (layer)->no_drc)
+ continue;
/* do nothing if there are no PV's */
if (TotalP + TotalV == 0)
{
@@ -2896,6 +2901,19 @@ ListsEmpty (bool AndRats)
return (empty);
}
+static void
+reassign_no_drc_flags (void)
+{
+ int layer;
+
+ for (layer = 0; layer < max_copper_layer; layer++)
+{
+ LayerTypePtr l = LAYER_PTR (layer);
+ l->no_drc = lookup_attr (&(l->Attributes), "PCB::skip-drc") != NULL;
+}
+}
+
+
/* ---
* loops till no more connections are found
*/
@@ -2903,6 +2921,7 @@ static bool
DoIt (bool AndRats, bool AndDraw)
{
bool newone = false;
+ reassign_no_drc_flags ();
do
{
/* lookup connections; these are the steps (2) to (4)
@@ -3345,6 +3364,7 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
/* check if there are any pins or pads at that position */
+ reassign_no_drc_flags ();
type
= SearchObjectByLocation (LOOKUP_FIRST, &ptr1, &ptr2, &ptr3, X, Y, Range);
@@ -3361,9 +3381,10 @@ LookupConnection (LocationType X, LocationType Y, bool AndDraw,
int laynum = GetLayerNumber (PCB->Data,
(LayerTypePtr) ptr1);
- /* don't mess with silk objects! */
- if (laynum >= max_copper_layer)
+ /* don't mess with non-conducting objects! */
+ if (laynum >= max_copper_layer || ((LayerTypePtr)ptr1)->no_drc)
return;
+
}
}
else
diff --git a/src/global.h b/src/global.h
index 0420a18..8460714 100644
--- a/src/global.h
+++ b/src/global.h
@@ -301,6 +301,7 @@ typedef struct /* holds information about one layer */
char *Color, /* color */
*SelectedColor;
AttributeListType Attributes;
+ int no_drc; /* whether to ignore the layer when checking the design rules */
}
LayerType, *LayerTypePtr;
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Re: gEDA-user: Breaking up power planes
On Sat, 19 Feb 2011 12:37:53 -0500 DJ Delorie wrote: > I use the polygon editor. With the new Holes tool, it's a lot easier. You mean moving the vertex of a polygon? And waht are you doing when it is hidden by a clearance? Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Status of gEDA - gschm, pcb?
On Thu, 10 Feb 2011 18:09:21 + (UTC) three_jeeps wrote: > Where can I find the most up to date symbol library for gschem? (Do > ppl actively contribute to it? For example, are there libraries for > Atmel and TI processors?) I'd say... a lots of places. I use the mentioned gedasymbols.org, and I have my own library as well. http://git.logonex.eu/?p=library.git;a=tree;f=electronic Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: adding information to gerber output, anyone?
On Wed, 09 Feb 2011 23:29:52 +0100 myken wrote: > Hello all, > > I didn't see any reply on my question so I guess the very busy and > overloaded knowledge base of this list didn't find the time to look > at it, so please consider this a friendly reminder ;-) > > Or am I asking a very silly question? (didn't find a answer by google) > > The question was: > I was wondering if it is possible to add more information to the > fabrication layer output of the gerber export (*.fab). > Added: I like to do this through PCB, is there a variable I need to > set? Or a command executed? So that every time the gerber is > generated by PCB this information is stored automatically in the > gerber fabrication layer output file. > I like to add the copper thickness for that specific pcb (preferably > for ever layer individually (inner/outer layer)). > So far I came up with adding this information to the outline layer > (but that doesn't end up in t A text on copper layers? Outside the board area? -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: 100 inches?
Hi list, I discovered that PCB (the GTK HID) doesn't let me define boards greater than 10 mils. Is it intentional? N.B. I can make the board larger by editing the bcb file manually. Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to make a foot print
On Wed, 5 Jan 2011 10:00:24 -0800 Colin D Bennett wrote: > [...] > > Actually, I am impressed with the flexibility of your footgen.py > script. It looks like you've created many different types of > footprints using it. I think we miss-understood each other. Or let me say I wasn't clear enough. footgen.py was written by Darrell Harmon. I'm just a user, who provided patches. http://dlharmon.com/geda/footgen.html > However, unfortunately for me at least, I cannot use it for "the > majority" of my footprints. Most of my custom footprints require > individualized design. For instance: > > - SMT LED footprints with special oversized pads as specified by > manufacturer for thermal dissipation. A good point. Please share your footprints if you can! > - FFC/FPC connector, proprietary 1.25 mm SMT header, etc. with special > extra pads for mechanical support, and silk screen indication of > reference pin (e.g., arrow for pin 1). > > - SMT aluminum electrolytic capacitors, two-pin polarized devices that > should have special silk screen including a beveled corner and "+" > symbol by one pad. Well.. I became too lazy to do that. I put a "+" mark by hand to the layout, when someone else solders the PCB. I, and the pick and place machine know the polarity. :-) > - Illuminated push-button, 5 pin through hole with non-standard pin > arrangement. > > My point is not to take away from the usefulness of your script, but > to show that many footprints (I would even say "most") require manual > design for the best results. The tool, pcb, should make this easier > and faster for users. Yes. For example, I did footprints for the Tag-connector. http://www.tag-connect.com/website_html/what_is_it.html It was made by hand. > For me, the most difficult part of drawing a footprint in pcb is > getting various dimensions from part specifications into the pcb > drawing as I create a footprint. If pcb had a dimensioning tool that > could place dimension measurements on the drawing as one is working > on it, then that would make my job much faster. As it is, I always > sketch the footprint by pencil on graph paper and figure out > dimensions from there based on part specifications, then transfer > these into pcb as I draw, making heavy use of the Ctrl-M measurement > tool. Yes. I too miss some GUI features, like "put this 2cm away", "copy that 10x with 100mil spacing", etc. > I will say that I am getting much more confident and much faster at > creating footprints in pcb as I gain experience with it, and I'm no > longer scared when I face a new part with an odd footprint. :-) Yes! YES! That is the way! I am happy to hear that! :-) -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Voltage symbols and Spice
On Mon, 03 Jan 2011 23:52:12 +0100 "Johnny Rosenberg" wrote: > Den 2011-01-03 23:37:23 skrev John Doty : > > [...] > > A bit off topic, but is it recommended to call something ”5VA” in > this case? Couldn't it be confused with the fact that VA means > Volt-Amperes, which is what you measure apparent power in? I would not start a netname by a numeric character (I don't have any reason why). I call this kind of nets as AVCC and DVCC. When I have more than one supply net I call them AVCC1, AVCC2, etc. I know this is a bit uncommon, because you have to have a table somewhere (at least one in your mind) which links which supply is what. AVCC2=5V, AVCC1=12V etc. Same goes for ground connections. AGND and DGND. HTH, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: New year
Happy new year all! Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: European symbols?
On Fri, 31 Dec 2010 13:05:41 +0100 "Johnny Rosenberg" wrote: > So I am the only one that use still them? > > And why did they use a small circle for the NOT function at the > output if the plotters had difficulties plotting them? > > They seems to be used pretty much in my country anyway. I used them > for eight years at a company a few years back. When I was working for The Big Red German Automotive Electronic supplier company back in 2008, they were using rectangular shapes for OPAs as well. Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Seeing pin numbers in PCB
On Wed, 29 Dec 2010 23:48:00 -0800 (PST) Oliver King-Smith wrote: > I can measure the size of stuff using gerbv (there may be a better > way to do this in pcb) Use Ctrl+M to set an origin. You have relative coordinates printed next to the cursor position. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Resistor values…
On Wed, 29 Dec 2010 13:18:24 -0500 DJ Delorie wrote: I regret that I made that comment. > I wish it weren't so common. Such wars are a pointless waste of time > and serve only to drive valuable contributors away. Soon, the only > people "working" on gEDA/PCB will be those who enjoy complaining, as > there will be nobody left willing to wade through the bitter arguments > and actually write code. I agree with you. But I think that it is a fact that there are lots of wars. We should really concentrate on "work". > So let me make this perfectly clear - if you're not willing to write > code, your complaints about how others write code will fall on deaf > ears. As far as I know, those of us who DO write code, do it for > purely selfish reasons - we benefit from our own work. We've said > this before, it should be no surprize to anyone. I think in an open source domain, users and "code writers" are pretty much the same. I consider myself a user, but there is code in PCB of mine. I've written a few scripts for gEDA/PCB as well. It is not much, I know. I am willing to write code, but I'm not good at code writing (Never tried it seriously though). > OTOH if you have suggestions on how to make gEDA/PCB better - easier > to use, more functional, etc - feel free to voice them. If you can > back them up with a solid design and usability models, that's even > better. Discussions about the details and caveats are to be expected! Yes! I meant "war" that I feel everyone dumps their experience, favourite tool, etc. without working the problem. > But as soon as the discussion degrades into yet another bikeshedding, > the instigators of said bikeshedding have lost all credibility with > me. > > New users - ask your questions without regret. There are no bad > questions. Harvest the answers that are useful and ignore the crap. Yes. The "let us start a Vi vs. Emacs" comment was a joke. -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Resistor values…
On Sat, 25 Dec 2010 22:01:43 +0100 "Johnny Rosenberg" wrote: > Hm… I start to regret that I asked the question in the first place… We are very good at making wars. We make wars on "what kind of fileformat to use", "what kind of documentation tool to use", "what is gschem used for" etc. So don't regret it, it is getting common. Lets make a vi vs. emacs war! Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Resistor values…
On Sat, 25 Dec 2010 00:50:07 -0600 Vanessa Ezekowitz wrote: > * If the part in question can usually be described by a single value, > for the purposes of the signal flow in the schematic that is, then > give it a default of "value=0". That is bad. You have to think twice that "is it a 0 Ohm resistor, or do I missed to attach normal value of that device?" > * If it is a discrete part that is specified entirely by its part > number rather than a measurement, like a diode or a transistor, then > pick a reasonable default; "value=1N914" or "value=2N". Again. Is it the default or real? Nobody knows. > * If the part is something like a logic IC, use the standard name of > the part in the fastest commonly available series for that particular > gate; "value=74F74" or "value=74HCT245". > > * If none of these fits, then leave the "value=" attribute off > entirely, since the user would have no choice but to get creative > anyway. That will make gnetlist to crash! :-) Believe me I tried! I spent nights manually seeking for this. Don't do it. What I do is I keep my symbols light. Sometimes it doesn't even have pin-numbers! After I made my design, I update all my symbols, and attributes with an updater script, which pulls everything from a MySQL database. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: bugs, warts and feature requests (3)
On Thu, 23 Dec 2010 12:43:45 +0100
kai-martin knaak wrote:
> • pcb feature request: Please put all the gerbers in a dedicated
> subdir of the working directory by default. The name of the subdir
> should be configurable.
>
> • pcb feature request: Optionally zip all gerbers and the cnc files
> to yield a single file that can be sent to the fab. The name of the
> zip file might contain the current date.
The two can be done by hand or scripts or Makefile, etc. Like I did (a
Makefile snipet):
gerber: ${PCBNAME}.pcb
${PCB} -x gerber --gerberfile ${PCBOUTDIR}/${FILEBASE} ${PCBNAME}.pcb
later in the Makefile:
output: clean_output gerber pdf
cp ${FILEBASE}.pdf ${PCBOUTDIR}
tar -jcvf ${FILEBASE}_${DATE_S}.tar.bz2 ${PCBOUTDIR}
rar a ${FILEBASE}_${DATE_S}.rar ${PCBOUTDIR}
Levente
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Re: gEDA-user: How to make a foot print
On Wed, 22 Dec 2010 17:29:24 -0800 Colin D Bennett wrote: > You are not alone. Making footprints in pcb takes a lot of practice, > for me a least. I have made many footprints in pcb over the past > couple of years and still I have to refer to guidelines, if I haven't > made a footprint for some time and have gotten rusty. I recommend using footprint generators for the majority of the footprits. I use the footgen.py python script. I have created most of my footprints with the script. The inputs for footgen can be found here: http://git.logonex.eu/?p=library.git;a=tree;f=electronic/autolib/footprints;hb=HEAD All of my footprints including the generated and the manually drawn ones is located here: http://git.logonex.eu/?p=library.git;a=tree;f=electronic/footprint;hb=HEAD Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Christmas wishlist
On Sat, 25 Dec 2010 22:07:16 +0100 Stephan Boettcher wrote: > This is fundamentally different from how PCB treats copper, > connectivity and netlist now, and restricts the flexifility of the > tool that results from how it works now. So, that would be a > separate set of changes. > > The current netname only as documentation? The thing made post my previous message, is that it is very annoying when unconnected line stays on PCB, and there is no chance to connect anything to it. Even to the net it was formerly connected. Other solution to this would be to let anything to be connected to copper objects (Via, line) when it is not connected to anything. > Anyway, a flexible format (like xml) can accomodate everything, > syntactically. I was thinking mostly about semantics, now. Ok, I like your ideas. Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Creating new symbols
On Sat, 25 Dec 2010 09:17:41 +0100 kai-martin knaak wrote: > IMHO, it should not. Every translation breaks instances of the symbol > in existing schematics. > > A better solution would be the notion of an origin, similar to the > diamond in pcb footprints. In PCB it is annoying that it saves the footprint with the coordinate equal to the original position of the pcb. When you save this, and let gsch2pcb do the work, it'll have some offset. One have to edit the footprint manually with a text editor. :-( This should be fixed as well. Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Christmas wishlist
On Sat, 25 Dec 2010 18:14:27 +0100 Stephan Boettcher wrote: > 132 150 132 250 I'd add a current netname to copper objects 132 150 132 250 Or something like this. Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Christmas wishlist
On Sat, 25 Dec 2010 10:10:16 +0100 Stephan Boettcher wrote: > > Merry Christmas! Same to you and to the community! > == PCB wishlist == > > The recent (and some not so recent) discussions made me think about > how development of PCB could proceed to solve some of the feature > request, in a future-proof way. This is what came up in my mind. > > === Make all layers explicit === > > Everything shall be layers. Silk, paste, mask layers shall be exlicit. > > Via-layers typically only contain filled circles, the holes. A > via-layer defines to which subset of other (copper) layers it connects > to. A Via is a hole on a via layer plus copper circles on all copper > layers. Vias-layers will probably not be implememted before macros > (below) are available. Until then, they may be special case macros, > like they are now. > > The old layergroup mechanism will be replaced by defining for a copper > layer to which other layers it electrically connects, in the same way > as a via-layer does. > > File format/connectivity does not require different layer types. > There is no difference between via-, copper-, graphical layers. Layer > types steer footprint import, routers, drc, ... Those can be > arbitrary attributes, understood by the respective HID engines. Yes. That would be nice > === Make elements small layouts === > > An element shall be defined as a small layout, same syntax, same > semantics. A pin/pad shall be an attribute on any piece of copper > (which may then be drawn dark gray by the HID). > > On footprint import, some layer mapping needs to happen, so that > generic pads and pins appear on and connect to the right layers. I like this idea. Then, there would be only one file format. In the same way, we could import other PCBs to e.g. a panel pcb. Only grouping needs to be implemented. The same way, we could define padstacks as well. > === Introduce the concept of classes/macros === > > A macro is a sub-layout that can be instantiated at a higher level, > positioned and rotated. > > Footprints and via-stacks are defined as macros. A via is defined as a > via-stack macro instance, an element initially typically contains a > single footprint macro instance. The HIDs will implement Copy-On-Write > by default, so we can still change individual vias, pads, ... Or > descend into the hierarchy, and edit the macro. > > COW can either create a new macro (default for Vias?) or copy the > macro contents into the Element. Yes! > === Hierarchical layout === > > Elements may contain Elements. Either with hierarchical netlist, or > with flattened refdes, like gnetlist generates. When the higher level > elements are defined as macros, a fully hierarchical layout is > possible. > > === Convert the internal units from decimil to nanometer === > > Start by defining a variable (=254e-9), and make all output HIDs use > that to convert to PS-point or gerber units or whatever. Then > introduce attributes of the layout file which sets the internal units > and the default unit of the file. Use 64bits integers. > === ASIC HID === > > When all that is implemented, an HID(-mode) optimized for chip design > is only a small step. Well, I'd focus on PCB layout for the first time. Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: overlapping via changes
On Sun, 19 Dec 2010 22:12:30 -0500 DJ Delorie wrote: > > I changed the "overlapping vias" test in two ways... > > 1. Via copper is now allowed to overlap when vias are created. Via >*drills* are not. > > 2. Vias which violate this rule in a *.pcb file are preserved at load >time. > > Thus, PCB will make a modest attempt at preventing users from making > vias that might be difficult to manufacture, but if the user finds a > way around the restriction, PCB will let them get away with it. > Simply moving an existing via is an adequate way around it. I think this should trigger a non-copper DRC error. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Random thoughts on the future interface of PCB
On Thu, 9 Dec 2010 14:45:47 +1100 Stephen Ecob wrote: > Boiling it down greatly, Clif and Kaimartin are both asking for more > attention from the maintainers. Has the gEDA community given thought > to the possibility of paid maintainers ? I'm a relative newbie, > please let me know if this has already been thrashed through. If it > is worth discussing, I guess the big questions are: > 1. Would any of the existing maintainers be able to devote more time > to gEDA if they had financial support to do so ? > 2. Could we raise enough money to make this viable ? Why don't we put banners to our webpage: "We need developers!" "We need contributors!" or something like that. There might be some out there, who would spend more time on the project. I've seen this on other FOSS pages. Just an idea. -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Clearance in fiducials & blocking solder paste
Hi, Attached is a fiducial example. Enjoy! -- Levente Kovacs http://levente.logonex.eu fidu.fp Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: coordinates and angles of the components
On Thu, 02 Dec 2010 15:44:34 -0500 Rick Collins wrote: > I'm not asking about the pick point. I'm asking about the > centroid. They are completely different things. As I think I said, > the centroid is to tell the assembly house where to put the > part. The pick point is a point on the part where the machine will > attach the nozzle and has nothing to do with the position where the > part is to be placed. Further, regardless of how you set your files, > the pick point is selected by the assembly house to optimize how they > pick the part. You have no way of knowing where this will be. That is good news. > The centroid needs to be a spot on the part that everyone knows > without requiring it to be explained. Unfortunately for oddly shaped > parts, it does not seem to be well understood how to select the > centroid. One document I have from "Screaming Circuits" says it is > the center of the part including the pins and the body. I have yet > to be able to find this info in an IPC document. The IPC document > seems to leave out some other important info about rotations. You > would think they would figure out this is a problem and fix it... > > I can't say if your centroids will give you trouble, but from what > you are telling me, you are not defining them correctly. From what I > have read, I'm not sure PCB does it correctly either. I found some > references on the web that says they use the geometric center of the > pins not including the package. I don't think that is right. > > Screaming circuits is not the ultimate reference for defining how > this is to be done, but they have a document that covers all the > bases and is easy to understand. In fact, when I pointed out that > they had a discrpancy with the IPC docs, they immediately fixed it > and put the updated doc on their web site. www.screamingcircuits.com Okay. Thank you for pointing out all that. I think I'll be fine with the centroids. It states that the centroid must be the center of the entire footprint. It gave me some information about the rotating angle. I go and tweak my script. Thank you again, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB vs. cursor position
On Thu, 2 Dec 2010 14:41:01 -0500 DJ Delorie wrote: > src/file.c > WritePCBDataHeader() Thanks -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: coordinates and angles of the components
On Thu, 2 Dec 2010 12:40:39 -0500 DJ Delorie wrote: > So change it :-) I rather write scripts than modify the source... Please note that my script now calculates placement angles as well! :-) -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB vs. cursor position
On Thu, 2 Dec 2010 12:40:53 -0500 DJ Delorie wrote: > Aside from editing the sources? No :-P Okay... :-) Cold you tell me any point where to look? Thanks... Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: coordinates and angles of the components
On Thu, 02 Dec 2010 12:21:00 -0500 Rick Collins wrote: > If the XYRS file output does not output proper centroids, I see this > as a major issue. If they are not outputting the correct value for > asymmetric parts, how do you see the centroid being defined exactly? Most of my footprints are generated, and the zero point is the center of the package. I think they are OK for pick point. There are other footprints, which I made manually. In that case, I imagine the best pick point and I put the zero point there. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: coordinates and angles of the components
On Tue, 30 Nov 2010 12:22:43 +0100 Kovacs Levente wrote: > I have to put one of my boards into mass production. The factory > require a text file which includes the coordinates of the SMDs, and > their angle. The zero point must be at the lower left corner. > > I know the XY output of PCB, but it messes up the components with > asymmetric pin layout (for example a SOT223 package). > > My wish would be to have some script which calculates the angle as > the XY exporter, and simply put the coordinates of the component to > the output file. > > Has anyone made such script? It would be great help. Answering to my own email... Thanks to open formats, I did it in an hour. The script searches for a special footprint (attached), and takes its position as reference. -- Levente Kovacs http://levente.logonex.eu refpoint.fp Description: Binary data gen_element_coords.pl Description: Perl program ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: creating new symbols
On Mon, 29 Nov 2010 19:34:36 +0100 Michał Dwużnik wrote: > there's no visible clue in case of such error - segfault > does not seem very elegant... You should file a bug report on SF project page. gEDA should not crash. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist crash
On Sat, 13 Nov 2010 14:38:57 +0100 Patrick Bernaud wrote: > Have you built gnetlist from release sources (tarballs) or from a git > checkout? The issue with malformed attributes should have been fixed > with commit 019990c. It was a release. (version 1.6.1.20100214) Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist crash
On Sat, 13 Nov 2010 13:07:23 + Peter TB Brett wrote: > Could you please post a bug to the bug tracker, so we don't > forget about this? Sure... -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist crash
On Sat, 13 Nov 2010 11:24:06 +0100 Patrick Bernaud wrote: > Could you please post the files of your project (directly to to the > list or in private to the address above if you prefer)? Ok, I solved the problem. The problem was that there was an empty "value" attribute attached to one of my symbol. That is bad, but gnetlist should not crash. Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist crash
On Sat, 13 Nov 2010 01:19:18 +0100 Levente Kovacs wrote: > I'm trying to build gEDA from sources. I successfully installed it, > but it keep searching for *.scm files in old places. When I run > gnetlist I get: > > Invalid path [/usr/share/gEDA/bitmap] passed to bitmap-directory > Loading schematic > [/home/leva/git/lbus/hardware/concentrator/if_card/sch/if_card.sch] > Loading schematic > [/home/leva/git/lbus/hardware/concentrator/if_card/sch/ps.sch] Failed > to read init scm file [/usr/share/gEDA/scheme/gnetlist.scm] Failed to > read drc2 scm file [/usr/share/gEDA/scheme/gnet-drc2.scm] > > How can I get the system to find the /usr/local/* stuff? Ok, this is solved. There was some stuff left over from the former installation of gEDA. Now... back to the story. It is a hierarchical design. Now I run the following: gdb --args /usr/local/bin/gnetlist -v -g drc2 -o drc2_out.txt if_card.sch ps.sch and I get some very funny output: GNU gdb (GDB) 7.0.1-debian Copyright (C) 2009 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "x86_64-linux-gnu". For bug reporting instructions, please see: <http://www.gnu.org/software/gdb/bugs/>... Reading symbols from /usr/local/bin/gnetlist...done. (gdb) run Starting program: /usr/local/bin/gnetlist -v -g drc2 -o drc2_out.txt if_card.sch ps.sch [Thread debugging using libthread_db enabled] Loading schematic [/home/leva/git/lbus/hardware/concentrator/if_card/sch/if_card.sch] Loading schematic [/home/leva/git/lbus/hardware/concentrator/if_card/sch/ps.sch] -- Verbose mode legend n : Found net C : Found component (staring to traverse component) p : Found pin (starting to traverse pin / or examining pin) P : Found end pin connection (end of this net) R : Starting to rename a net v : Found source attribute, traversing down ^ : Finished underlying source, going back up u : Found a refdes which needs to be demangle U : Found a connected_to refdes which needs to be demangle -- - Starting internal netlist creation C CpPnnPpPPpPPpnnPpnnPpnnPpnnPpnnPpnnPpnnPpnnPpnnPpnnPpnnP CpnnP Cpn nP CpnnP CpnnP CpnnPpnPpnnPpnnPpnnPpnPpnnPpPPpPnPpPnPpPnPpnn nnPpPpP CpnnP CpnP CpnP CpnPpnnnPnnP CpnPpnnnPnnP CpnP CpnP CpnP CpnP CpnnP Cpnn P CpnnP CpnnP CpnnPnP CpnP CpnP CpnPpnnPnP CpnP CpnPpnPnPpnnPpnnPpnnPpnP CpnnP Cpnn P CpnnP CpnP CpnP CpnnPpnPnP CpnnP CpnPpnPpnPpnnPPnPpPPpPP CpnPpnnPn nP CpnPpnnPnnP CpnP CpnP CpnP CpnP CpnP CpnnPpnPpnPpnPpnnPnPPpPpPpnPpnPp nnPnPPpnnPpnPpnPpnPpPpPpnPpnP CpnnP CpP CpP CpnnPpnnnPPP C pnnPpnnP CpnnP CpnnPpPpnnPpnnnPPpnnP CpnP CpnP CpnP CpnP CpnP CpnP CpnnPPnnPnP nPnPPnPpnnPPnnPnPnPnPPnP CpnnPPnnPnPnPnPPnPpnnPPnnPnPnPnPPnP CpnnPPnnPnPnPnPPnP pnnPPnnPnPnPnPPnP CpnnnPPPnnPnPnPPnPpnnnPPPnnPnPnPPnP CpnnnPPPnnPnPnPPnPpnnnPPP nnPnPnPPnP CpnnnPPPnnPnPnPPnPpnnnPPPnnPnPnPPnP CpPPPnPnPnPPnP CpPPPnPnPnPPnP CpP CpnnP CpP CpnnPpPpnnPpPpnnPpPpnnPpnnPpnnPpPnPpnn nnPnPpnPpnPpnP CpnPpPnP CpnPpPnP CpnPpPnP CpnPpnnPnnP CpnP CpnP CpnP CpnP CpPnPpPnPpnnPnnPpPnPpPnPpPnPpnPpnPpnPpnPpnPpnP CpnP CpnP Cpn nP CpnnP CpnnP CpnnP CpnnnPPPnnPnPnPnPPpnnnPPPnnPnPnPnPP CpnnPPPnnPnPnPnPnPpnnPPPn nPnPnPnPnP CpP CpnP CpnP CpnP CpnnP CpnnP CpnnP CpnnP CpnnP CpnnP CpnnP CpnnP CpnP CpnP CpnP CpnP DONE - Starting internal netlist creation CpnnnPPnPnnPpnnnPPnP CpnnPnPnPpnnPPnP CpnnPnPnnPnP CpnnPPnPpnnPnPnnPnP CpnnnPnPpn nPnPP CpnnPPnPnPnPpnnnPnPpnnnPpnnPpnnnPnPpPnPnPnnnpnnPPnPnPnPp PPnnnPnPnP CpnnPpnnnPnP CpnnPPnPnPnPpPnPnPnnn CpnnPpnnnPnP CpnnnP pnnnP CpnnnPnPpnnPPnP CpnnPnPnP CpnnP CpnnnPPnPpnnnPPnPnnP CpnnP CpnnnP CpnnP CpnnP Cp nPpnP CpnP CpPPnPnPpnP CpPPnnnPnPnPpPnPnPnnn CpPPnnnPnPnPpnnn nPnPnPnnn C CpnPpnPpnPpnPpnPpnPpnPpnPpnPpnPpnPpnPpnPpnPpnPpnPpnPpnPpnPpnPpn PpnPpnPpnPpnnnPnPnPnPnPnPpnnnPnPnPnPnPnPpnnnPnPnPnPnPnPpnnnPnPnPnPnPnPpnnnPnP nPnPnPnPpnnPnnPnPnPnPnPpnPpnP CpnPpnPpnnPpnPpnnPpnnPpnnPpnPpnPpnPpnnPpnnPpnnPp nnPpnnPpnnPpnnPpnnPpnPpnPpnPpnPpnPpnPpnnnPnPnPnPnPnPpnnnPnPnPnPnPnPpnnnPnPnPn PnPnPpnnnPnPnPnPnPnPpnnnPnPnPnPnPnPpnnPnnPnPnPnPnPpnPpnP CpnnnPnPnPnPnPnP CpnnP CpnnP CpnnP CpnnP CpnnP CpnnP CpnnP CpnnP CpnnP CpnnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnnnPnPnPnPnPnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP C pnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnP CpnnPpnnPpnnPpnnPp nnPpnPpnPpnPv - Starting internal netlist creati
Re: gEDA-user: gnetlist crash
On Fri, 12 Nov 2010 23:53:06 + Peter TB Brett wrote: > On Friday 12 November 2010 23:37:18 Levente Kovacs wrote: > > Hi all, > > > > > > I could make gnetlist crash with the following command: > > > > gnetlist -q -g gsch2pcb -o pcb/if_card.new.pcb -m gnet- > gsch2pcb-tmp.scm > > sch/if_card.sch sch/ps.sch > > Hi, > > Are you able to narrow it down to a minimal testcase at all? > > Also, the stack trace would be more helpful if you installed the - > dbg packages for libguile and libc. I'm not sure how to do that on > Debian, I'm afraid. > > Thanks! I'm trying to build gEDA from sources. I successfully installed it, but it keep searching for *.scm files in old places. When I run gnetlist I get: Invalid path [/usr/share/gEDA/bitmap] passed to bitmap-directory Loading schematic [/home/leva/git/lbus/hardware/concentrator/if_card/sch/if_card.sch] Loading schematic [/home/leva/git/lbus/hardware/concentrator/if_card/sch/ps.sch] Failed to read init scm file [/usr/share/gEDA/scheme/gnetlist.scm] Failed to read drc2 scm file [/usr/share/gEDA/scheme/gnet-drc2.scm] How can I get the system to find the /usr/local/* stuff? Thanks, Levente > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gnetlist crash
Hi all, I could make gnetlist crash with the following command: gnetlist -q -g gsch2pcb -o pcb/if_card.new.pcb -m gnet-gsch2pcb-tmp.scm sch/if_card.sch sch/ps.sch backtrace: #0 __strcmp_sse2 () at ../sysdeps/x86_64/multiarch/../strcmp.S:99 #1 0x77b97bad in g_get_attrib_value_by_attrib_name () from /usr/lib/libgeda.so.38 #2 0x778c1f1c in ?? () from /usr/lib/libguile.so.17 #3 0x778c15e4 in ?? () from /usr/lib/libguile.so.17 #4 0x778c1b68 in ?? () from /usr/lib/libguile.so.17 #5 0x778c4456 in scm_eval () from /usr/lib/libguile.so.17 #6 0x77913c9f in scm_c_catch () from /usr/lib/libguile.so.17 #7 0x77b9437d in g_scm_eval_protected () from /usr/lib/libgeda.so.38 #8 0x004072d0 in ?? () #9 0x00405661 in ?? () #10 0x00407359 in ?? () #11 0x0040749e in ?? () #12 0x00404488 in ?? () #13 0x778d7dff in ?? () from /usr/lib/libguile.so.17 #14 0x778ae93a in ?? () from /usr/lib/libguile.so.17 #15 0x77913c9f in scm_c_catch () from /usr/lib/libguile.so.17 #16 0x778aedab in scm_i_with_continuation_barrier () from /usr/lib/libguile.so.17 #17 0x778aee40 in scm_c_with_continuation_barrier () from /usr/lib/libguile.so.17 #18 0x77912d04 in scm_i_with_guile_and_parent () from /usr/lib/libguile.so.17 #19 0x778d7db5 in scm_boot_guile () from /usr/lib/libguile.so.17 #20 0x00403ef3 in ?? () #21 0x77032c4d in __libc_start_main (main=, argc=, ubp_av=, init=, fini=, rtld_fini=, stack_end=0x7fffe478) ---Type to continue, or q to quit--- at libc-start.c:228 #22 0x00402839 in ?? () #23 0x7fffe478 in ?? () #24 0x001c in ?? () #25 0x000a in ?? () #26 0x7fffe732 in ?? () #27 0x7fffe744 in ?? () #28 0x7fffe747 in ?? () #29 0x7fffe74a in ?? () #30 0x7fffe753 in ?? () #31 0x7fffe756 in ?? () #32 0x7fffe76a in ?? () #33 0x7fffe76d in ?? () #34 0x7fffe783 in ?? () #35 0x7fffe793 in ?? () #36 0x in ?? () I'm on Debian testing. I can send schematics on request. gEDA/gschem version 1.6.1.20100214. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Enhancements for gEDA/pcb G-code export
Hi, I've exported some g-code from one of my former projects as a test. I don't have a milling machine, but I'd like to see the result. Could you please point me a g-code viewer for Linux? Preferably debian. Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: coordinate systems
On Sun, 17 Oct 2010 23:22:05 +0200 Markus Hitter wrote: [...] I consider myself a geek, who doesn't mind editing text files, etc, however, I see your point, and I think you've got it right. Anyways... attached is my gpcb-menu.res, which addresses the panning problem. :-) Levente -- Levente Kovacs http://levente.logonex.eu gpcb-menu.res Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: coordinate systems
On Sun, 17 Oct 2010 21:07:18 +0200 kai-martin knaak wrote: > There are two ways ;-) > > 1) activate solder mask > 2) let the mouse hover over the object you want to manipulate > 3) type [k] to increase and [shift-k] to decrease the mask distance > > Alternatively: > > 1) activate solder mask > 2) select the objects you want to manipulate > 3) type [:] to open the command window > 4) type >ChangeClearSize(Selected, value, unit) > where a signed value will be an increment/decrement, and > unit may be mil, or mm Both examples work on a footprint placed on a layout. I am talking about a footprint itself. Off course, you can copy a footprint into the buffer, rip up, edit, convert it back again to a footprint, copy to buffer, and overwrite the old one. Yes, I use VI to edit the soldermask openings. :-) A footprint mode is okay with me. I am thinking about a script that can run through my footprints and modify such parameters like soldermask opening and keepaway, etc. in one go; controlled by my Makefile system. We'd need such tool as well, regardless of the ability of PCB itself. P.S.: tell me, if there any script that does today... Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: coordinate systems
On Sun, 17 Oct 2010 20:28:36 +0200 kai-martin knaak wrote: > > http://reprap.org/wiki/PCB_Milling#gerbv > > "gEDA is yet another software suite with schematic and PCB layout > > editor. It wasn't included in the set of preferred choices here > > because it requires hand-coding of text files in between usage of > > the different GUI tools." > > Actually, it does not. > You can do the whole work-flow in GUI-mode only. You can use > xgsch2pcb or the shiny new pull feature of pcb to eliminate the > command line, too. That said, sometimes it is just easier to tweak > the *.sch, or *.pcb files than use the GUIs. Well, take a footprint for example. How do you edit the solder mask opening with the GUI? I don't think there is a way to do that with the GUI. So it is someway true, that hand editing is necessary. You can do it with scripts, yes. But that involves hand editing as well. IMHO, we'd need a footprint editor as well. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: coordinate systems [was: pcb crooked traces]
On Sun, 17 Oct 2010 11:02:03 -0400 Phillip Jones wrote: > Mainly because that has been the standard at least since Televisions > were invented. The beam in a CRT scans from left-to-right, > top-to-bottom. It's codified in the NTSC standard. So (x,y)=(0,0) is > the upper left corner. Why are CRT's like this? Probably because words > in books are also oriented left-to-right, top-to-bottom. Maybe if the > television had been invented in the middle-east it would be different. > I've got several digital image processing books on my shelf, the > oldest is from 1972. Every one of them defines (x,y)=(0,0) as the > upper left corner of an image. y as positive down, and x as positive > right is simply the de-facto standard in digital image processing. I think that is why X11 has its coordinate system as is; and that is why PCB developers went that way. But a CAD tool is not about CRT display or image processing. I think we should change it; it looks very awkward for a new user, who doesn't know the story. Just my EUR0.02 Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Sun, 10 Oct 2010 09:04:13 -0700 Andrew Poelstra wrote: > Plus, floating point is scary. That's a real argument, because it > affects developer confidence in the code, confuses analysis, and > might discourage future developers. +1 With int, you know what is going on behind the scenes. It is not true with any floating point value. I always try to avoid floats. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Fri, 8 Oct 2010 14:55:10 -0400 DJ Delorie wrote: > Yes, but there's a loss of performance if you do that. So, I'd put there a compiling option like 'enable huge boards (might be slow on 32bit systems) Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Fri, 8 Oct 2010 14:08:12 -0400 DJ Delorie wrote: > Files are text, no problem there. The routines that *read* files need > to parse them as 64-bit integers always, but we can complain if (1) > they don't fit in 32-bit and (2) PCB is built for 32-bit. Thus, > people who need more than 2 meter boards can just rebuild pcb and get > past the errors, but people who don't won't have subtle errors. Please forgive my ignorance, but can't one just define a 64bit integer on a 32bit system? I defined 32bit integers on a 8bit system with no problem. (atmel AVRs) Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
Ok, I dont really think that PCB has to have the ablity to handle a house, or kitchen in terms of length. > Yes. Set the scale-factor to 1000, and now your "base-unit" is um, > in that the smallest PCB object you can make will be scaled to a > micrometer, and you can have 2km boards if you want. Basically, I like this idea, but something tells me to stick to some unit. Let's say 10nm, which is OK for inch and mm; and you have 20m total board size, wich is more then enough. Even for a small kitchen. :-) Personally I'm okay with 2m as limitation. (my kitchen is ready, and I have a 64bit system :-)) Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Fri, 08 Oct 2010 10:31:10 -0400 Rick Collins wrote: > Personally, I can't imagine a PCB larger than 2 meters much less 4 > meters. Or is the possibility of uses other than PCB design being > considered here? I ended up designing my kitchen layout using PCB. I started with QCAD, gave a try for SweetHome (for java), and IKEA's tool. I realised that PCB was good for the job. Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Tue, 7 Sep 2010 17:08:18 -0700 Andrew Poelstra wrote: > On Tue, Sep 07, 2010 at 07:24:38PM -0400, DJ Delorie wrote: > > > > > Sounds nice -- could come from DJ upgrading GTK functionality. > > > > I was hoping someone else would do the GTK stuff :-) > > > > I'm working on cleaning up the Gtk code - well, refactoring > gui-top-window.c, anyway. Hopefully I'll be able to get things into a > top-down sorta structure that can be easily mapped to C++. > > The hard part is untangling the Gtk code from the HID action-passing > code. > > Plus, I don't have a clear understanding of what "mapped" and > "allocated" and "realized" mean in Gtk terms. Does anyone know of a > good overview of Gtk+? > > > Andrew I'd make the left pane of the GTK HID somehow optional. I'd implement it with a toolbox(es). We should think about the fact, that tear-off menus will disappear from GTK+ 3.x. :-( Levente > ___________ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Tue, 07 Sep 2010 22:41:25 -0500 John Griessen wrote: > How about a menu item that loads the .pcb file in your favorite > editor, and when that is done, reverts to file contents? If I recall correctly, that is why I added the File->Revert function. I use it to explicitly load the pcb from the filesystem. -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB format wishlist
On Mon, 6 Sep 2010 12:57:59 -0700 Andrew Poelstra wrote: > Or, could we base everything off of lines, attach a 'curvature' > property to create arcs, and build polygons from that. I woldn't do that. The file would end up consisting of the same stuff. It's like you could only have points. I think we should define primitives as the most commonly used shapes in pcb layouts. I prefer line, polygon, circle, arc. Why arc and circle are not merged? Because the diameter of the arc is the center of the bent line; however, the diameter of a circle is the edge. And of course we have to implement padstacks at the footprint level. Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Color silk layers in pcb
On Sat, 4 Sep 2010 11:24:38 + Ineiev wrote: > Probably this patch may be used as a workaround. Why don't we just push this patch to HEAD? This works just great. Thanks, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: crosshair snaps to pins and pads... on locked component
On Thu, 2 Sep 2010 16:03:55 -0400 DJ Delorie wrote: > What a coincidence. We were just discussing that on IRC. > > I think snap-to-locked is OK, but I want locked *elements* to be > ignored. I have one design that has a big LCD covering up all my > other parts, it's really hard to edit when every operation tags the > LCD instead of the parts under it. What a coincidence. I am editing a board right now with a big LCD covering it all! :-) Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: crosshair snaps to pins and pads... on locked component
Hi folks, I just can't figure out why can't the "Crosshair snaps to pins/pads" work when the component is locked. As far as I know, locking a component is for to lock the position of the component. I think it would be nice when anything could be done with a locked component except accident move. Anyone? -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: git HEAD PCB now supports user-defined holes in polygons
On Mon, 07 Jun 2010 00:38:16 +0100 Peter Clifton wrote: > git HEAD PCB now supports user-defined holes in polygons Hi Peter, This feature is cool. Thank you for implementing it. I found that it makes a funny thing when you move a cutout corner outside the polygon. I wish we could define pads as polygons, so with this feature any kind of pads could be implemented. Solder-mask cut outs would be nice too. Thanks again, Levente -- Levente Kovacs http://levente.logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: im new, soy nuevo
On Tue, 20 Apr 2010 00:10:34 -0400 Dave McGuire wrote: >Jive. > >"I speak Jive!" I dance Jive! -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB template?
On Tue, 20 Apr 2010 13:18:47 -0400 Jim wrote: > I am designing a couple of boards (if successful more than 2) that > have the same "form factor". That is they are the same physical size > and both (all) have fingers to plug into a card slot on a mother > board. So I don't have to worry about registration of the fingers > each time I come up with a new board, is there a way I can define a > PCB template that includes the fingers? That seems like it would be > hard to do since the fingers are a connector on the schematic and > wouldn't line up right without some tricks. The other option might > be if there were a command line to PCB that I could execute to tell > it "put pin 1 of conn1 at X, Y". Or would it be best to have a > template that has a target in silk to line the fingers up? > > I'm open to the simplest solution. Recently, I started to draw PCB outlines. This is nothing, but a PCB file. I copy the outline to my project, as pcb_template.pcb. My makefile system recognizes it, and when gsc2pcb is run, it'll automagically add the components to the board. The template pcb file is copied to the right place, and right name, etc. Here you can browse the templates: http://git.logonex.eu/?p=library.git;a=tree;f=electronic/outline;hb=HEAD The only useful stuff is probably the PCB for the 3U subrack Eurocard system. My Makefile system is available here: http://git.logonex.eu/?p=svn.git;a=tree;f=pskel;h=b4b690134e55b35ee0882140ff3770225c5228ee;hb=HEAD and here: http://git.logonex.eu/?p=svn.git;a=tree;f=scripts4geda;h=28030ab03ab4f2df9dbbe5adb380f5de46cc7c6d;hb=HEAD Enjoy, Levente -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gnetlist
Hi, I can't find any documentation about the hierachy support in gnetlist http://geda.seul.org/wiki/geda:gnetlist_ug#hierarchy_support Is there any documentation about hierarchy support? Is there any way to create PCAD netlist with gEDA? Thanks, Levente -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: paid help?
nd > >> footprints, I don't think anyone would have a problem with someone > >> promoting their own services and rates on their gedasymbols page. > >> > >> Perhaps what we need is a bounty system? Someone posts an URL for > >> a part's spec sheet and how much they're willing to pay. > >> Contenders post screenshots of the symbols and footprints they > >> come up with, and one is chosen to get the bounty and submit their > >> data files to the community. > > > > The single most important thing is to fix gschem so that it doesn't > > lead users into the unproductive trap of referencing unmodified > > library symbols in designs. Then maybe we can escape from the > > delusion that what's primarily needed is a bigger library. > > > > Don't get me wrong: I think publishing symbols is great. > > gedasymbols.org is a great resource, and indeed I have thrown a > > bunch of symbols into the pot there over the last few days. > > Starting with a symbol that's as close to what you need as possible > > is always best. But publishing symbols cannot solve the fundamental > > problem: "as close as possible" rarely means "exactly". > > > > John Doty Noqsi Aerospace, Ltd. > > http://www.noqsi.com/ > > jpd-eogpokeig7iavxtiumw...@public.gmane.org > > > > > > > > > > ___ > > geda-user mailing list > > geda-user-3olirty5fqqavzljymc...@public.gmane.org > > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > > > > > ___ > geda-user mailing list > geda-user-3olirty5fqqavzljymc...@public.gmane.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: paid help?
Hi, Well, I am lazy, and that is why I create my own library. I am lazy, so I don't upload it to gedasymbols.org. But it is availabel through my git server! :-) http://git.logonex.eu/?p=library.git;a=tree;f=electronic;hb=HEAD Enjoy! Levente On Tue, 06 Apr 2010 07:59:06 -0400 Patrick wrote: > Hi Everyone > > This is my first post here, I am also very, very new to PCB design. > > The last thing I want is to create another flame, Eagle vs geda > etc... but am I basically correct that the proprietary Apps have more > libraries and this is the main drawback of the open source alternates? > > If this is so, is there someone who has or would like to start a > small business filling in these libraries on a 'on demand" basis? > > I really want open source to grow, I feel like sending $100 or $1000 > to the Eagle people is feeding the enemy. If I sent this money to an > open source developer to fill in the gaps for me, would I not end up > with what I want and in turn help to make something good grow? > > If this is logical could I get some very rough guess-ti-mates of what > this would cost? If I had a board with let's say 10 chips unsupported > by geda how much would it cost to add them. > > Thanks for reading-Patrick > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB won't compile
On Thu, 18 Mar 2010 15:31:31 +0100 Patrick Bernaud wrote: > Hello, > > Kovacs Levente writes: > > [...] > > hid/lesstif/menu.c: In function ?lesstif_call_action?: > > hid/lesstif/menu.c:856: error: ?x? undeclared (first use in this > > function) hid/lesstif/menu.c:856: error: (Each undeclared > > identifier is reported only once hid/lesstif/menu.c:856: error: > > for each function it appears in.) hid/lesstif/menu.c:856: > > error: ?y? undeclared (first use in this function) > > > > Change the line to read: > ret = current_action->trigger_cb (argc, argv, px, py); > instead of: > ret = current_action->trigger_cb (argc, argv, x, y); Later, I figured it out. I don't know what is the current state of the contribution for gEDA/PCB, but attached is a patch to fix this issue. Levente -- Levente Kovacs http://logonex.eu diff --git a/src/hid/lesstif/menu.c b/src/hid/lesstif/menu.c index 9869483..44edaba 100644 --- a/src/hid/lesstif/menu.c +++ b/src/hid/lesstif/menu.c @@ -853,7 +853,7 @@ lesstif_call_action (const char *aname, int argc, char **argv) old_action = current_action; current_action = a; - ret = current_action->trigger_cb (argc, argv, x, y); + ret = current_action->trigger_cb (argc, argv, px, py); current_action = old_action; return ret; ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open Source mechanical CAD on the horizon
On Fri, 26 Feb 2010 01:58:18 + Peter Clifton wrote: > I met with the LiquidPCB developer today, and he's been working on a > STEP importer.. so there might be some possible overlap there. > > He also mentioned that he has a DXF outline -> (geda-)PCB converter, > which he would make available if anyone wanted it. I've wrote some C++ code to convert a DXF to PCB. It is in "works for me" state. Levente -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new components
Hi, I have a bunch of symbols here: http://logonex.eu/git/?p=svn.git;a=tree;f=gschem-sym;h=a684be6d0dc98a94e7d8ea092972e18f4a9cdce4;hb=90743ea21068a0c473ce71da1fd457353310ccf4 and a bunch of footprints here: ttp://logonex.eu/git/?p=svn.git;a=tree;f=levalib;h=f13a688b8f588acff7f081ac95999259bb0c01d2;hb=90743ea21068a0c473ce71da1fd457353310ccf4 feel free to pick anything you want. On Tue, 2 Feb 2010 08:32:51 -0500 Chris Cole wrote: > Hey all, > I'm new to the gEDA community (and fairly new to electronics in > general), and I have a pretty simple question for the gurus. I was > working on converting a PIC project schematic into gschem when I > realized that none of the Microchip IC's I was using were in the > component library. What's the standard procedure for this? Is it > easier to mooch off an existing part or to create your own? > > Thanks, > Chris > -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: flags
On Fri, 18 Sep 2009 21:01:52 +0400 Ineiev wrote: > BTW, what about adding attributes to layers, too, e.g. to specify > distinct design rules for particular layes? Or something like "mechanical", or "Inhibit_zone" etc. BTW, it would be nice to have the functionality behind them... -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: configure: error Couldn't find Xaw library
On Sun, 30 Aug 2009 07:09:52 -0700 (PDT) FRANCISCO ESPINOLA wrote: > I am trying to install geda in caelinux (pc linux) > and the configure give me the following error > > > configure: error Couldn't find Xaw library > > I find out that I have > /usr/lib/libXaw8.so.8 > /usr/lib/libXaw3d.so.7 > /usr/lib/libXaw.so.8 > > etc... Make sure you install the *-dev packages too. Cheers, Levente -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Appeal for transations
On Mon, 10 Aug 2009 15:11:50 +0100 Peter TB Brett wrote: > We'd really appreciate it if any of you who are able to speak > languages other than English would be kind enough to head towards the > Launchpad translations page [1] and spend an hour or two translating! Ok, I'm gonna spend some time on a train, so I'll bring my notebook, and do some Hungarian translation. Cheers, Levente -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: placing a connector footprint "out" of a board
On Sun, 2 Aug 2009 20:33:15 +0200 Oliver Lehmann wrote: > Hi, > > I made my first PCB ever - and I did it with PCB ;) Well done! > I've one question. I use a 3*32pin connector and I have problems with > placing it properly. I sized the board with the exact dimensions I > need, but I need to have the connection side of the connector "out" > of the board. This is not possible as far as I can see. I now made > the board a bit bigger to have the connector placed properly. I then > drew a brown line (component layer) to mark where the board should > end: The connector you are using is the standard eurocard connector. This system exactly specifies the place of the connector. I have this drawn as an empty board. I use the "outline" layer to specify the board contour. Just grab my PCB file to see what I did. It can be found here: http://logonex.eu/cgi-bin/viewvc.cgi/outline/eurocard_3U/eurocard_3U.pcb?view=co On the right side, there is a vertical line on the silk layer. There are other crossing lines. The crossing coordinate indicates pin 1. See this example of a complete board of mine: http://logonex.eu/cgi-bin/viewvc.cgi/lbus/concentrator/if_card/pcb/if_card.pcb?view=co Happy soldering! Levente -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: dsn exporter
On Sun, 26 Jul 2009 12:46:48 -0700 (PDT) Josh Jordan wrote: > This exporter outputs a .dsn file for opening with freeroute.net. It > only works on 2 layer designs so far. I searched google about this file format, and found that it has something to do with OrCAD. Does that means that I can export my gPCB layout to OrCAD format? If that is the case, it would be hilarious, hence at my day job I'm forced to use OrCAD, what I don't want. If I had a converter, I could hide all my gPCB works behind it! ;-) > I did not start writing an importer for it yet, if anyone has > suggestions on the architecture of this I will listen. (.cmd file?) > I will be out of town for the next 10 days and then I will work on > the importer. > > To install it, make a specctra directory in the hid directory, put > this file in it, a copy of hid.conf, make a change to makefile.am > in /src, and make install again. > > > > -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: board stacking
On Tue, 7 Jul 2009 18:34:42 -0700 Steven Michalske wrote: > Full ACK, spend the time making male and female footprints, > otherwise your going to pay another day. > > In the through hole case you might even want to make male and female > front and back side. footgen.py has built in supports for both female and male headers. -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist missing features
On Thu, 02 Jul 2009 14:22:44 +0200 Stefan Salewski wrote: > An other method may be a SPECIAL connection symbol in gschem for > connecting nets. I think that would be a nice solution. You could then add starpoints in power and ground nets. Levente -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: disperse all elements and locked objects
Hi, It would be nice if the "Disperse All Elements" function in PCB was working only on non locked element. I have PCB templates with pre defined mechanical elements, and when I place my electrical elements and say "Disperse All..." it moves away my mechanical things too, which are locked. Undo will move back all elemets to its original place, but the locked elements remain. :-o BTW... a 3U 100x160mm eurocard outline can be found here. http://logonex.eu/cgi-bin/viewvc.cgi/outline/eurocard_3U/eurocard_3U.pcb?view=log and its frontplane scetch... http://logonex.eu/cgi-bin/viewvc.cgi/outline/eurocard_frontplane/8HE.pcb?view=log Cheers, Levente -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb wishes
> That doesn't mean that everyone else has to stop working on the things that > interest/motivate them. True, but I guess the first step should be to remove the rounding errors. Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: footgen.py
Hi,
I've added capability to omit pins at the dip type. This enables to
generate footprints for reed relays.
type = "dip"
omitballs = "3,4,5,10,11,12"
pins = 14
will generate something like that
* *
* *
* *
* *
patch attached.
Cheers,
Levente
Index: footgen.py
===
--- footgen.py (revision 482)
+++ footgen.py (working copy)
@@ -485,15 +485,18 @@
pitch = findattr(attrlist, "pitch")
refdesx = findattr(attrlist, "refdesx")
refdesy = findattr(attrlist, "refdesy")
+omitlist = expandomitlist(findattr(attrlist, "omitballs"))
y = -(pins/2-1)*pitch/2
x = width/2
dipelt = "Element[0x \"\" \"\" \"\" 1000 1000 %d %d 0 100 0x]\n(\n" % (refdesx, -4000 - refdesy)
for pinnum in range (1,1+pins/2):
-dipelt = dipelt + pin(-x,y,paddia,drill,str(pinnum),polyclear,maskclear)
+if omitlist.find("\""+str(pinnum)+"\"")==-1:
+dipelt = dipelt + pin(-x,y,paddia,drill,str(pinnum),polyclear,maskclear)
y = y + pitch
y = y - pitch
for pinnum in range (1+pins/2, pins+1):
-dipelt = dipelt + pin(x,y,paddia,drill,str(pinnum),polyclear,maskclear)
+if omitlist.find(str(pinnum))==-1:
+dipelt = dipelt + pin(x,y,paddia,drill,str(pinnum),polyclear,maskclear)
y = y - pitch
silky = pins*pitch/4
silkx = (width+pitch)/2
___
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Re: gEDA-user: ??Error message PCB??
On Sat, 23 May 2009 17:27:59 +0200 Ernst van Spronsen wrote: > Is the attached footprint correct? If not what I'm doing wrong? It is too a .pcb file. I guess you open your footprint with pcb, and you save it. IMHO, PCB saves it as a .pcb file, regardless of its extension. You have a couple of options: 1. You regenerate your footprint like load it to the buffer, break it to elements, edit, end re-export. 2. You use your favourite text editor to tweak it. Cheers, Levente -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [OFF] high current amplifier
We want to avoid transformers. The older version of this equippment had the good old Quad-405 power amplifiers, and transformers at the end. It is so heave, that one man can hardly lift the unit. Btw... the same unit must also provide a voltage output up to 300V, but only 100Watts. For that, we'll go for transformer. And a plus... multiply everything by 3, hence it must be 3 phase... :-) On Wed, 20 May 2009 11:27:48 -0500 Mark Rages wrote: > On Wed, May 20, 2009 at 11:16 AM, Levente Kovacs > wrote: > > On Wed, 20 May 2009 10:48:53 -0500 > > Mark Rages > > wrote: > > > >> What kind of transient are you trying to simulate? Maybe it would > >> be easier to make a circuit to add the transient to mains power, > >> instead of recreating mains power with an amplifier. > > > > 230V times 100A is something I dont want to even calculate. > > > > -- > > You need a high-current, low-voltage transformer: > > http://www.cooperhandtools.com/brands/CF_Files/model_detail.cfm?upc=037103079480 > > Regards, > Mark > markra...@gmail > -- > Mark Rages, Engineer > Midwest Telecine LLC > markrages-oYGxGvcBBqUZk/wt9ibm20eocmrvl...@public.gmane.org > > > ___ > geda-user mailing list > geda-user-3olirty5fqqavzljymc...@public.gmane.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [OFF] high current amplifier
On Wed, 20 May 2009 09:26:07 -0700 Joerg wrote: > I'd wear eye protection :-) > > I can already picture it, on day a connection comes loose, we all > hear a muffled *BOOM* and see an orange glow over Budapest ... Well... I will do it in Budakalász. :-) But yes, I know it is a crazy toy! :-) -- Levente Kovacs http://logonex.eu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
