Re: gEDA-user: Importing board outline from .emn file
Thanks DJ. I will look into this. If I go the scripting route would Python be ok? For the plug-in route are there some pointers to show how to go about creating a plug-in? On Thu, 2009-02-05 at 00:21 -0500, DJ Delorie wrote: Nothing at the moment, but if it's a documented text file, you could write a script to convert it into pcb's file format - a separate .pcb that just has the outline/keepout layers (keepout isn't supported, but you can create a layer with that name just to hold the outlines). Then use File-Load layout data to import it into the paste buffer. This might be a good case for a plug-in that imports that data, too. Save a couple of cut-paste steps. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Importing board outline from .emn file
Hi Folks, Does anyone know if there is a way to import a board outline defined in an emn file into PCB? The emn file is produced by ProEng 3-D CAD tool and it seems quite simply structured. I have attached it below ... .HEADER BOARD_FILE 3.0 Pro/ENGINEER TM Wildfire 3.0 (c 2009/02/04.13:30:43 3 PCB-DB MM .END_HEADER .BOARD_OUTLINE MCAD 1.2 0 0.0 0.0 0.0 060.0 0.0 0.0 060.030.0 0.0 0 0.030.0 0.0 0 0.0 0.0 0.0 .END_BOARD_OUTLINE .DRILLED_HOLES 3.521.5 16.0 NPTHBOARD PIN MCAD .END_DRILLED_HOLES .PLACE_KEEPOUT UNOWNED TOP 0.0 0 7.8320030.0 0.0 0 7.8320027.99400 0.0 010.8320027.99400 0.0 010.8320030.0 0.0 0 7.8320030.0 0.0 .END_PLACE_KEEPOUT .PLACE_KEEPOUT UNOWNED TOP 0.0 049.1450030.0 0.0 049.1450027.99400 0.0 052.1450027.99400 0.0 052.1450030.0 0.0 049.1450030.0 0.0 .END_PLACE_KEEPOUT .PLACE_KEEPOUT UNOWNED TOP 0.0 010.84300 0.0 0.0 0 7.84300 0.0 0.0 0 7.84300 2.00600 0.0 010.84300 2.00600 0.0 010.84300 0.0 0.0 .END_PLACE_KEEPOUT .PLACE_KEEPOUT UNOWNED TOP 0.0 052.12000 0.0 0.0 049.12000 0.0 0.0 049.12000 2.00600 0.0 052.12000 2.00600 0.0 052.12000 0.0 0.0 .END_PLACE_KEEPOUT .PLACE_KEEPOUT UNOWNED TOP 0.0 0 0.018.87600 0.0 0 0.015.87600 0.0 0 2.0060015.87600 0.0 0 2.0060018.87600 0.0 0 0.018.87600 0.0 .END_PLACE_KEEPOUT .PLACE_KEEPOUT UNOWNED TOP 0.0 057.9940018.88100 0.0 060.018.88100 0.0 060.015.88100 0.0 057.9940015.88100 0.0 057.9940018.88100 0.0 .END_PLACE_KEEPOUT ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I typically deal with this by separating the planes at the schematic level using a bead-core inductor. The two planes are then on different nets at the PCB level. This not only makes it easier to do the routing but they also serve an electrical purpose of isolating the two planes from a high frequency viewpoint, whilst connecting them at DC. On Mon, 2008-10-27 at 16:39 +0100, Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Syntax error in pcb file
Hi Guys, PCB is detecting a syntax error in my .pcb file and failing to open it. The output from PCB Log is as follows... Looking for default_font in . Can't open ./default_font for reading Looking for default_font in /usr/local/bin/../share/pcb Found default_font in /usr/local/bin/../share/pcb ERROR parsing file 'CL0002/board.pcb' line:133 description: 'syntax error' The gtk gui currently ignores grey50as part of a menuitem resource. Feel free to provide patches ghid_load_menus(): Mouse resources are currently ignored by the GTK HID. Please feel free to submit a patch to implement this! Here is the area around line 133 of the .pcb file ... 123 Element[0x0 Biopeak_0603 C2 0.1u 0 0 -7011 -10437 0 100 0x0] 124 ( 125 Pad[-3543 0 -3149 0 3937 2000 4737 input 1 0x0100] 126 Pad[3149 0 3543 0 3937 2000 4737 input 2 0x0100] 127 ElementLine[-7011 3468 -7011 -3468 1000] 128 ElementLine[-7011 -3468 7011 -3468 1000] 129 ElementLine[7011 -3468 7011 3468 1000] 130 ElementLine[7011 3468 -7011 3468 1000] 131 ) 132 133 FileVersion[20070407] 134 135 PCB[ 17100 12400] 136 137 Grid[1000.00 0 0 0] 138 Cursor[0 0 0.00] 139 PolyArea[2.00] 140 Thermal[0.50] 141 DRC[1000 1000 1000 1000 1500 1000] 142 Flags(nameonpcb,uniquename,clearnew,snappin) 143 Groups(1,c:2,s) 144 ++ Anyone got any ideas what could be causing this? I checked another .pcb file that I have with a design that opens ok and it has the following lines ... # To read pcb files, the pcb version (or the cvs source date) must be = the file version FileVersion[20070407] Best Regards, Neil ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Syntax error in pcb file
Thanks This is a fresh pcb file created using gsch2pcb i.e. I have not intervened in any way. Is there something that could be wrong with the schematic to cause this? The pcb file generally looks quite jumbled with Element definition not all in one place. Regards, Neil On Thu, 2008-10-02 at 14:45 -0400, DJ Delorie wrote: 128 ElementLine[-7011 -3468 7011 -3468 1000] 129 ElementLine[7011 -3468 7011 3468 1000] 130 ElementLine[7011 3468 -7011 3468 1000] 131 ) 132 133 FileVersion[20070407] 134 135 PCB[ 17100 12400] You somehow have two files concatenated together. This never works. FileVersion[] should be the first non-comment in the file. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Syntax error in pcb file
Yes that's exactly what I did. I had previously viewed a footprint in PCB in order to measure its dimensions and then I must have inadvertently saved it, which turned it into a PCB file. Thanks for the help in getting to the bottom of this. On Thu, 2008-10-02 at 15:01 -0400, Stuart Brorson wrote: I'll betcha you tried to create a footprint by drawing something using PCB and then exporting your board file into a .fp file, and then placed it into your layout. Or something like that. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Adding extra layer
I have a 10 layer pcb that I have just completed routing. I need to create a board outline with some notches etc and when I try to add an extra layer for the outline I can not, as I am maxed out at the 16 layer limit (i.e. 10 routing layers + silk + rats + pads + vias + far side + solder mask). I have read a couple of posts about a patch and a compile switch to enable extra layers. What is the best approach to achieve this? Regards, Neil ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Connections to ground plane show up as circle
Hi Guys, Just curious if this is a new feature or a bug... When I connect a net to a ground plane. Subsequent Optimize Rats Nest executions show all pins/pads connected to this net as a circular rat line over the pad/pin. It seems like a cool feature (avoids rats nest clutter) but I have never seen it before. Regards, Neil ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Connections to ground plane show up as circle
Nice. I normally would not have even questioned if it was a bug but I am (for the first time) running a new version I have compiled from sources. I must say that the more I use this package; the more impressed I become with the quality of the tool and the support community. Great job! On Tue, 2008-08-12 at 21:12 -0400, DJ Delorie wrote: When I connect a net to a ground plane. Subsequent Optimize Rats Nest executions show all pins/pads connected to this net as a circular rat line over the pad/pin. Feature. Relatively new. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Blind Buried Vias
Hi Steve, Sorry I should have described things better. The non-component side of the board has exposed pads that make deliberate contact with the body for a couple of selected nets on the PCB. All other nets on the PCB (eg power) can not be exposed on this side of the board. I had considered using tented vias to selectively isolate certain vias but I am concerned that this thin insulation layer could scrape off and expose the via. Regards, Neil On Sat, 2008-06-07 at 13:54 -0700, Steve Meier wrote: Neil, If the requirement is not to have the board not make electrical contact with skin, why not put an insulator on the back of the board? There are various types of tapes and even sprayes that can be used to encapsolate one or both sides. Steve Meier Neil Webster wrote: Hi all, I have an application where I am creating a small PCB as the basis of an active electrode. The non-component side of the board is in contact with skin and exposed vias on this side of the board therefore must be avoided. In the previous generation of the design, the circuit was simple enough to allow me to perform routing purely on the top surface. However the new design is significantly more complex and I think I will need to move to a multi-layer board. I therefore need blind vias. The official PCB documentation says that these are not supported. Extract from section 2.2: Each via exists on all copper layers. (i.e. blind and buried vias are not supported) However I did find a number of threads on this topic in the archive, one of which is referenced below. However this was almost 1 year ago and there may have been further developments. http://www.seul.org/pipermail/geda-dev/2006-July/000135.html Is there any way to achieve this with pcb? Regards, Neil ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Blind Buried Vias
Hi all, I have an application where I am creating a small PCB as the basis of an active electrode. The non-component side of the board is in contact with skin and exposed vias on this side of the board therefore must be avoided. In the previous generation of the design, the circuit was simple enough to allow me to perform routing purely on the top surface. However the new design is significantly more complex and I think I will need to move to a multi-layer board. I therefore need blind vias. The official PCB documentation says that these are not supported. Extract from section 2.2: Each via exists on all copper layers. (i.e. blind and buried vias are not supported) However I did find a number of threads on this topic in the archive, one of which is referenced below. However this was almost 1 year ago and there may have been further developments. http://www.seul.org/pipermail/geda-dev/2006-July/000135.html Is there any way to achieve this with pcb? Regards, Neil ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Circular Board Outline
Wow that's impressive !! A workaround and a fix all within a day. Thanks
guys.
Any idea when the next snapshot will be available with this fix?
On Sun, 2008-06-01 at 23:34 -0400, DJ Delorie wrote:
Is there a way to create circular PCBs in gEDA? I tried adding
connected arcs to the outline layer but these are ignored as it
seems to require connected straight line segments.
I checked in a fix for this:
Index: print.c
===
RCS file: /cvsroot/pcb/pcb/src/print.c,v
retrieving revision 1.51
diff -p -U3 -r1.51 print.c
--- print.c 20 Apr 2007 11:31:13 - 1.51
+++ print.c 2 Jun 2008 03:33:21 -
@@ -296,7 +296,7 @@ PrintFab (void)
for (i = 0; i max_layer; i++)
{
LayerType *l = LAYER_PTR (i);
- if (l-Name l-LineN)
+ if (l-Name (l-LineN || l-ArcN))
{
if (strcasecmp (route, l-Name) == 0)
break;
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gEDA-user: Circular Board Outline
Is there a way to create circular PCBs in gEDA? I tried adding connected arcs to the outline layer but these are ignored as it seems to require connected straight line segments. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
